Abstract: An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of isochronous channels. The isochronous data pipe is a programmable sequencer that operates on the stream of isochronous data as it passes through the isochronous data pipe. The isochronous data pipe is programmed by an application to perform specific operations on the stream of data before the data is either transmitted across the bus structure or sent to the application, thereby pre-processing and manipulating the data before it is delivered to its destination. The operations are performed on both the packet header and the data field of the data packet. The isochronous data pipe can be stopped and started on the occurrence of specific events.

Abstract: The information processing system is configured such that a portable information terminal and host information processing apparatus can connect via a bus. A program executed by a CPU of the portable information terminal is sent from the host information processing apparatus on the bus to the portable information terminal for storage in a volatile memory. Thus, the portable information terminal does not need a non-volatile memory.

Abstract: When the data bus is cut off from the CPU (1) and the transmission ready signal (TXRDY) is activated, the DMA control circuit (10) reads 32 bits of data at once according to the lead address of the destined area for storage in the DRAM (2) and the address width that are set by the CPU (1), and stores the data in the transmission buffer (16). The selector (17) selects 8 bits of data at a time from the transmission buffer (16), the data is written to the communication circuit (14) and thus output, the bus release request is cancelled, 8 bits of data is read at a time from transmission buffer (16), and the data is written into the communication circuit (14). When the transmission ready signal is provided once again, the above-described processing is repeated.

Abstract: An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices.

Abstract: A modular, scalable high-bandwidth computer architecture. A single integrated router/bridge ASIC defines a family of peripheral controllers that accept high-speed packet switched data, either for routing to other, identical controllers, or for routing to on-board PCI buses, or a combination of the two destinations, depending on the number of ASICs employed and their selectable configuration.

Abstract: An interface card is connected to a first data bus with a first bit width (for example, 16-bit width) and has a data storage section which is capable of storing data of a second bit width (for example, 32 bits of data) which is larger than the first bit width. Between the data storage section and an information processing device, data transmission is carried out via a second data bus with the second bit width.

Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Abstract: A method and apparatus are provided for implementing peripheral component interconnect (PCI) combining function for PCI bridges. A programmable boundary for a combined operation is selected. A write request is received. Responsive to the write request, checking for a combined operation hit is performed. Responsive to an identified combined operation hit, a combined operation is accepted. Checking for the selected programmable boundary for the combined operation is performed. Responsive to identifying the programmable boundary for the combined operation, the combined operation is launched to a destination bus. A programmable timer is identified for the combined operation. Responsive to the programmable timer expiring, the combined operation is launched to a destination bus.

Abstract: A method and system for adjusting the bandwidth allocated for isochronous data traffic on an interconnected data bus is disclosed. The present system uses an isochronous resource manager (IRM) to sense a bandwidth change request from a talker. The IRM instigates a bandwidth adjustment associated with the bandwidth change request to one or more bus bridge portals.

Abstract: A circuit comprising (i) one or more input paths, (ii) one or more output paths, and (iii) one or more switch circuits. The switch circuits may be configured to connect one or more of said input paths to one or more of said output data in response to one or more control signals. The present invention may be used to read and/or write data in one or more modes of operation such as 9-Bit Big Endian Write, 9-bit Little Endian Write, 18-bit Big Endian Write, 18-bit Little Endian Write, a 36-bit Write, 9-Bit Big Endian Read, 9-bit Little Endian Read, 18-bit Big Endian Read, 18-bit Little Endian Read, 36-bit Read or other mode.

Abstract: Deposit and extract instructions include an opcode, a source address, a destination address, a shift number, and a K-bit mask string. The opcode describes the operations to be performed upon a J-bit source string and an N-bit destination string. The source address points to the memory location of the J-bit source string. The destination address points to the memory location of the N-bit destination string. The shift number indicates the number of bits the J-bit source string is to be shifted to generate a shifted bit string. The combination of the shifted bit string with the N-bit destination string is conducted under the control of the K-bit mask string. The invention is useful for high speed digital data processing, such as that performed by devices operating under the IEEE 1394 protocol.

Abstract: A buffer circuit coupling an input bus having a first portion and a second portion to an output bus. Each of the first portion, the second portion, and the output bus carry data of a predetermined width. The buffer circuit comprises a first plurality of registers, a second plurality of registers, an unload counter, and a multiplexer. The first plurality of registers is coupled to store data from the first portion of the input bus. The second plurality of registers is coupled to store data from the second portion of the input bus and from a data order signal. The unload counter provides an unload count that selects one of the first plurality of registers and a corresponding one of the second plurality of registers. The multiplexer provides either the selected one of the first plurality of registers or the corresponding one of the second plurality of registers to the output bus. The multiplexer is responsive to the data order signal stored in the corresponding one of the second plurality of registers.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: A system provides a general purpose bus with programmable timing capability. As part of a microcontroller, this general purpose bus provides a mechanism for communication between general purpose peripherals connected to the bus and enables external devices to be connected with proper timing to the microcontroller. The general purpose bus controller includes programmable interface timing control logic which allows the bus cycle length for commands from a processor or other bus master to be programmed. Accordingly, memory and I/O read and write commands are customized to suit the timing requirements of peripheral devices connected externally to the microcontroller. A significant variety of peripheral devices may thus be coupled to the microcontroller without requiring additional glue logic. The general purpose bus controller further includes an echo mode which permits accesses to internal peripheral devices to be interpreted by a logic analyzer or other debugging equipment.

Abstract: A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

Abstract: A compact adapter for interconnecting a digital computer peripheral device that uses a Single Connector Attachment (“SCA”) to a conventional Small Computer System Interface (“SCSI”) bus. A SCA connector of the adapter mates with and engages a complementary SCA connector included in a peripheral device. The SCA connector is juxtaposed perpendicularly with a first face of a planar printed circuit board. A narrow width for the printed circuit board permits a disk drive mated with the adapter to fit within a space in a digital computer system adapted to receive a peripheral device. The compact adapter also includes an electrical power connector together with a first, conventional SCSI bus connector. Preferably, the adapter also includes a second, conventional SCSI bus connector having a different style from that of the first SCSI bus connector.

Abstract: A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The system also includes a device bus, which may or may not be coupled to the PCI bus by a south bridge. A device bus interface bypasses the north and south bridges, to provide a single-step interface to the device bus. This reduces the latency.

Abstract: A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data queues are provided in the bus bridge for transfer of data in both directions, and the speed of one of the buses is increased over the speed of the other one of the buses. In one embodiment, the first bus is a PCI bus and the second bus is an internal CPU bus.

Abstract: A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction.

Abstract: A serial interface circuit capable of converting a large volume of data into packets based on a predetermined standard for transmission and reception and capable of performing smooth transmission and reception processing, configured so that, in a reception operation, a request packet generation circuit generates a request packet and calculates the maximum length of data of the response packet with respect to the request packet transmitted and a transaction controller compares the maximum length of data maxpl with the remaining memory amount of the response use FIFO and, when the remaining memory amount is larger than the maximum length of data, transmits the request packet. When the remaining memory amount is smaller than the maximum length of data maxpl, the output of the request packet to the link core, that is, the transmission of the request packet to the other node, is temporarily suspended until the remaining memory amount becomes larger than the maximum length of data maxpl.

Abstract: A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. In a preferred embodiment, the processor bus has a first integer number of significant data lines. The processor is responsively coupled to the processor bus and includes a first decoder for decoding a first set of instructions received over the set of processor data lines, The first set of instructions each contains a second integer number, less than the first integer number, of significant bits.

Abstract: A communication system for transferring (Peripheral Component Interconnect) PCI and non-PCI data over a non-PCI bus is disclosed. The system bus is a non-PCI bus having an address bus and a data bus for communicating addresses and data. A PCI-compatible peripheral is coupled to the non-PCI bus for transmitting and receiving PCI-compatible data. A non-PCI device is also coupled to the non-PCI bus for transmitting and receiving non-PCI data. In addition, a slave device is also coupled to the non-PCI bus for receiving and transmitting non-PCI data and PCI data. A byte size control line capable of being driven by the PCI-compatible peripheral and the non-PCI device is coupled between the PCI-compatible peripheral, the non-PCI device, and the slave device for indicating whether data appearing on the data bus is from the PCI-compatible peripheral or the non-PCI device, and for indicating how many bytes on the data bus are actually valid, if the data appearing on the non-PCI bus is from the non-PCI device.

Abstract: A low pin count, moderate speed serial data bus that has a variable width for the transfer of data between devices of a computer system. The serial data bus can be selectively configured to be 1-bit, 4-bit, 8-bit or 16-bit wide. Data (including bus commands and addresses) carried by wider parallel buses are serialized into data blocks, which are then transferred by the serial data bus at a high speed. One feature of the present invention is that the pin count requirement for the present invention is low: only four control pins are required for controlling the data transfer mechanisms of the data bus. Another significant feature of the present invention is that the host and companion interfaces of the serial data bus can have non-matching widths. To allow for host and companion interfaces with non-matching widths, an initialization protocol is used to establish the effective width of the data bus at power-on reset.

Abstract: A data processing system provided with a CPU for reading at units of 32 bits per read cycle, a font card that requires read accesses of either 16 or 8 bits per cycle by accessing a specific address area, and an address specifying control circuit positioned between the CPU and font card. When accessing the specific address area, the CPU provides information on the data width for access and the low-order portion of the address to the address specifying control circuit. Based on this data, the address specifying control circuit outputs the low-order portion of the address to the font card for accessing the font card at the prescribed unit of bits, regardless of the address data output from the CPU. For example, when performing a 16 bit read, the second to lowest order bit (ADR01) is set to 0 in the first read cycle, and the low-order 16 bits of data is considered valid. In the second read cycle, ADR01 is set to 1, and the high-order 16 bits of data is considered valid.

Abstract: A method of servicing a processor array of a computer system by quiescing a processor selected for maintenance and removing the selected processor from a processor pool used by the computer's operating system. The selected processor is then powered down while maintaining power to and operation of other processors in the processor array. The selected processor may be identified as being defective, or may have been selected for upgrading. The processor array may include several processor clusters, such that the quiescing, removing and powering down steps apply to all processors in one of the processing clusters. The operating system assigns one of the processors in the processor array to be a service processor, and if the service processor is the processor selected for maintenance, the OS re-assigns the service processor functions to another processor in the processor array.