Abstract: A method for transmitting digital data, which is continued in data frames of variable lengths, from a first data bus to a second data bus, which is operated asynchronously with respect to the first data bus and is controlled by a microprocessor. The method has the below listed steps. The data is written from the first data bus to a memory of a settable size. A memory control unit informs the microprocessor, in the form of an interrupt, when the memory is full or when the end of a data frame is reached. The microprocessor determines from the memory control unit the quantity of data to be read from the memory, reads the data from the memory, and sets the size of the memory. Finally, the microprocessor acknowledges reception of the data block to the memory control unit.

Abstract: A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

Abstract: A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer.

Abstract: A semiconductor manufacturing apparatus includes: a calculation unit having at least one computer for processing semiconductor design information; a control unit for controlling radiation of an electron in accordance with a processing result of the semiconductor design information; a writing unit for radiating an electron in accordance with instructions of the control unit; and at least one storage device. The semiconductor manufacturing apparatus permits a communication between the storage device, the calculation unit, the control unit, and the writing unit. The semiconductor manufacturing apparatus further includes a communication pass through which the storage device can be controlled.

Abstract: Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system.

Abstract: A method (and system) of improving performance of a multiprocessor system, includes proactively flushing and locking an arbitrarily-sized region of memory out of caches of the multiprocessor system.

Abstract: A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of the operation. The status of the condition setting indicator determines whether or not multibit condition codes are set. When they are to be set, they are set depending on the results of carrying out the operation for each lane.

Abstract: An error correction code mechanism for the extensions to the peripheral component interconnect bus system (PCI-X) used in computer systems is fully backward compatible with the full PCI protocol. The error correction code check-bits can be inserted to provide error correction capability for the header address and attribute phases, as well as for burst and DWORD transaction data phases. The error correction code check-bits are inserted into unused attribute, clock phase, reserved, or reserved drive high portions of the AD and/or C/BE# lanes of the PCI-X phases.

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.

Abstract: In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.

Abstract: The invention generally relates to a method, apparatus, and system to change one or more communication pathways in a processor without changing a physical component layout in the processor. For example, in an embodiment, the invention generally relates to a routing agent to change one or more communication pathways in a processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to the following method. The method comprises sending a control signal to one or more components within a processor to change one or more communication pathways in the processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to a method of changing the bandwidth between a processor and a device exterior to the processor without changing the physical component layout in the processor.

Abstract: An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. external pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test dat or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SERCLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control.

Abstract: Methods and associated structure for providing a substitute, predetermined, fixed length when transferring burst transactions from one device to another through a bridge device where the burst transaction has an indefinite length specified. In one exemplary preferred embodiment, an AMBA AHB bus bridge slave device recognizes initiation of burst transactions of a indefinite length and translates the indefinite length burst transactions on the first bus into appropriate bus transactions for application to a second bus or device having a predetermined fixed length for the transferred the burst transactions. In a second embodiment, a slave device acting as a bridge receives a burst of indefinite length and translates the bus request into one with a predetermined fixed length for application to a device controller.

Abstract: An apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses are described. Data transfers between a memory and a PCI-bus pass through a PCI-side aligner unit, PCI FIFO, Endian swap logic, and PCI-bus interface unit under the control of a PCI FIFO controller. The PCI-side aligner unit properly aligns the data while communicating data with the memory's bus on a word-at-a-time basis, and communicating data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the memory's bus. The Endian swap logic properly orients the data in big or little Endian orientation. The PCI-bus interface unit communicates data with the PCI-bus on a word-at-a-time basis, and communicates data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the PCI-bus.

Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Abstract: A system and method for data processing includes packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and simultaneously operating on the elements in a register in a single cycle using the same operand. The elements can be independent of each other, and the sizes of the elements in a register can differ from each other. Moreover, a relatively large element can be split across multiple registers. In an exemplary application, a data stream representing two images can be simultaneously processed using the same number of registers as have been required to process a single image. Or, a single image can be processed approaching N-times faster, where N is the number of elements per register. In any case, the present invention results in a significant increase in processing efficiency.

Abstract: A tunnel device for an input/output node of a computer system. A tunnel device includes a first interface, a second interface and a control unit. The first interface may receive a plurality of data bytes associated with a command packet on a first external input/output bus. The second interface may be coupled to the first interface by an internal data path configured to convey up to a maximum number of data bytes in a given cycle. The control unit may be coupled to control the conveyance of the data bytes from the first interface to the second interface upon the internal data path. The first interface may further align the smaller number of data bytes on a corresponding number of designated bits of the internal data path with no intervening invalid data bytes when conveying a smaller number of data bytes than the maximum number of data bytes.

Abstract: Once attached to a slot of a personal digital assistant PDA, a card module CM executes an application-specific program and transmits a result obtained thereby to the personal digital assistant PDA. The thus received execution result is outputted from an output part. Accordingly, the output part can be provided for shared use among several card modules CM for output of the execution result.

Abstract: A method and apparatus in which an arbiter links to a processor having a flexible architecture, and the processor connects to a device through a point to point bus.

Abstract: An entertainment apparatus comprising a peripheral device and a controller for controlling the peripheral device. The peripheral device and the controller are connected each other by an address bus and a data bus. The peripheral device which receives a DMA acknowledge signal from the controller carries out 32-bit DMA transfer using lower 16 bits of the address bus and the data bus, during assertion of the DMA acknowledge signal.

Abstract: A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer.

Abstract: A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.

Abstract: A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register and which simultaneously transfers two data, in which, in the case where an LDCTX instruction which is the instruction for loading data to more than two register is executed, a combined data of two data each of which is to be loaded in different register is transferred from the operand access unit to the data register, and high order 4 bytes of data and low order 4 bytes of in the data register are simultaneously transfers to two register through two data transfer paths, respectively, and in the case where an STCTX instruction which is the instruction for storing data from more than two register is executed, contents of the two registers are simultaneously transferred to a high order 4 bytes and a low order 4 b

Abstract: The method maps at least one intermediate data register of a first data width into the address space of the computer bus. The computer bus writes data to an intermediate data registers with write strobes corresponding to data subsets of a second smaller data width equal to the data width of the device registers. The IDE controller then transfers data from the intermediate data register to the device registers in subsets of the device register data width in a fixed order of device registers. Similarly, for reads of the device register, the computer bus writes data to a read selection data field of an intermediate data register. Each bit of the read selection data field corresponding to one device register. The IDE controller transfers data from the device registers corresponding to bits of the read selection data field having a predetermined first digital state to an intermediate data register in a fixed read order of device registers.

Abstract: Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.

Abstract: Interface logic is disclosed. The interface logic comprises a first address decoder, a first set of mode logic coupled to the address decoder and a first selector coupled to the first set of mode logic. The interface logic is adaptable to connect the programmable logic to the system interconnect via one of a plurality of access modes supported by the system interconnect.

Abstract: Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

Abstract: In a data processing system, the effective speed of transferring data packets between a data processing unit and various other devices with different performance characteristics is improved by a data transfer method and a packing and buffering device, thus offloading the data processing unit or the various devices. FIFO buffers provide intermediate storage of transfer data, and packing and unpacking modules ensure efficient use of bus widths that are different on the data processing side and the device side. Data packet transfer control is effected using a control and status module with a common byte counter, and a direct transfer is facilitated via a supplementary direct data path between the data processing unit and other devices.

Abstract: This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus (2) links the flash memory (1) to the microprocessor (3), said flash bus (2) having a width m which is greater than the width n of the microprocessor's data bus (8). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers (4) connects the flash bus (2) with the data bus (8) of the microprocessor (3) for performing the width conversion.

Abstract: In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.

Abstract: A method and system for adjusting the bandwidth allocated for isochronous data traffic on an interconnected data bus is disclosed. The present system uses an isochronous resource manager (IRM) to sense a bandwidth change request from a talker. The IRM instigates a bandwidth adjustment associated with the bandwidth change request to one or more bus bridge portals.

Abstract: A method and apparatus is provided for selecting one of a plurality of data bus width configurations of a memory device using a logic circuit. The logic circuit includes a plurality of I/O circuits each connected to at least one of a plurality of memory arrays, and at least one address selection data path connected to at least one of the I/O circuits. A signal transmitted on the address selection data path selects one of a plurality of arrays from which to access data for each I/O circuit. When in a larger bus width configuration, each of the I/O circuits is connected to a data bus line. When in a smaller bus width configuration, a subset of the I/O circuits is connected to the data bus line and data from the plurality of memory arrays is output through the subset of I/O circuits, which selectively switch outputs between memory array inputs.

Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Abstract: Disclosed herein is a apparatus and method for packing a 16-bit number into an 8-bit result byte. The method and apparatus utilize a parallel processing right shift circuit and a filter to obtain desired results. The parallel processes are comprised of a plurality of multiplexers capable of discretely analyzing smaller groups of bits. In this manner, higher throughput may be obtained than previously known.

Abstract: An interface allows communication between a host device coupled to a host bus and a target device coupled to a target bus. First, the interface receives the address of the target device from the host device via the host bus, where the address has a first width. Next, the interface converts the received address from the first width into one or more address components each having a second width. Then, the circuit accesses the target device by driving the one or more address components onto the target bus. Such an interface allows for a simple, direct communication path between the host bus bus, such as a system bus, and a target bus, such as an LPC bus. The interface consolidates several tasks into one general purpose interface, providing a savings in components used, design complexity, and overall cost of implementation. Further, the length of time required for communications between interfaced busses is substantially reduced.

Abstract: A dynamic perimeter circular bus method and system includes a serial interconnect and elements connected in a serial loop through the serial interconnect. In operation, a variable sized loop word is transferred between elements along the serial loop. A sync character of the loop word is transferred from element to element along the serial loop. The sync character is indicative of the beginning of the loop word. At least one present character of the loop word after the sync character is then transferred from element to element along the serial loop. A present character is then asserted at an element to indicate that a data word follows the asserted present character in the loop word. The data word from the element is then put on to the loop word after the asserted present character thereby increasing the size of the loop word. The data word of the loop word is then transferred from element to element along the serial loop.

Abstract: The bus width of the data bus among blocks for transferring data among respective blocks such as the memory control block, the error correction block, and the host I/F block is 32-bit width, and the bus width of the memory data bus for transferring data between the buffer memory and the memory control block is 64-bit width, whereby an access to the buffer memory is performed by the unit of 64 bits, while respective block processings are performed by the unit of 32 bits out of the 64 bits. Therefore, 32-bit data transferred through the data bus among blocks are always valid data, whereby the access rate from respective blocks in the system to the buffer memory can be increased.

Abstract: A switching router memory map is organized as 64-bit wide double words. The bi-directional data bus is only 32-bits wide, so the Least Significant Words (LSW) are mapped to the even addresses and the Most Significant Words (MSW) are mapped to the odd address. When the host writes to the even address the 32-bit data is stored in the bidirectional data bus buffer. When the host writes to the odd address the entire 64-bit double word access is posted to the appropriate global access bus. When a read operation is performed from an even address the entire 64-bit double word access is performed by the appropriate global access bus. The LSW is available on the bi-directional data bus address data pins and the 32-bit MSW is buffered within the bi-directional data bus. The host can access the MSW by performing a read from the odd address.

Abstract: A high-speed block transfer circuit includes a processing unit that can carry out dummy symbol processing using a CPU block transfer instruction based on a condition discriminant “DE≦HL+(y−x) [byte] (x≠y)” where “HL” represents an initial address of a block transfer origin, “DE” represents an initial address of a block transfer destination, “x [byte]” represents a block transfer data fixed length of an original instruction, and “y [byte]” represents a corresponding bus sizing length.

Abstract: A FIFO memory device for use in data transfer between data processing apparatuses having different data bus widths, has an input circuit 11 with a data bus width of k bits, an output circuit 12 with a data bus width of N×k bits (where N>1) that outputs data within the FIFO memory device, a writing pointer 2 that points to a data writing address of the FIFO memory device, a reading pointer 4 that points to a data reading address of the FIFO memory device, and a valid/invalid indicating circuit 6 that indicates whether or not data output to the output circuit 12 is valid.

Abstract: The present invention provides a bus architecture for a data processing system that improves transfers of vector data using a vector transfer unit (VTU). An external bus is coupled between the vector transfer unit and the memory. The external bus includes a system command bus that is used to transmit a data transfer command. The command is based on a corresponding vector transfer instruction in the application program, such as load vector data or store vector data. The commands for transferring the data elements include a burst read command and a burst write command. A variable number of data elements may be transferred, according to the user's requirements. The system command bus is also capable of transmitting a packing ratio that indicates the number of data elements that fit in the width of the external bus. This allows the entire bandwidth of the external bus to be used during vector data transfers.

Abstract: An interface for interfacing a plurality of first data buses each having an N-bit data width and a second data bus having a 2N-bit data width. The interface includes a selection circuit and first and second conversion circuits. The selection circuit outputs the data on a data bus selected from the first data buses in response to a selection signal. The first conversion circuit pre-fetches first and second N-bit data on the selected data bus in response to a read control signal and transfers 2N-bit data comprised of the pre-fetched first and second N-bit data to the second data bus. The second conversion circuit converts the 2N-bit data on the second data bus into N-bit data in response to a write control signal and transfers the N-bit data to a data bus selected from the first data buses.

Abstract: A system for maintaining data flow between buses is provided wherein the bandwidth of a first bus is less than the bandwidth of a second bus. The bandwidth of a bus is based on the clock speed of the bus and the bit width of the bus. The system includes a first bus having a first clock rate and a first bus-width, a second bus having a second clock rate and a second bus-width, and control logic. The control logic receives data from the first bus and transfers the data to the second bus. The control logic may comprise a set of storage devices selectively coupled to the first bus and the set of storage devices may be addressable memory. The control logic may further include a first bus control logic for writing data to the set of storage devices and a second bus control logic for reading data to from the set of storage devices.

Abstract: In a bus connection circuit for connecting buses having different bit widths, number of clock cycles can be reduced, and hardware amount can be reduced. The bus connection circuit connects buses of mutually different bit widths having control lines and data lines connected to a bus master unit and bus slave unit. The control command lines of the buses are connected to a common control command bus to control command information on the buses. The data lines of the buses are connected via a data conversion unit to perform bit width conversion between the buses. An arbitration circuit is provided to perform arbitration of bus right for the buses in response arbitration request. Upon transfer of data between the buses, by obtaining of bus right by sender side bus, write access and rear access between buses is performed.

Abstract: An apparatus includes an instruction word storage for storing a plurality of general instruction words and extended instruction words, a temporary storage unit including a plurality of buffers for pre-fetching and storing the plurality of instruction words from the instruction word storage, an instruction word search unit for receiving and decoding the plurality of instruction words pre-fetched and outputting a position signal of a general instruction word and the positions of one or more successive extended instruction words stored in the temporary storage a selector for selecting a buffer in which a general instruction word is stored and outputting the general instruction word sequentially, according to the position signal a general instruction word parser for receiving a general instruction word from the selector and outputting a plurality of control signals for executing the general instruction word simultaneously, an extended data parser is provided for performing an operational processing of operands of

Abstract: An information processing system, which has a computer, scanning apparatus, and printing apparatus using an IEEE 1394 bus as a communication interface, searches for an available channel in order to assign a predetermined number of channels to an apparatus having operation priority. When no available channel is found by the search, the system determines whether any of channels allocated by an other apparatus can be reassigned to the high-priority apparatus. If any channels are determined to be reassignable, the system reassigns the channels to the high-priority apparatus. This makes it possible to flexibly assign channels in an isochronous transfer serial bus and transfer information desired by the user.

Abstract: An apparatus comprising a first bus, a second bus, a memory and one or more interconnections. The memory may be connected to the first bus and the second bus and may be configured to transfer data over the first bus and the second bus. The one or more interconnections may be connected between one or more data lines of the first bus and the second bus to control a bit-width of the first and second buses.

Abstract: An external bus controller which is configured such that, when an external device having a data width smaller than that of an external bus is connected to the external bus, the signal lines of the external bus can be freely selected. This external bus controller comprises a first exchange, which converts the data width of input/output data so as to compensate for differences between the data width of the internal bus and the data width of an external device, and a second exchange, which exchanges signal lines between the first exchange and the used signal lines. The signal lines to be used are set for each external device using configuration pins or similar means.

Abstract: In a data processor including a master circuit that issues an access request and slave circuits that perform processing in response to the access request received from the master circuit, the disclosed invention enables the master circuit to access all data areas of the slave circuits even if the master circuit does not have an access command in data size suitable for accessing the slave circuit. An access size control unit that can convert access size input from the master circuit to data size in which the slave circuit accepts access is installed between the master circuit and the slave circuit. The access size control unit retains at least one address for access size setting. As the master circuit accesses the appropriate address for access size setting, the access size conversion procedure can be carried out.

Abstract: A multi-bus computer system is adapted for dynamic load balancing. The computer system includes a plurality of expansion slots, a first expansion bus, a second expansion bus, and a bus switching mechanism to assign at least one of the plurality of expansion slots between the first expansion bus and the second expansion bus. Selection of the particular expansion bus may be controlled by a bus selection signal based on a type of device in the particular expansion slot, the speed of the device in the expansion slot, the bitsize of the device in the expansion slot, or availability of each expansion slot.