Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract: A network device includes a first port to allow the device to communicate with other devices on an expansion bus. The device also includes a second port to allow the device to communicate with devices on a second bus and a memory to store data. A processor receives an interrupt signal from an expansion device on the expansion bus and generates an indicator of completion. The processor then inserts the indicator into a transaction queue after the set of data.

Abstract: A low-power audio CD player for portable computers permits operation of the CD-ROM subsystem when power is not being supplied to the computer subsystem. In one embodiment of the invention, the computer subsystem comprises a system CPU, a digital-audio generating circuit, a digital computer bus coupling the CPU and the digital-audio generator circuit, and a digital computer bus controller. The CD audio subsystem comprises an audio device capable of playing an audio CD and coupled to the digital computer bus controller, an audio amplifier circuit coupled to the audio device, and an audio interface coupled to the digital computer bus in parallel to the digital computer bus controller and the audio device. The audio interface is adapted to generate signals to operate the audio device and play the audio CD when power is not being supplied to the computer subsystem or to the CPU.

Abstract: A method and apparatus for creating USB peripheral device report descriptors: A short, compressed, report descriptor is stored in a peripheral device. This short report descriptor is transmitted to a USB wireless bridge and combined with templates stored in the bridge to create a USP report descriptor. Power is saved because less time is required to transmit the short report descriptor than would be required to transmit a full USB report descriptor. Hardware is also saved in the peripheral device since less memory is required to store the short report descriptors as compared to storing a full USB report descriptor.

Abstract: A bus controller and a control method are used in a computer system. In a bus controller, a bus controller main circuit issues a first signal to the central processing unit in response to a bus configuration cycle for indicating the presence of a first-level bus that the first group of components is coupled to. A virtual bridge device issues a second signal to the central processing unit in response to the bus configuration cycle for indicating the presence of a second-level bus that the second group of components is coupled to. A path selection unit electrically connected to the first and second groups of components via the first-level and second-level buses, respectively, outputs a normal device select signal to one of the first-level and second-level buses while outputting an invalid device select signal to the other of the first-level and second-level buses according to address data of a transaction.

Abstract: A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it has connections for connecting at least two data buses and can output data received by a first data bus either onto the same data bus or onto another data bus immediately or later. Therefore, the data transmission device can be used selectively, alternately or simultaneously as a DMA controller and a bus bridge. It also has additional functions unrelated to DMA controllers and bus bridges.

Abstract: A system includes a first device; an Integrated Drive Electronics (IDE) bus; and a data storage device having a first task file register, the data storage device being coupled to the first device via the IDE bus for storing data within the data storage device as received from the first device via the IDE bus, or for passing the data stored within the data storage device to the first device via the IDE bus according to commands passed from the first device via the IDE bus. The data storage device is further for controlling predetermined operations of the first device by storing different values within the first task file register, and the first device is for reading the first task file register of the data storage device via the IDE bus and performing the predetermined operations according to the different values.

Abstract: The data processing device according to the invention comprises a first processing unit (1) linked to a first bus (5), a second processing unit (2) linked to a second bus (6), a first bus master (3) linked to the first bus (5), a second bus master (4) linked to the second bus (6), a first and a second communication channel (7, 20, 8, 21) linking the first and the second bus master (3, 4) with each other, and a control unit (9) controlling the data transfer between the first and the second bus master (3, 4) via the first and the second communication channel (7, 20, 8, 21).

Abstract: A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a first set of switches. The first set of switches is configured to route communications between the root complex device to either a second connection point of the first GPU via a second set of switches or to a first connection point of a second GPU. The second set of switches is coupled to a second connection point of the first GPU. The second set of switches is configured to route communications to and from the second connection point of the first GPU and to either the root complex device via the first set of switches or to a second connection point of the second GPU.

Abstract: A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.

Abstract: A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and a high speed interface. A preferred embodiment of the invention is a bus transceiver on a multi-chip module.

Abstract: An interruption control system includes a PIC, an APIC and a power management unit disposed in a south bridge chip of a computer system. In response to the triggering of an interrupt status indicating signal received through an interrupt status indicating pin of a north bridge module or by the triggering of a peripheral device coupled to the south bridge chip, the PIC sends an interrupt signal to the CPU via an interrupt request signal pin when the computer system is in a PIC mode. The APIC is disabled when the computer system is in the PIC mode, and enabled when the computer system is in an APIC mode to generate a memory write cycle message to the CPU in response to the triggering of the peripheral device. The power management unit is optionally triggered with the interrupt signal or the interrupt status indicating signal to awake the CPU.

Abstract: A method and computer system for accessing initialization data stored in a boot memory space. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the memory space and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.

Abstract: A smart storage device that can be either used in conjunction with a conventional storage device or integrated into a conventional storage device to become a smart storage device is disclosed. The smart storage device of the present invention includes a transmission interface, a processor, a control interface, a storage medium, an input interface, an input device, a response interface, and a response device. The processor further includes a memory, a data transmission and medium control module, and a monitor, analysis and response (MAR) module. The MAR module is for monitoring and analyzing the operation requests and responding accordingly. When used in conjunction with a conventional storage device, the external smart storage device includes a host-end transmission interface, a processor, a device-end transmission interface, an input device, an input device, a response interface, and a response device.

Abstract: Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.

Abstract: Systems and methods for coordinating the interoperability of devices with varying capabilities are disclosed. A host device may inquire as to the capabilities of a storage device in a storage network. A routing device may receive this response, and if the routing device has a higher capability than the storage device the routing device may convert the response to a response that reflects the higher capabilities of the routing device before sending the response on to the host. However, if the storage device has a higher capability than the routing device, the routing device may pass the response through to the host unaltered so the host may take advantage of the capabilities of the storage device. Alternatively, the router may convert the response to a response that reflects the lower capabilities of the routing device before sending the response on to the host.

Abstract: A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

Abstract: A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the scaling features of the PCI Express standard. During operation of the computer system, the status of the endpoints is detected and unused links (or unused portions of links) are rerouted to other endpoints.

Abstract: A system and method of initializing a core processing circuit are disclosed. The core processing circuit is held in a reset state while a reset vector is loaded to one or more registers at a boot address associated with the core processing circuit. The reset vector is loaded from a system memory through a host bridge. The reset vector comprises one or more instructions to initialize the core processing system upon release from a reset state.

Abstract: A large multimaster I2C bus system is partitioned into smaller bus segments. The bus segments are connected by bridges that isolate the segments and direct selected transactions and commands between the segments. The bridge may handle bus segment error conditions and particularly a hang on the Port B bus by attempting to cause any device on the bus segment to respond after the bus bridge has attempted to acquire the segment for a first predetermined period of time. If the bus responds within the first predetermined period of time, the bus bridge resets the bus segment.

Abstract: The specification may disclose a computer system and related method of checking for proper operation of a computer system, and taking corrective action if the computer system is not functioning properly. A monitoring device within the computer system may be programmed to actively monitor computer system operation, and take corrective action upon a failure of one or more computer system components.

Abstract: One embodiment of the present invention provides a flexible peripheral access protection mechanism within a data processing system (10) in order to obtain a more secure operating environment. For example, the data processing system may include a combination of secure (12) and unsecure bus masters (14, 15) needing to access shared peripherals (22, 24). One embodiment allows for the dynamic update by a secure bus master (12) of access permissions corresponding to each unsecure bus master for each peripheral. A secure bus master is therefore able to establish which unsecure bus masters have permission to access which peripheral in order to protect the data processing system from corruption due to errant or hostile software running on unsecure bus masters. Through the use of a bus master identifier (36), access to the requested peripheral is either allowed or denied based on the permissions established by the secure bus master.

Abstract: A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.

Abstract: A bus bridge for coupling between a first bus and a second bus includes: a number of data buffers for a particular request type; a counter for monitoring a number of requests of the particular type received at the bus bridge from the first bus for access to the second bus; and override logic. Each request of the particular type requires one data buffer of the number of data buffers for the particular request type. The override logic determines when the monitored number of requests of the particular type exceeds the number of data buffers for the particular request type at the bus bridge, and responsive thereto, initiates a request termination signal at the bus bridge to terminate a received request of the particular type. When request coherency is maintained employing snooping, the request termination signal is a retry snoop response signal output from the bus bridge.

Abstract: A high assurance processing system includes a plurality of data processors coupled in parallel, a bridge coupled to the plurality of data processors, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to the bridge through the input/output processor for processing by the parallel data processors, which generate redundant effector data for comparison by the bridge to detect errors. If data matches are found, data is transmitted to the effector.

Abstract: A method is provided for utilizing four error correcting code (ECC) pin connections of a PCI/PCI-X bus for one of Grant (GNT) and Request (REQ) pin connections. The method determines a mode of the PCI bus to be PCI-X Mode 1, PCI-X Mode 2, or PCI. If the determined mode is PCI-X Mode 2, the four ECC pin connections are used as ECC pin connections, and if the determined mode is PCI or PCI-X Mode 1, each of the four ECC pin connections is used as a GNT pin connection or a REQ pin connection.

Abstract: An integrated device (e.g., an integrated PCI bridge device) buffers received PCI bus strobe signals and distributes strobe signals for PCI receive data relative to the PCI data lines, enabling all PCI receive data to be latched using locally-generated PCI strobe signals generated based on the same PCI bus strobe signals. In addition, data line latch modules having primary and secondary flip-flops enable the PCI receive data to be held for an entire clock cycle, optimizing conversion between a PCI clock domain and a local clock domain of the PCI bridge device. A transmission circuit also can be configured to transmit data according to either double data rate (DDR) mode or quad data rate (QDR) mode in an efficient manner.

Abstract: Method, apparatus and system for controlling input/output adapter data flow operations in a data processing system that includes at least one of a traffic class mechanism in conjunction with virtual channel resources so as to be able to associate Load/Store and DMA flows to/from an input/output adapter, and a relaxed ordering mechanism for associating a relaxed ordering bit to Load/Store operations to an input/output adapter. Functionality for controlling the input/output adapter data flow is provided in a host bridge that connects the input/output adapter to a system bus of the data processing system.

Abstract: An interface module is operatively connected to a Fieldbus process control network and to at least one non-Fieldbus process control network to facilitate the exchange of process control information between the networks. The interface module stores a database in which the process control parameters of the function blocks in the field devices of the Fieldbus process control network are mapped to corresponding process control parameters of the non-Fieldbus process control network. Once the Fieldbus process control parameters are mapped to the non-Fieldbus process control parameters, the interface module is adapted to transmit request messages on the Fieldbus process control network to the Fieldbus field devices for the current values of the process control parameters, receive response messages from the Fieldbus field devices, and store the current values of the process control parameters in the database.

Abstract: In one aspect, an interface circuit for interfacing a Parallel ATA bus to a storage device. The interface circuit including a storage device controller in communication with the storage device to control a flow of information between the storage device and a Serial ATA bus. The Serial ATA bus to carry information having a Serial ATA format. A bridge circuit configured as a host bridge to interface between the Serial ATA bus and the Parallel ATA bus. The host bridge to convert Serial ATA information to Parallel ATA information and to convert Parallel ATA information to Serial ATA information.

Abstract: An interface module is operatively coupled to a Fieldbus process control network and a Modbus process control network to facilitate the exchange of process control information between the networks. The interface module stores a register map database in which the process control parameters of the function blocks in the field devices of the Fieldbus process control network are mapped to register numbers of the Modbus process control network. Once the Fieldbus process control parameters are mapped to the Modbus registers, the interface module is adapted to transmit request messages on the Fieldbus process control network to the Fieldbus field devices for the current values of the process control parameters, receive response messages from the Fieldbus field devices, and store the current values of the process control parameters in the register map database.

Abstract: A computer subsystem of a computer includes a CPU, RAM, display, storage device, input device(s), and a digital-audio generating IC. A CD-ROM subsystem of the computer includes a CD-ROM drive and CD-ROM control buttons for controlling CD-ROM drivers operation while playing audio CDs. An audio-interface IC of the CD-ROM subsystem couples a bus of the computer subsystem to the CD-ROM drive, and to the control buttons. The audio-interface IC, in one operating mode, relays commands and data between the bus and the CD-ROM drive. A second operating mode permits turning the computer subsystem off while the audio-interface IC autonomously responds to the control buttons and transmits commands to the CD-ROM drive for playing an audio CD.

Abstract: A mass storage device motherboard or secondary board includes a bridging circuit. The bridging circuit converts signals from the mass storage device into USB signals. The bridging circuit can be provided by a chip that converts ATA/ATAPI signals into USB signals.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: Bus logic couples plural master logic units with plural slave logic units to enable data transfers. Each master unit performs an address transfer which, when received by a specified slave unit, causes a data transfer between that master unit and said specified slave unit. Each slave unit must complete a data transfer prior to performing any further data transfers. A slave unit performs data transfers in an order which differs from that in which associated address transfers were received by that slave unit. In response to an adress transfer, the bus logic couples a master unit with a slave unit to enable a data transfer. The bus logic determines whether propagation of an address transfer may cause a deadlock situation where data transfers can not take place between affected master and slave units and, if so, to prevent propagating that address transfer.

Abstract: A method for facilitating read completion in a computer system supporting write posting operations. A posted memory write and its associated tag both need to be buffered, where the associated tag is designated to a master of a local bus originating the posted memory write. When a read request moving in an opposite direction of the posted memory write is detected, the read request is checked to identify which master of the local bus is addressed. A destination tag is then assigned to the read request contingent upon the currently addressed master. Further, the destination tag of the read request is compared with the associated tag of the posted memory write. If the destination tag of the read request differs from the associated tag of the posted memory write, the read request can be completed directly regardless of the outstanding posted writes.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A bus bridge for coupling between a first bus and a second includes: at least one data buffer; data load logic and data unload logic. The data load logic places received data in the at least one data buffer, wherein the data is received at the bus bridge from across the first bus in a first data ordering. The data unload logic automatically translates the received data from the first data ordering to a second data ordering during unloading of the data from the at least one data buffer for transfer across the second bus, wherein the first data ordering and the second data ordering are each a different one of a linear data ordering and an interleaved data ordering.

Abstract: In a method for exchanging data between several stations belonging to various data bus systems. The data bus systems are spatially and physically separate from each other. The stations exchange data via control devices which are respectively associated with a data bus system and which are interconnected by means of a faster data bus, which said bus is not busy.

Abstract: A communication system and method with configurable posting points have been described.

Abstract: An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported by an external recipient into a second predetermined command recognizable/supported by the external recipient. Such arrangement is further arranged to control a predetermined ordering of the converted second predetermined command with respect to other commands. The command translation/ordering unit may be arranged to control ordering such that all commands handled prior to the first predetermined command are completed prior to completion of the converted second predetermined command. Further, the command translation/ordering unit may be arranged to control ordering such that all commands handled after the first predetermined command are completed after completion of the converted second predetermined command.

Abstract: A data processing apparatus comprises a master device 150, 160, 170, 180, a slave device 110, 120, 130 and a communication bus 140 via which transaction requests are passed from master to slave. A transaction annotator of the master device generates transaction identifiers having a master identifier portion and a priority request portion. The slave device determines an order of servicing of transaction requests in dependence upon transaction ordering requests at least partially derived from the master identifier portions and in dependence upon priority values specified in the priority request portions.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: An integrated circuit implementing a storage-shelf router, used in combination with path controller cards and optionally with other storage-shelf routers, to interconnect SATA disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop. Various embodiments of the present invention provide a tunneling mechanism through the storage-shelf interface provided by one or more storage-shelf routers within a storage shelf to enable external processing entities to directly access various components within the storage shelf. In one embodiment of the present invention, a WRITE-BUFFER command and a READ-BUFFER command are added to the command interface supported by storage-shelf router. These commands are exchanged via the FCP protocol over the fiber channel in the same manner that SCSI commands are packaged within the FCP protocol.

Abstract: Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active, then disabling of a selectively hidden device interfaced with another active bus provides a bus number to the newly active bus. For instance, if a graphics capability is added to a computer system through a PCI bus, a PCI bridge associated with a second PCI bus is disabled so that the PCI bus number for the portion of the second PCI bus between the chipset of the computer system and the PCI bridge is available for use as the PCI bus number for the PCI bus associated with the graphics capability. The PCI bus number for the portion of the second PCI bus between the PCI bridge and existing peripheral devices is available for use for both portions of the second PCI bus.

Abstract: A bridge-chip may interface a Universal Serial Bus to a mass storage device. Communications of the universal serial bus may be examined to determine a command block wrapper (CBW) of a bulk transport protocol and if a configuration command block (CFGCB) of the CBW may include a signature associated with the bridge-chip. A command of the CFGCB might then be performed by the bridge-chip upon determining the signature. This procedure might be used to get or set configuration or descriptor data of the bridge-chip separate from other USB configurations operations.

Abstract: The invention relates to a method for exchanging data between a plurality of subscribers (K1, K2, K3, K) by means of a data bus. The subscribers are located in their totality in at least two spatially and physically separate subordinate data buses and exchange, in the interval in which the more rapid data bus is not busy, data via control devices that are associated with every subordinate data bus and that are interconnected via a more rapid data bus.

Abstract: In at least some embodiments, a computer system comprises a central processing unit (“CPU”), a bridge device coupled to a main memory, and a cache controller coupled between the bridge device and the CPU. The computer system further comprises a cache memory coupled to the cache controller and providing memory space to the CPU, wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using a first protocol and the bridge device communicates using a second protocol, and wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using the second protocol and the bridge device communicates using the first protocol.

Abstract: A bridge for interconnecting a processor to a peripheral device by way of a PCI bus may have a read buffer. The bridge autonomously requests data from the peripheral device and places received data in the read buffer. The processor reads the data from the receive buffer. The bridge may have a write buffer. The bridge accumulates data in the write buffer until a triggering event occurs. Upon the occurrence of a triggering event the bridge sends the data in the receive buffer to the peripheral device in a burst.