Abstract: An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each processor element interface of at least two bus gaskets operates according to a first logical layer protocol. Each port interface operates according to a consistent port interface protocol by sending transaction requests and receiving acknowledgements and by sending and receiving packet datums via the corresponding port. The physical layer interface transfers packets between the ports and includes an arbiter and an interconnect coupled to each port. Additional bus gaskets may be added that operate according to a second logical layer protocol which may or may not be compatible with the first. Any bus gasket may be added that is configured to communicate using multiple logical layer protocols.

Abstract: A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

Abstract: A semiconductor device includes: a plurality of function blocks; a plurality of buses, each of which is respectively connected to one of the plurality of function blocks; a plurality of control signal lines, each of which is respectively connected to one of the plurality of function blocks; a main bus; a bus control unit connected to the main bus; a bus division control unit located between the plurality of buses and the main bus, for connecting one of the plurality of buses to the main bus and transmitting a control signal to a corresponding one of the plurality of control signal lines in accordance with a decoded result of information supplied from the bus control unit via the main bus, thereby controlling a corresponding one of the plurality of function blocks.

Abstract: A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.

Abstract: Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system includes an external access bus used when data is output from the CPU or data is input to the I/O unit or the internal memory unit; an internal access bus used when data is input to the CPU, data is output from the I/O unit or the internal memory unit, or data is input to or output from the peripheral circuitry; and an internal memory test bus used when data is output from the internal memory unit and input to the I/O unit.

Abstract: An integrated circuit system (70) includes a processor (130) and a system bus (12) with a first complexity coupled to the processor. Apparatus for enabling communication between the processor and one or more devices through the system bus include a first device (90), a second device (80), and a first bus interface (72) coupled to the system bus (12), coupled to the first device (90) through a first bus (92) with a second complexity less than the first complexity and coupled to the second device (80) through a second bus (82) with a third complexity less than the first complexity.

Abstract: A low-power audio CD player for portable computers permits operation of the CD-ROM subsystem when power is not being supplied to the computer subsystem. In one embodiment of the invention, the computer subsystem comprises a system CPU, a digital-audio generating circuit, a digital computer bus coupling the CPU and the digital-audio generator circuit, and a digital computer bus controller. The CD audio subsystem comprises an audio device capable of playing an audio CD and coupled to the digital computer bus controller, an audio amplifier circuit coupled to the audio device, and an audio interface coupled to the digital computer bus in parallel to the digital computer bus controller and the audio device. The audio interface is adapted to generate signals to operate the audio device and play the audio CD when power is not being supplied to the computer subsystem or to the CPU.

Abstract: The present invention provides a technique for ordering responses received over a split transaction bus, such as a HyperTransport bus (HPT). When multiple non-posted requests are sequentially issued over the split transaction bus, control logic is used to assign each request an identifying (ID) number, e.g. up to a maximum number of outstanding requests. Similarly, each response received over the split transaction bus is assigned the same ID number as its corresponding request. Accordingly, a “response memory” comprises a unique memory block for every possible ID number, and the control logic directs a received response to its corresponding memory block. The responses are extracted from blocks of response memory in accordance with a predetermined set of ordering rules. For example, the responses may be accessed in the same order the corresponding non-posted requests were issued.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.

Abstract: A system and method for scaling a bus based on a location of a device on the bus are disclosed. An information handling system includes a host bridge interfaced between a local bus and a peripheral bus operable to run at a plurality of bus speeds generated by the host bridge. A plurality of expansion slots are coupled to the peripheral bus and a bus switch is coupled to the peripheral bus between at least two of the expansion slots. Control logic is interfaced with the host bridge and the expansion slots. The control logic is operable to enable at least one of the expansion slots based on a signal received from each of the expansion slots by manipulating the bus switches.

Abstract: A method for accessing a device, such as a memory device and an interface device, by a processor is disclosed. The method involves the processor requesting access permission for the transfer of data. The bridge device grants access permission. The processor in response to the granting of access permission indicates that the processor is busy with the access. The processor also generates address and control signals for the access. The bridge device indicates that data is ready for transfer. A processing system including the processor and the bridge device is also disclosed.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”).

Abstract: A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the scaling features of the PCI Express standard. During operation of the computer system, the status of the endpoints is detected and unused links (or unused portions of links) are rerouted to other endpoints.

Abstract: An aliasing technique allows transparently connecting multiple interconnects across a shared cross-connect interconnect, allowing devices on one interconnect to communicate with devices on another interconnect as if both interconnects were connected by a single interconnect bridge. Each interconnect appears to the cross-connect interconnect as a device on the cross-connect interconnect. Transactions between devices on different interconnects are aliased by a routing engine connected to the cross-connect interconnect for transmittal across the cross-connect interconnect and are invisible to other transactions on the cross-connect interconnect. Transactions between devices on the same interconnect are invisible to other interconnects. Cache coherent requests are supported by the use of additional attribute bits.

Abstract: In the present invention, a computer in which a plurality of programs are executed under a management of an Operation System having a memory management mechanism includes a unit for ensuring atomicity of a first user process without requiring a dedicated CPU instruction. The unit for ensuring atomicity includes a unit for detecting an interrupt by a second user process, a unit for canceling the first user process by utilizing a memory protection function possessed by said Operating System, and a unit for executing an operation of the first user process again.

Abstract: An ATA device access system preferably includes surrogate registers that correspond to ATA registers. A command register can be configured to control data transfer between the ATA and surrogate registers. A status register can be configured to signal completion of data transfer to or from the surrogate registers. Using the ATA device access system, data can be written to the surrogate registers during a write operation with little or no wait and then transferred to the ATA registers without tying up a bus or a processor. Similarly, data can be loaded into the surrogate registers from the ATA registers during a read operation with little or no wait, before being read from the surrogate registers by a processor.

Abstract: An architecture is provided that includes a reconfigurable bridge for routing data among functional units. Register transfer units effect the routing of data among registers that are associated with each functional unit. Synchronous and asynchronous register transfers are supported, including interrupt signal generation for efficient digital signal processor support. A preferred embodiment of the reconfigurable bridge includes a plurality of reconfigurable datapath units that provide ancillary functions to facilitate the processing and pre-processing of data items as they are transferred among registers. A preferred embodiment of the invention also includes an instruction memory that contains instructions to effect the desired register transfers and ancillary operations.

Abstract: Ports of a switch are assigned by a person, for example a network manager, to be for communication up the spanning tree toward the root switch (“up ports”), or down the spanning tree away from the root switch (“down ports”). This assignment is made by enabling “Uplinkguard” status for a desired up port, and by connecting the desired port to a switch which it is desired to place in the higher layer of the spanning tree. A port having Uplinkguard enabled is prevented, for example by software or firmware in its switch, from transitioning to a designated role. Uplinkguard-enabling a port, by preventing the port from transitioning to the designated role, has at least two consequences: preventing the port from being selected by the STP to transmit to lower switches in the spanning tree; and, preventing the port from transmitting when a one way connectivity fault develops on that port. A port with Uplinkguard enabled may transition to root port role.

Abstract: A bridge system having at least one bridge chip to control the operations of the bridge. Each bridge chip uniquely connects to a bus interface allowing communications between a host system and the bridge chip when that bus interface is to be utilized. Each bridge chip also connects to another bus interface connecting the bridge with a device. Each bridge chip includes an activation circuit that automatically disables that bridge chip after a power-on or a hardware reset occurs. When the activation circuit receives a protocol initialization signal, the activation circuit causes only the associated bridge chip to become enabled. Once enabled, the bridge chip drives all of the pins in the bus interface connecting the bridge with the device and remains in control of that bus interface until a power-off, a hardware reset occurs, or the bridge chip has been physically disconnected from the host.

Abstract: Systems, methodologies, media, and other embodiments associated with a system for producing a bus-type header-type field from a point-to-point data-type field are described. One exemplary system embodiment includes a logic configured to identify that a point-to-point transaction includes non-memory-data information encoded in a data flit, a logic configured to extract the non-memory-data information from the data flit, and a logic configured to produce a header-type field for a bus-type transaction produced by the virtual bus interface from the point-to-point transaction.

Abstract: ATA devices, such as mass storage units, have increasingly larger storage sizes that use larger configuration register sizes. A command block format allows the USB/ATA bridge circuit to be used with ATA devices with larger registers and at the same time operates with earlier ATA command block formats.

Abstract: In a serial bus network, an environment is provided, in which the serial bus is divided to two local buses and a specific terminal connected to one of the local buses can reliably occupy other terminals connected to the other local bus without influence on the terminals connected to the local buses. A specific terminal is connected to a local bus 101, to which an inner portal 3 is connected, and an ID information thereof is preliminarily recorded in a ROM 8. After a power source is turned on, the specific terminal connected to the side of the inner portal 3 is detected according to the ID information from the ROM 8. An ID information of all of nodes connected to a local bus 104, to which an outer portal 4 is connected, is read out and stored in a control portion 5. A bus reset is generated on the local bus 101. In order to give a connection information of the local bus 104, a self-ID packet is generated by the control portion 5 and transmits it through a dedicated PHY 6.

Abstract: A computer system with dynamic device identification redirection. The computer system may include a processor, a system memory, and a bridge logic device having a peripheral bus interface. The bridge logic device is associated with at least a first address line, which is also associated with a first peripheral device. The computer system may also include a logic device coupled to the peripheral bus that swaps a second address line for the first address line when a peripheral bus cycle is run to the first address line.

Abstract: A master unit and a slave unit in a data processor are coupled together by a data bus. The master unit sends data transactions to the slave unit through the data bus and the slave unit executes the data transactions. The present invention comprises an apparatus and method for executing a data transaction either (1) by executing the data transaction “in order” with respect to other data transactions received by the slave unit, or (2) by executing the data transaction “out of order” with respect to other data transactions received by the slave unit. The master unit assigns a priority identifier to each data transaction. The slave unit reads the priority identifier to determine whether to execute the data transaction “in order” or “out of order” with respect to the other data transactions.

Abstract: A method of regulating usage and/or concession eligibility in a smart card system is described herein. A card acceptance location (110) detects a presence of a smart card and determines its identification code. The card acceptance location (110) checks the identification code against a list stored locally at the card acceptance location (110). The card acceptance location (110) received the list from a second device. If the identification code of the smart card is listed on the list, the card acceptance location (110) performs an action on the smart card.

Abstract: Distributed peer-to-peer transactions are defined on an interconnect bus of a computer system according to an interconnect protocol. The transactions contain a completer device attribute data and a self-defining payload data. The transaction is identified as a peer-to-peer transaction by a command or an attribute data in the transaction. The transaction can be routed across a hierarchy of interconnect bus segments using the completer device address data. A handle can be used by an operating system of the computer system to indicate permission for the peer-to-peer transaction. Address information in a completer device address space can be provided within the peer-to-peer transaction or by a completer device driver for use by the completer device in processing the peer-to-peer transaction.

Abstract: In a computer system, a host-to-I/O bridge (e.g., a host-to-PCI-X bridge) includes core logic that interfaces with at least two host buses for coupling a central processing unit(s) and the bridge, and interfaces with at least two PCI-X buses for coupling at least two PCI-X devices and the bridge. The core logic includes at least two PCI-X configuration registers adapted to have bits set to partition the core logic for resource allocation. Embodiments of the present invention allow the system to program the logical bus zero to behave as a single logical bus zero or partition into two or more separate “bus zero” PCI-X buses with their own configuration resources. Partitioning allows performance and functional isolation and transparent I/O sharing.

Abstract: A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of issuing interrupts, and an I/O bridge interfacing between the I/O devices and the processors. Interrupts, such as level sensitive interrupts (LSIs), asserted by an I/O device coupled to a specific port of the I/O bridge are sent to a processor for servicing by an interrupt controller, which also sets an interrupt pending flag. Upon dispatching the respective interrupt service routine, the processor generates two ordered messages. The first ordered message is sent to the I/O device that triggered the interrupt, informing it that the interrupt has been serviced. The second ordered message directs the interrupt controller to clear the respective interrupt pending flag. Both messages are sent, in order, to the particular I/O bridge port to which the subject I/O device is coupled.

Abstract: In an environment in which plural external storage devices having different function control interfaces are intermixed, when a function of a storage device is controlled from a computer, a common interface for controlling the function of the storage device is provided. A device that provides the common interface manages an interrelationship between a storage area recognized by a host computer and a storage area provided by the storage device and associates a storage area which becomes a target of a function control instruction with the storage device that provides the storage area. A type of the storage device that provides the storage area which becomes the target of the function control instruction is identified and function control is ordered through a function control interface unique to the device.

Abstract: An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective requestor. The requests are placed by the respective requestor by asserting a request signal, and the request signal is deasserted by the respective requestor when a response is sent back. A retry request may be sent to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later. Together with the retry request, a ready signal is sent indicating whether the request could be processed. This allows the requestor to modify its request when retrying it, if the request was not yet processed.

Abstract: The present invention provides a system for signaling legacy serialized interrupts within a PCI-Express environment, using message signaled interrupts. The system provides structures and methods that interface a PCI environment (106) with a PCI-Express environment (104). The present invention provides a PCI to PCI-Express bridge device (110) that is communicatively linked (112, 114) to the PCI and PCI-Express environments. The bridge device comprises a translation function (116) that is communicatively linked (120, 122) to the PCI and PCI-Express environments. A serialized interrupt is signaled from the PCI environment, and the translation function generates a message signaled interrupt within the PCI-Express environment based on that serialized interrupt.

Abstract: An inter-integrated circuit port comprising an electrical connector for communicatively coupling to an I2C bus and a controller coupled to the electrical connector. The controller controls data communication flow through the electrical connector, including preventing the electrical connector from unauthorized access to the data.

Abstract: A method and apparatus is provided for managing a controller embedded in a south bridge. The method includes determining if the south bridge of a processor-based system is configured to operate in a slave mode or a master mode, and polling one or more sensors in the processor-based system for status values in response to determining that the south bridge is configured to operate in the master mode. The method further includes receiving requests from a network interface card to access sensors internal to the south bridge based on determining that the south bridge is configured to operate in the slave mode.

Abstract: An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.

Abstract: A USB (Universal Serial Bus) host controller, a corresponding integrated circuit chip, a computer system and an operation method are provided for handling the data traffic between at least one USB device and the computer system having system memory. A transaction processing unit processes transactions to or from the at least one USB device. Further, a transaction duration management unit is provided for determining estimated duration values of the transactions. The transaction processing unit is adapted to process the transactions dependent on the estimated duration values. A descriptor-to-transaction converter may be provided, and the prefetched mechanism may be made dependent on a threshold value relating to the estimated duration values.

Abstract: Private devices are implemented on the secondary interface of PCI bridge by re-routing the activation of device select signals (IDSEL) during the address phase of a Type 0 configuration operation on the secondary bus in response to a Type 1 configuration operation on its primary bus. Under control of a mask register and device select reroute circuit, if a configuration command on the primary interface attempts to activate the IDSEL line associated with one of the private, or reroute, devices on the secondary interface, a different IDSEL is activated to select a monitoring device on the secondary interface.

Abstract: A interrupt is generated for all processors in a multiprocessor system when a critical datapath experiences an error. Serialization code in the interrupt handling routine for that interrupt suspends all processors except one and places the suspended processors in a waiting queue while the one processor handles the error. After the error has been handled, the remaining processors are allow to execute the interrupt handler, which simply exits detecting no error.

Abstract: Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active, then disabling of a selectively hidden device interfaced with another active bus provides a bus number to the newly active bus. For instance, if a graphics capability is added to a computer system through a PCI bus, a PCI bridge associated with a second PCI bus is disabled so that the PCI bus number for the portion of the second PCI bus between the chipset of the computer system and the PCI bridge is available for use as the PCI bus number for the PCI bus associated with the graphics capability. The PCI bus number for the portion of the second PCI bus between the PCI bridge and existing peripheral devices is available for use for both portions of the second PCI bus.

Abstract: To prevent data performance impacts when dealing with target devices that can only transfer data for a limited number of bytes before disconnecting, the invention implements a short term data cache on the bridge. Using this feature, the bridge will cache additional data beyond a predetermined quantity of data following a disconnect with the requesting device. As such, the bridge may continue to prefetch additional data up to an amount specified by a prefetch read byte count and return the additional data should the requesting device request additional data resuming at the point of disconnect. However, the bridge will discard the additional data when at least one of the following occurs: a) the requesting device disconnects data transfer, and b) a further READ request that resumes at the point of disconnect is not received within a predetermined time.

Abstract: Provided are a method, system, and program for processing operations in a system including a bus, a target device and devices capable of accessing the target device over the bus. The target device receives a transaction request from one of the devices over the bus and determines whether a delayed read request is pending after receiving the transaction request. The target device issues a command to disconnect the device initiating the transaction request from the bus. The device initiating the transaction request is allowed to reconnect to the bus and complete the transaction request after the delayed read request is completed.

Abstract: A logical pipeline or logical hybrid pipeline is used for an xDSL communication system, and particularly for processing DMT symbols. This flexible arrangement permits easy and efficient sequencing of DMT symbols for transmit/receive tasks, and for multiple ports, since the pipeline resources can be shared or allocated as needed to support a particular data transmission. Each stage in the pipelines works on input data objects, and creates output data objects in the same format for use by other stages. The data objects are based on DMT symbols, so this facilitates intelligent control and sequencing of a DMT data transmission. The combination of the pipeline and the tailored data objects permits an implementation of a customized xDSL symbol processor.

Abstract: An integrated circuit, a computer system, and a method of operating the computer system. The integrated circuit includes an internal bus, a microcontroller connected to the internal bus, an Ethernet controller coupled to the internal bus, and a plurality of buffers coupled between the microcontroller and the Ethernet controller for buffering data between the microcontroller and the Ethernet controller. The microcontroller is configured to master the internal bus. The Ethernet controller and the microcontroller are configured to exchange data over the internal bus.

Abstract: A methodology by which a host computer can dynamically rebalance PCI-to-PCI bridges to overcome Operating System/BIOS and Chipset limitations in order to allow multiple level PCI buses. This methodology also allows hot-swappable PCI buses to be added and removed without failure. Additionally this method allows for proper I/O resource allocation where previously alliasing preventing this. The present invention overcomes the limitations of an Operating System, such as Windows 2000 and Windows XP, to allow a PCI bus segment to be added by rebalancing the PCI bus tree and resource requirements as needed in order to fit the new PCI bus segment.

Abstract: A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.

Abstract: The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.

Abstract: A method for operating automation control equipment applications ensures uninterrupted execution of a control application, at least during specific time periods, but such that the control application does not have the access privileges of a device driver. The operating system is configured for preventing calling of the processor commands from the control application, the processor communicating with the controlled automation equipment via a programmable bus interface. An embodiment of the method comprises the steps of performing read and write access of the control application to the bus interface directly and without routines of the operating system or device driver, and suspending processing of hardware interrupt calls of the processor during a preselected time period.

Abstract: Embodiments are provided in which a method is described for a processor to perform a task of accessing a PCI-X device via a PCI-X bridge, the PCI-X bridge including a processing circuit. The processor builds M read/write control blocks (RWCBs), M being a positive integer. Then, the processor signals the processing circuit and switches to another task. In response, the processing circuit fetches and processes the M RWCBs, one RWCB at a time, to access the PCI-X device. After processing the M RWCBs, the processing circuit interrupts the processor. In response, the processor obtains the result of the processing of the M RWCBs.

Abstract: A bridging system for a communication system comprises a first gateway (107) and a second gateway (108) arranged to communicate with each other. Each gateway (107, 108) is connectable to a different bus (100, 105) of the communication system. The first gateway (107) is operative to communicate details of available devices (102, 103) on its respective bus (100) to the second gateway (108). The second gateway (108) is operative to generate at least one proxy element corresponding to each of said available devices (102, 103). Each proxy element is operative to communicate data and messages between devices (130) on the bus (105) of the second gateway (108) and the device on the first gateway (100) corresponding to the proxy element.

Abstract: A crossbar switch is disclosed. The crossbar switch comprises a plurality of input sorting units and a plurality of merge and interleave units. Each input sorting unit is capable of receiving from a respective device an access request to any one of a plurality of physical memory devices. Each merge and interleave unit is capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device. Also disclosed is method implemented by the crossbar switch.