Abstract: Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.

Abstract: A method and apparatus for implementing RAID through control of the IO channels on the motherboard is provided. One exemplary method locates IO channels on a motherboard. Next, the IO channels on the motherboard are controlled where the IO channels are configured to communicate with a storage media. Then the storage media associated with the IO channels is managed as a RAID. Some notable advantages of the discussed methods and apparatuses include the simplicity of implementing the host based RAID through existing infrastructure contained within a computing system. Additionally, the added benefits of improving reliability and system performance associated with a RAID subsystem are made available in a cost effective manner because most of already existing infrastructure.

Abstract: A low-power audio CD player for portable computers permits operation of the CD-ROM subsystem when power is not being supplied to the computer subsystem. In one embodiment of the invention, the computer subsystem comprises a system CPU, a digital-audio generating circuit, a digital computer bus coupling the CPU and the digital-audio generator circuit, and a digital computer bus controller. The CD audio subsystem comprises an audio device capable of playing an audio CD and coupled to the digital computer bus controller, an audio amplifier circuit coupled to the audio device, and an audio interface coupled to the digital computer bus in parallel to the digital computer bus controller and the audio device. The audio interface is adapted to generate signals to operate the audio device and play the audio CD when power is not being supplied to the computer subsystem or to the CPU.

Abstract: A computer system is arranged to provide protection against faults. The computer system comprises a plurality of processing sets (14, 16), each having at least one processor (52) and a bridge (12) coupled to each of the processing sets (14, 16) and operable to monitor a step locked operation of said processing sets (14, 16). Each of the processors (52) has a processor identification register (64) which is read/writeable and is operable to store in the register data representative of a processor identification. The processors (14, 16) are arranged, consequent upon a masking condition, to load a common predefined data value into the processor identification register, which predefined common data value has an effect of masking the processor identification. The erroneous detection by the bridge (12) of a fault condition resulting from functionally the same processors having a different processor identification is thereby avoided, or at least the likelihood of a false detection reduced.

Abstract: A system and method for observing transactions on a packet bus is disclosed. In one embodiment, a computer system includes a plurality of input/output (I/O) nodes serially coupled to a processor. Each of the I/O nodes may be configured to operate in a first (normal) mode, and a second (analysis) mode. During the normal mode, packets may be selectively conveyed through an I/O tunnel in the I/O node, and particular packets may be selectively conveyed to a peripheral bus interface in the I/O node. In the analysis mode, electrical signals corresponding to packets conveyed through the I/O tunnel may be replicated on a peripheral bus coupled to the peripheral bus interface. No conversion from the packet bus protocol to the peripheral bus protocol. A signal analyzer may be coupled to the peripheral bus, thereby allowing observation of the electrical signals.

Abstract: A computer system having an operating system which complies with the advanced configuration and power interface (ACPI) specification comprises a temperature sensor for sensing an inner temperature of the computer system and for generating an alarm signal when the sensed temperature exceeds a predetermined value, a bridge controller for generating a system management interrupt (SMI) in response to the alarm signal, a basic input-output system (BIOS) read-only memory (ROM) for storing a power management routine, and a power management processor for receiving a power control command signal generated by the power management routine in response to the SMI, and for generating a system command interrupt (SCI). The operating system causes the computer system to enter a “sleep” state in response to the SCI. The computer system enters the “sleep” state when the inner temperature exceeds the predetermined value, and restores data normally when the computer system resumes operation.

Abstract: A computer system including multiple CPUs inform other logic in a computer system as to the priority level (e.g., task priority) associated with the CPU or software executing thereon. The logic makes arbitration decisions regarding CPU transactions based, at least in part, on the task priorities of the various CPUs. The logic that implements this technique may be a host bridge within a computer system having multiple CPUs or in a switch or router that interconnects multiple nodes or computer systems.

Abstract: A switching I/O node for connection in a multiprocessor computer system. An input/output node switch includes a bridge unit and a packet bus switch unit implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link in response to determining the destination each of the upstream packet transactions.

Abstract: A USB apparatus includes an upstream port, a downstream port, a connection detector and a controller. The connection detector is connected to the upstream port and the downstream port, and is for detecting connection statuses of the upstream port and the downstream port to generate a detecting signal accordingly. The controller is used for controlling the USB apparatus to be operated at a host mode or a hub mode according to the detection signal and control method.

Abstract: A method and apparatus is disclosed for implementing an integrated video card and smart card reader. A single processor is used to perform both video and smart card reader functions. The processor simulates a PCI-to-PCMCIA detection logic scheme. An operating system, such as Windows, detects both a video card and a PCI-to-PCMCIA bridge. A smart card reader is attached to the integrated video card and smart card reader.

Abstract: A system and method increases the number of split transactions that can be outstanding on an input/output (I/O) bus operating in accordance with a bus protocol, such as the Peripheral Component Interface Extended (PCI-X) specification standard. An I/O bridge that interfaces between one or more processors and one or more I/O devices coupled to the I/O bus includes a transaction initiation engine, a transaction completion engine and one or more queues for buffering information that is to be transferred onto or which has been received from the I/O bus. The I/O bridge is configured to concatenate, at least logically, a tag field and a function number field from an attribute message so as create a novel, super-tag field that the I/O bridge then associates with each bus transaction. By creating the super-tag field, the I/O bridge substantially increases the number of uniquely identified bus transactions which may be responded to with a Split Response.

Abstract: A method, system, and apparatus for providing data to an I/O adapter from a PCI-to-PCI bus bridge is provided. In one embodiment, once the PCI-to-PCI bus bridge receives a request for data from the I/O adapter, the PCI-to-PCI bus bridge determines whether the requested data is contained within a cached memory within the PCI-to-PCI bus bridge. If the data is contained within the cached memory, then the requested data is provided to the I/O adapter from the cached memory. If the requested data is not within the cached memory, the data is fetched from system memory, then cached in the PCI-to-PCI bus bridge, and sent to the requesting I/O adapter. To ensure that the data in the cached memory within the PCI-to-PCI bridge is not stale, signals are received, periodically or aperiodically, by the PCI-to-PCI bridge from a PCI host bridge indicating whether the data contained within the buffers is stale.

Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Abstract: A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.

Abstract: A bridge device for use in computer systems has a first interface to a first interconnect apparatus such as a processor bus. It also has a second interface to second interconnect apparatus such as an I/O bus. The second interconnect apparatus is of a type capable of connection to a DMA-capable peripheral device. The bridge device has address translation hardware to translate I/O virtual addresses received from the second interface into physical memory addresses for transmission onto the first interface. The address translation hardware has an associated coherency maintenance apparatus. In a particular embodiment, the address translation hardware has a translation lookaside buffer and the coherency maintenance apparatus is apparatus for snooping through the first interface, invalidating TLB entries when a page table in memory is updated.

Abstract: An apparatus and method for passing messages through a bus-to-bus bridge while maintaining ordering. The method comprises passing messages into a message container in the bus bridge without using the bridge buffer, setting a flag that tracks all the writes in the write queue ahead of when the message was put into the message container, blocking the receiving device on the bus connected to the bridge from accessing the message container until the flag is cleared, and clearing the flag when all the writes put into the write queue ahead of when the flag was set have been written to local memory on the receiving bus, then allowing the device on the receiving bus that is the intended recipient to receive the message.

Abstract: An amount of data to be pre-fetched during read operations is adaptively modified based upon the experience of previous reads. If previous reads were terminated before all the data desired was obtained, subsequent read amounts may be increased. The initial amount of pre-fetched data may be pre-set or modified dynamically.

Abstract: A combination of data processing systems that are connected to a common peripheral bus, such as a PCI bus. The processor(s) of each system or blade may communicate with the peripheral bus through an intermediate bus controller. The bus controller may include facilities, such as registers that define a starting address, suitable for defining a window in the blade's system memory that is available or visible to other processors (or masters) on the bus. One or more of the bus controllers may be configured to read information that uniquely identifies each system or blade. The bus controller may use this identification information to define the window in the blade's system memory that is visible to other processors. In an embodiment where each blade is connected to a PCI bus through a CompactPCI® connector, the identification information may be read from the geographic address (GA) pins on the system's J2 connector.

Abstract: A method of and apparatus for communicating data using a hub. The method includes the step of buffering a single transfer request received at a hub during a transaction between the hub and a host controller, where the single transfer request is to be performed between the hub and an agent to generate a result. The method then includes the step of determining whether a transfer inquiry received at the hub from the host controller corresponds to the result.

Abstract: Controller for coupling data between a data storage system and a host includes a first processor and a first RAM coupled to the first processor; a first auxiliary processor including a first memory controller and a first cache coupled to the first memory controller, the first memory controller including first interface for coupling with second auxiliary processor including second memory controller and associated second cache and second interface for coupling with first auxiliary processor, first memory controller including logic for treating the caches as single memory; a bus coupling first primary processor and first auxiliary processor; and interconnection channel separate from the bus coupling first interface of first memory controlled and second interface of second memory controller. Interconnection may be an out-of-band channel permitting device-to-device sharing of associated cache memories without requiring data transfer over the bus. Method and computer program product are also provided.

Abstract: A bridge for connecting a DSP to an ASIC on-chip bus as a slave. The bridge couples signals between a DSP internal memory direct memory interface and an on-chip bus such as the AMBA AHB. The bridge includes a generic slave module which provides direct connections to the on-chip bus in the on-chip bus protocol. It also includes a slave engine connected to the DSP memory interface to control read and write transactions with the memory. The generic slave and the slave engine are coupled by a pulse grower and pulse shaver to allow the engine to operate at DSP clock frequency while the generic slave operates at the usually slower on-chip bus frequency. The bridge allows masters in the ASIC to perform read and write transactions with the DSP internal memory.

Abstract: There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.

Abstract: A method, system, apparatus, and computer-readable medium for eliminating bus renumbering in a computer system are provided. A pool of bus numbers are reserved for each device within a computer system capable of hosting a bridge device. Upon startup of the computer system, each of the buses present in the computer are assigned unique bus numbers. Buses present in the system as a result of a bridge device are allocated bus numbers from the pool of bus numbers reserved for the device upon which the bridge device resides.

Abstract: A USB host system includes a core logic having a host controller and a first root hub coupled thereto, a second root hub external to the core logic and coupled to the first root hub via a mapping interface, and a plurality of USB ports coupled to the second root hub, each of the USB ports adapted to couple an external USB device.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: A split operation such as a split read or a split write is handled by a bus bridge circuit. The bus bridge receives the read or write command from a requesting device, where the command includes a bus number for routing a completion of the command. The bus bridge then compares the bus number received from the requesting device with the return route bus number range of the bus bridge, and issues a split response to the requesting device if the bus number matches the return route bus number range of the bus bridge. If the bus number does not match the return route bus number range, then the command is aborted.

Abstract: A USB device centric agent is associated with an operating system. The agent software is only required to be loaded once and then it will function with multiple compatible USB devices. A standard interface is established between the device agent and any compatible USB device. This enables any compatible USB device to control the agent which in turn controls the host computer. This is opposite the standard practice where the host controls the USB device.

Abstract: A method of (and system for) of transporting a sideband signal through a physical layer of an extended bridge, includes on a first node of the extended bridge, providing an interface to a sideband component coupled to a side of the extended bridge, encoding a first data stream being output from the sideband component with a unique header to identify the data output from the sideband component, and multiplexing the first data stream from the sideband component with a second data stream from a principal signal port, and outputting the multiplexed first and second data streams to another node of the extended bridge.

Abstract: A method and system for a multi-phase net refresh on a bus bridge interconnect, the interconnect comprising a number of nodes, a bus bridge, and a number of buses, are described. In one embodiment, a primary bus is acquired by communicating with other bus bridges on the buses. A secondary bus is breached to acquire the secondary bus. In addition, the primary bus and the secondary bus are committed.

Abstract: Disclosed are a system and method of configuring processing resources for communication with one or more devices coupled to a data bus through a bridge. Resources at a processing system may be configured to communicate with the bridge as a transparent bridge or a non-transparent bridge depending on how the processing system may be implemented in a processing platform.

Abstract: Machine-readable media, methods, and apparatus are described for flexibly establishing lanes of links. In some embodiments, any port of a device may be connected to another port of another device. Further, the device may determine interconnections of its ports to ports of other devices by issuing requests on its ports.

Abstract: A Universal Serial Bus hub apparatus and method is disclosed that is compatible with the On-the-Go (OTG) supplement to the USB 2.0 specification so as to enable dual-role devices (OTG devices) to be connected via a hub. The hub includes a number of ports that are configured to connect the hub to one or more external devices, which may include OTG devices. A controller within the hub controls operations therein. The hub also includes a port switching device controlled by the controller for selectively allowing one of the number of ports to act as a host port and the other remaining ports to act as device ports.

Abstract: A jumper (60) is provided as a control input means for switching operation modes of a CardBus controller (42). Also, a bidirectional bypass path (40A, 66, 58A) is provided in parallel with the controller. When a passthrough mode signal (64) from the jumper exhibits an inactive state, the controller is enabled for operation and the bypass path is disabled for operation, thereby to cause the controller to be operated in its normal mode. On the other hand, when the passthrough mode signal exhibits an active state, the controller is disabled for operation and the bypass path is enabled for operation, thereby to cause predetermined signals on PCI bus signal lines (40A), or signals on CardBus signal lines (58A) corresponding with the predetermined signals to be output on the CardBus or PCI bus as they are via the bypass path. In order to inspect transactions on the PCI bus, a PCI bus analyzer or exerciser is connected to a PC card slot (44A), to which the bypass path is connected.

Abstract: In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

Abstract: The inventive multiple partition computer system allows the reconfiguration of the installed hardware, possibly while the various partitions continue normal operations. This aspect includes adding and removing process cell boards and I/O from partitions which may or may not continue to run. The invention also allows changes to the association between cells, I/O and partitions. The partitions may be able to stay running, or may have to be shut down from the resulting changes. In the invention, multiple copies of the OS are running independently of each other, each in a partition that has its own cell boards with processors and memory and connected I/O. This provides isolation between different applications. Consequently, a fatal error in one partition would not affect the other partitions.

Abstract: A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device. The interface bus is coupled to the first memory device, the second memory device and the memory interface. Control signals, address signals and data signals are transmitted over the interface bus.

Abstract: Non-volatile memory access, such as firmware access by a service processor, is disclosed. The service processor asserts a controller signal to select either a first non-volatile memory, or a second non-volatile memory. The first non-volatile memory is located behind a first bridge controller and is otherwise accessible by the service processor. The second non-volatile memory is located behind a second bridge controller and is otherwise accessible only by a processor other than the service processor. The service processor then access the selected non-volatile memory, via a bus communicatively coupled to both the non-volatile memories.

Abstract: An improved response reordering technique for use in a southbridge device or I/O hub or similar devices are provided. Non-posted read requests are received from at least one requestor, and upstream commands are transmitted based on the non-posted read requests. Each of the upstream commands is uniquely identified by a command tag. When response data is received in reply to previously transmitted commands, responses are transmitted to the at least one requestor based on the response data. Transmitting the responses comprises reordering the received response data by accessing a buffer of the southbridge device. The buffer stores the received response data and has a plurality of buffer elements that are each uniquely assigned to one of the command tags.

Abstract: A method and implementing system is provided in which multiple nodes of a Peripheral Component Interconnect PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.

Abstract: A bridge for connecting a DSP to an ASIC on-chip bus as a master on the bus. The bridge includes a DSP instruction unit master interface and a DSP data unit master interface to convert DSP instruction unit and data unit external signals into bus protocol signals. An arbiter is provided to receive the signals from the two DSP interfaces and selectively pass the signals to a generic bus master which couples the signals to the on-chip bus. A synchronization unit is provided to insure alignment of positive clock transitions between the different clock frequencies of the ASIC and the DSP and to buffer signals as needed. The generic bus master couples signals from the arbiter and the synchronization unit to the ASIC bus in full compliance with the bus protocol.

Abstract: A network configuration method ensuring high reliability of bridge manager selection and bus reset is disclosed. After configuring each of the IEEE 1394 buses according to IEEE 1394 standard, a network management node is selected from a first IEEE 1394 bus including at least one node capable of network management. First, the first IEEE 1394 bus is configured such that the first IEEE 1394 bus belongs to the network management node. Then, an adjacent IEEE 1394 bus of the first IEEE 1394 bus is configured into a configured IEEE 1394 bus to produce an interim network such that the adjacent IEEE 1394 bus belongs to the network management node. The configuration of the adjacent IEEE 1394 bus is repeated until no adjacent IEEE 1394 bus which does not belong to the network management node is left in the IEEE 1394 network.

Abstract: Apparatus and method for providing DMA transfers between an adapter card with or with out DMA capabilities and a system CPU with DMA capabilities. An adapter DMA controller circuit resides between the system CPU and the adapter card. This adapter DMA controller allows the system to run in immediate mode which allows the system CPU to talk to the adapter card as if the adapter DMA controller was not there. The system can also run in DMA mode. In this mode the system CPU sets up the system DMA controller and the adapter DMA controller. The adapter DMA controller takes over sending or receiving data to the adapter card and then requesting a DMA transfer with the system DMA controller. The transfer of data between the adapter DMA controller and the adapter does not use any system CPU resources such as the data and address busses. The system CPU is free to use the system resources to continue operation.

Abstract: A transaction tracing circuit for use with a bus bridge that is couplable to at least a first and second bus. The transaction tracing circuit includes at least one set of trace control registers that is associated with a transaction tracing function for tracing a specific transaction occurring on the bus bridge. A number of bus transaction tracing circuits, one for each bus to which the bridge is connected, are coupled to the trace control registers and are utilized to store is transactions that are captured as they occur on the individual buses. An internal transaction tracing circuit is coupled to the trace control registers and is utilized for storing captured internal transaction information corresponding to the specific internal transaction.

Abstract: In some embodiments, the inventions include a device and bus transaction control circuitry to receive bus transactions with tag space including a first part that at times is used to represent a transaction number and a second part that at times contains information which under some conditions is used by the device. Other embodiments are described and claimed.

Abstract: A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.

Abstract: A computer system reroutes a configuration cycle intended for an unused system bus address line to the IDSEL, or equivalent, configuration chip select input pin of a device which uses the same system bus address line as another device on the system bus. The computer system has a PCI bus to which a programmable logic device and an electronically-controlled switch are connected. The programmable logic device detects PCI bus configuration cycles associated with a PCI bus AD line that is otherwise unused as a chip select during configuration cycles. When the logic device detects a configuration cycle associated with the unused AD line, the logic device asserts a control signal to the electronically-controlled switch. The switch then connects the previously unused AD line to the AD line that is connected to the IDSEL input pin of the PCI device that experiences the conflict.

Abstract: In a bridged, pipelined network (FIG. 1), a network-to-host bridge (140) identifies the address space of a host computer (FIG. 2) as not being contained within the host computer memory space (120). During the removal of the host computer (100) and its replacement by a new host computer, the network-to-host bridge (140) momentarily locks out traffic (FIG. 3, step 320) in order to disable peripheral components (FIG. 1, 160, 180) from initiating bus transactions. When the new host computer is installed (FIG. 3, step 320) and the bus lockout is removed (step 340), the new host memory area is protected from direct memory access transactions which were stored in the bus hierarchy during the host computer swap.

Abstract: An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.

Abstract: Provided are a method, system, and program for processing operations in a system including a bus, a target device and devices capable of accessing the target device over the bus. The target device receives a transaction request from one of the devices over the bus and determines whether a delayed read request is pending after receiving the transaction request. The target device issues a command to disconnect the device initiating the transaction request from the bus. The device initiating the transaction request is allowed to reconnect to the bus and complete the transaction request after the delayed read request is completed.

Abstract: A high-speed bus subsystem includes a plurality of bus channels, wherein each bus channel has an independent channel clock signal generated by an associated channel clock generator. A master device or other interface component receives and utilizes a system clock signal and a channel clock signal for each channel. For each channel, a derivative of the system clock signal and a derivative of the channel clock signal are routed to a clock generator. The clock generator compares the received signals, and generates its channel clock signal at a phase which eliminates any significant phase difference between the system clock signal and the channel clock signal.