Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.

Abstract: Configuration item data from information technology resources of an air-gapped network are collected for an information technology configuration management database. The collected configuration item data is filtered using a specified item data property including by automatically identifying a collected information of interest about a discovered information technology asset among the collected configuration item data and irreversibly modifying the collected information of interest about the discovered information technology asset included in the collected configuration item data. Based on a type of content that has been modified in the collected information of interest, a new automatic rule indicating the type of content to be avoided during a future data collection is determined. At least a portion of the filtered collected configuration item data is stored on a portable physical storage medium within the air-gapped network.

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) device and a method of operating the same. The PCIe device may include a performance analyzer, a delay time information generato and a command fetcher. The performance analyzer may measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions. The delay time information generator may generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information. The command fetcher may fetch a target command from a host based on a delay time of a function corresponding to the target command.

Abstract: A storage system is provided. The storage system includes a plurality of storage units, each having a controller and solid-state storage memory. The storage system further includes one or more first pathways that couple processing devices of a plurality of storage nodes and is configured to couple to a network external to the storage system and one or more second pathways that couple the plurality of storage nodes to the plurality of storage units, wherein the one or more second pathways enable multiprocessing applications.

Abstract: In some embodiments, a system for communicating USB information via a non-USB extension medium is provided. The system comprises a downstream facing port device (DFP device). The DFP device is configured to receive, via the non-USB extension medium, an ACK IN packet addressed to a first endpoint while receiving DATA packets from a second endpoint. The DFP device is further configured to detect an end of transmission of the DATA packets from the second endpoint; determine a number of packets that can be received from the first endpoint during a remaining amount of time in a current bus interval; and transmit at least one synthetic ACK IN packet to the first endpoint based on the number of packets.

Abstract: A quantum coding system coupled to a quantum channel that includes an entanglement server that generates a first and second entangled qubit. A first cache coupled to the entanglement server and comprising a quantum store configured to store qubits and a classical store configured to store classical tagging information associated with the stored qubits, the first cache configured to provide the first entangled qubit at an output at a first time that is based on classical tagging information associated with the entangled qubit pairs. A transmitter coupled to the first quantum cache and coupled to the quantum channel, the transmitter configured to modulate the first entangled qubit pairs from the first cache using classical information, thereby producing coded classical information, and to provide the modulated qubit to the quantum channel.

Abstract: A test method is for testing a decision feedback equalization (DFE) of a memory device is provided. The memory device includes a memory bank. The test method includes: providing a first test data pattern having a first data transition frequency and a second test data pattern having a second data transition frequency different from the first data transition frequency; writing the first test data pattern into a first memory section of the memory bank with a first DFE; writing the second test data pattern into a second memory section of the memory bank with the first DFE; reading a first reading data pattern stored in the first memory section and a second reading data pattern stored in the second memory section; and generating a test result signal according to the first reading data pattern and the second reading data pattern.

Abstract: Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.

Abstract: Systems and methods involving quantum machines, hybrid quantum machines, aspects of quantum information technology and/or other features are disclosed. In one exemplary implementation, a system is provided comprising a quantum register that stores quantum information using qubits, wherein the qubits are configured to store the quantum information using particles or objects arranged in a lattice of quantum gates, a clock that provides a clock cycle to the quantum register, and a qubit-tie computing component coupled to the quantum register, wherein the qubit-tie computing component is configured to shift the quantum information between the qubits, wherein the system stores the qubits in different states using physical qualities, which may define qubits that are configured to be entangled and superposed at a same time. Further, the quantum register may comprise an entanglement component, and/or the qubit-tie computing component may comprise a superposition component.

Abstract: A baseboard management controller (BMC) and an operation method thereof are provided. The BMC includes a path switching circuit, a host interface circuit, a universal serial bus (USB) hub controller, a USB physical layer circuit, and a control circuit. The host interface circuit is adapted to be electrically connected to a host circuit outside the BMC. The USB physical layer circuit is adapted to be electrically connected to an external USB host or an external USB device outside the BMC. The control circuit controls the path switching circuit to selectively couple the host interface circuit to the USB hub controller, selectively couple the USB hub controller to the USB physical layer circuit, or selectively couple the host interface circuit to the USB physical layer circuit.

Abstract: An input/output unit for data acquisition in a field bus system includes a microcontroller that has at least one integrated synchronous serial bus interface and a control device for direct memory access. A signal source for a digital signal is connectable to a digital data input master input, slave output (MISO) of the at least one synchronous serial bus interface. The first synchronous serial interface reads in the digital signal present at the data input MISO at a first clock rate that corresponds to a data transmission rate of the at least one synchronous serial bus interface. The control device for direct memory access forwards the read-in data words to a buffer memory, and periodically fetches the read-in data words from the buffer memory and forwards the read-in data words to a second synchronous serial bus interface or to another bus interface.

Abstract: A flexibly configured multi-computing-node server mainboard structure and a method. A processing unit connects to PCIE devices via I2C concurrently. The processing unit analyzes whether the acquired data of the PCIE devices are abnormal. The processing unit connects to a baseboard management controller via I2C, when the data are normal, the processing unit polls to transmit analyzed data to the baseboard management controller via I2C. When the data are abnormal, the processing unit pauses polling and transmitting information, and preferentially transmits abnormality information to the baseboard management controller. The processing unit is provided with an internal clock assembly and an external clock assembly, the external clock assembly is connected to a PCH, the internal clock assembly and the external clock module are connected to a data selector, and an output of the data selector is electrically connected to the PCIE devices.

Abstract: A chip includes a peripheral component interconnect express (PCIe) switch, a dual-mode device, and a signal transmission control circuit. The PCIe switch includes a first downstream port. The dual-mode device switches between a root complex (RC) mode and an endpoint (EP) mode. The signal transmission control circuit is coupled between the PCIe switch and the dual-mode device. The first downstream port communicates with the dual-mode device operating under the EP mode. The signal transmission control circuit allows an external PCIe device to communicate with the dual-mode device operating under the RC mode.

Abstract: Example implementations relate to executing a workload in a computing system including processing devices, memory devices, and a circuit switch. An example includes identifying first and second instruction-level portions to be consecutively executed by the computing system; determining a first subset of processing devices and a first subset of memory devices to be used to execute the first instruction-level portion; controlling the circuit switch to interconnect the first subset of processing devices and the first subset of memory devices during execution of the first instruction-level portion; determining a second subset of the processing devices and a second subset of the memory devices to be used to execute the second instruction-level portion; and controlling the circuit switch to interconnect the second subset of processing devices and the second subset of memory devices during execution of the second instruction-level portion.

Abstract: The invention provides an interface conversion device including a USB connector, a DP connector, a first physical layer (PHY) circuit, a second PHY circuit, a digital buffer, a USB controller, and a path switching circuit. A first terminal of the first PHY circuit is coupled to the USB connector. The digital buffer and the USB controller are coupled to a second terminal of the first PHY circuit. A first terminal of the second PHY circuit is coupled to the DP connector. The path switching circuit selectively electrically connects a second terminal of the second PHY circuit to an output terminal of the digital buffer when the interface conversion device is operated in DP ALT mode. The path switching circuit selectively electrically connects the second terminal of the second PHY circuit to a DP output terminal of the USB controller when the interface conversion device is operated in tunneling mode.

Abstract: A total number V of virtual host-managed device memory (HDM) decoder configurations are generated for the same total number V of HDM memory regions attached to a non-host computing device. Each virtual HDM decoder configuration in the virtual HDM decoder configurations corresponds to a respective HDM memory region in the HDM memory regions. A proper subset of one or more virtual HDM decoder configurations is selected from among the virtual HDM decoder configurations to configure one or more physical HDM decoders of a total number P of the non-host computing device into one or more virtual HDM decoders. The one or more physical HDM decoders configured as one or more virtual HDM decoders are applied to translate a host physical address (HPA) received from a host computing device in a memory access transaction involving the host computing device and the non-host computing device.

Abstract: A device connectable between a host computer and a computer peripheral over a standard bus interface is disclosed, used to improve security, and to detect and prevent malware operation. Messages passing between the host computer and the computer peripherals are intercepted and analyzed based on pre-configured criteria, and legitimate messages transparently pass through the device, while suspected messages are blocked. The device communicates with the host computer and the computer peripheral using proprietary or industry standard protocol or bus, which may be based on a point-to-point serial communication such as USB or SATA. The messages may be stored in the device for future analysis, and may be blocked based on current or past analysis of the messages. The device may serve as a VPN client and securely communicate with a VPN server using the host Internet connection.

Abstract: The present disclosure provides a port controller and an electronic device. The port controller is compatible with a Universal Serial Bus (USB) Type-C standard and is used in a device operable as a sink device. The port circuit is communicable with an external main controller. A transceiver is communicable with a source device via a configuration channel (CC) pin of a receptacle. A control unit is capable of negotiating with the source device via the transceiver. A pin control circuit controls a state of the CC pin and monitors the state of the CC pin. A power supply circuit receives a bus voltage supplied from the source device and generates a power supply voltage of the main controller.

Abstract: Reliability, in 5G and emerging 6G, is a continuing challenge due to signal fading, heavy interference, and phase noise, among others. The disclosed procedures show how to locate the most likely faulted message elements according to a deviant modulation, excessive amplitude or phase instability, and inconsistency between successive transmissions of the message. In addition, the receiver can rectify the message either by altering the faulted message elements to other modulation states, or by selectively merging two versions of the message according to signal quality. In either case, reliability is improved, range is extended, and time is saved.

Abstract: A method of ensuring power delivery in a universal serial bus (USB) interface between a device and a counterpart device, the device including a port controller and a USB receptacle. The method includes the port controller attempting to detect an abnormal state in which a leakage current occurs in the USB receptacle using at least one pin of the USB receptacle; and when the abnormal state is detected, the port controller turning OFF a switch connected between a power pin of the USB receptacle and an internal circuit of the device, and determining to enter an unattached state of being separated from the counterpart device.

Abstract: Data centers often run long lived services such as web servers that are intended to run for hours, days, or even longer before being torn down and replaced with another instance of the long-lived service. Currently, many applications are being implemented with microservice architectures that run short lived services that start up, implement an operation, and are then torn down. An aspect of starting up a service is creating administrative data structures such as InfiniBand queue pairs. A packet processing pipeline having a DMA output stage can be configured to create the administrative data structures, thereby increasing the rate at which the administrative data structures are created. As a result, services running in data centers can be started up more rapidly and efficiently.

Abstract: A USB hub, including multiple USB upstream ports, multiple downstream ports, multiple image processing units, a USB hub unit, a first multiplexer, and a second multiplexer, is provided. The USB upstream ports include a first USB upstream port and a second USB upstream port. The downstream ports include a first downstream port and a second downstream port. The image processing units include a first image processing unit and a second image processing unit. The first multiplexer is coupled to the first USB upstream port, the second USB upstream port, the first image processing unit, the second image processing unit, and the USB hub unit. The second multiplexer is coupled to the first image processing unit, the second image processing unit, the USB hub unit, the first downstream port, and the second downstream port.

Abstract: An SPI-based data transmission system is provided. In the system, a master SPI apparatus enables a first slave SPI apparatus by using a combination of a first and a second chip select signal. In response to the master SPI apparatus driving the first chip select signal to be in an enable state and driving the second chip select signal to be in a disable state, the master SPI apparatus controls a second slave SPI apparatus to send data using a data line. The master SPI apparatus further receives data by using the data line, and the first slave SPI apparatus receives data using the data line. When the first chip select signal is in the enable state and the second chip select signal is in the disable state, the master SPI apparatus and the first slave SPI apparatus can simultaneously receive data transmitted by the second slave SPI apparatus.

Abstract: A method includes receiving a request for an allocation of memory resources based on quality of service (QoS) parameters. The method further includes provisioning, via a QoS manager component, a plurality of physical functions to provide the requested allocation of resources. At least two of the plurality of physical functions can be provided to meet a QoS criteria.

Abstract: The present disclosure provides a multipath device working system, including a processor and a touch display module, a control management module, a wireless communication module, a USB module, a microphone, and a loudspeaker that are respectively connected to the processor. The touch display module is configured to display a user operation interface and obtain a control instruction from a user. Both the wireless communication module and the USB module are configured to perform data transmission between the multipath device working system and an external communication device. The control management module is configured to manage a plurality of software communication terminals on the external communication device. The processor is configured to separately perform data processing on data transmitted by the touch display module, the control management module, the wireless communication module, the USB module, the microphone, and the loudspeaker.

Abstract: A computer program component configured to collect configuration item data from information technology resources of an air-gapped network for an information technology configuration management database is provided. Configuration item data collected from the information technology resources of the air-gapped network is obtained using the provided computer program component, wherein the obtained configuration item data is physically transferred between a device within the air-gapped network and a device outside the air-gapped network at least in part via a portable physical storage medium, and the collected configuration item data has been reviewed and filtered within the air-gapped network prior to being physically transferred via the portable physical storage medium. The obtained configuration item data is imported to the information technology configuration management database outside the air-gapped network.

Abstract: A system including a fabric manager, a memory mapper, and a switch is described. The memory mapper receives and stores mapping information from the fabric manager that maps memory locations in a plurality of hosts to corresponding memory locations in a plurality of physical devices. The switch receives at least a portion of the mapping information from the memory mapper, receives a request from a host, and accesses memory that is identified by the request on a physical device of the plurality of physical devices.

Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.

Abstract: Systems and methods for memory management for virtual machines. An example method may include receiving, by a host computing system, a memory access request initiated by a peripheral component interconnect (PCI) device, wherein the memory access request comprises a memory address and an address translation flag specifying an address space associated with the memory address; and responsive to determining that the address translation flag is set to a first value indicating a host address space, causing a host system input/output memory management unit (IOMMU) to pass-through the memory access request.

Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.

Abstract: The present invention provides a control method of a server, wherein the control method includes the steps of: periodically controlling a first register and a second register of a first node to have a first value and a second value, respectively; periodically controlling a third register and a fourth register of a second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value is different from the fourth value; controlling the second register and the third register to synchronize with each other, wherein the second value is different from the third value; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.

Abstract: An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.

Abstract: A thunderbolt device module is provided. The thunderbolt device module of the invention includes a first interface protocol component, a thunderbolt controller and a second interface protocol component. A root complex of an electronic device is via a bus, conforming to a PCIe interface protocol, directly or indirectly electrically coupled to the second interface protocol component. The first interface protocol component and the second interface protocol component both conform to a predetermined interface protocol. In particular, the predetermined interface protocol is not the PCIe interface protocol, but supports the PCIe interface protocol. The thunderbolt controller is electrically coupled to the first interface protocol component. The second interface protocol component is electrically coupled to the first interface protocol component. The communication between the second interface protocol component and the first interface protocol component conforms to the predetermined interface protocol.

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

Abstract: Disclosed are techniques to regenerate SYNC bits of a High-Speed data packet lost by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may lose some SYNC bits at the beginning of the SYNC pattern. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. If the end of the SYNC is read before a programmable number of SYNC bits have been transmitted, the repeater/hub generates additional SYNC bits for transmission until the programmable number of SYNC bits are transmitted. The repeater/hub then resumes transmitting the rest of the High-Speed data packet starting from the payload.

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

Abstract: A data processing system includes a central processing unit (CPU) and accelerator cards coupled to the CPU over a bus, each of the accelerator cards having a plurality of data processing (DP) accelerators to receive DP tasks from the CPU and to perform the received DP tasks. At least two of the accelerator cards are coupled to each other via an inter-card connection, and at least two of the DP accelerators are coupled to each other via an inter-chip connection. Each of the inter-card connection and the inter-chip connection is capable of being dynamically activated or deactivated, such that in response to a request received from the CPU, any one of the accelerator cards or any one of the DP accelerators within any one of the accelerator cards can be enabled or disabled to process any one of the DP tasks received from the CPU.

Abstract: Systems, methods, and apparatuses relating to performing an attachment of an input-output memory management unit (IOMMU) to a device, and a verification of the attachment. In one embodiment, a protocol and IOMMU extensions are used by a secure arbitration mode (SEAM) module and/or circuitry to determine if the IOMMU that is attached to the device requested to be mapped to a trusted domain.

Abstract: An integrated circuit includes a primary initiator domain (ID) circuit including having a processor core, a responder domain (RD) control circuit, and a reset controller. Secondary ID circuits, each include a processor core and a reset controller. RD circuitry is coupled to communicate with the primary ID circuit and the secondary ID circuits and includes RD resource circuits. The RD control circuit is configured to allocate each of the RD resource circuits to a first initiator domain consisting of the primary ID circuit or one of the secondary ID circuits, and when one of the secondary ID circuits enters a reset mode of operation, the RD resource circuit allocated to the one of the secondary ID circuits enters a reset while the remaining RD resource circuits are not affected by the reset.

Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.

Abstract: Alternate sideband signaling in a Peripheral Component Interconnect (PCI) express (PCIE) link may be enabled over existing sideband lines in a conventional PCIE link. For example, the default sideband communication of PCIE may be changed to a Universal Asynchronous receiver/transmitter (UART), line multiplex UART (LM-UART), serial peripheral interface (SPI), I2C, or I3C mode of communication. This change may be negotiated between the host and slave of the communication link, with a transition occurring after the negotiation concludes. The new mode of communication may include or encode the conventional PCIE sideband signals.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

Abstract: A dynamic switching method is applied to an electronic switching device. Judge whether insertion and withdrawal times between the electronic switching device and a USB cable reach a preset threshold value. Start a UART function of the electronic switching device temporarily. Judge whether an instruction of starting the UART function sent by the USB cable is received. If a recognition program unit receives the instruction of starting the UART function, the recognition program unit starts the UART function. Execute the UART function. Judge whether the electronic switching device receives an instruction of stopping the UART function. Switch to an initial status. Change a start value of a UART circuit unit into an initial value of the UART circuit unit. Charge the electronic switching device through the USB cable.

Abstract: A bridge circuit includes an NVMe device controller, a network subsystem, and a data transfer circuit. The NVMe device controller is arranged to communicate with a host via a PCIe bus. The network subsystem is arranged to communicate with an NVMe-TCP device via a network. The data transfer circuit is coupled between the NVMe device controller and the network subsystem, and is arranged to deal with data transfer associated with the NVMe-TCP device without intervention of the host.

Abstract: A CDN traffic is optimized by a client-side system that maps the servers in the CDN system. Content requests from client devices for domain names are forwarded to servers in the CDN system that may be selected from the map to prevent a cache miss in the a server for a particular request for content.

Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes instructing a PCIe fabric communicatively coupling a plurality of physical computing components including PCIe devices and one or more PCIe switches to establish a first PCIe communication path between the management processor and a target PCIe device. The method also includes directing at least configuration data to the target PCIe device using the first PCIe communication path and instructing the PCIe fabric to remove the first PCIe communication path between the management processor and the target PCIe device. The method also includes instructing the PCIe fabric to establish a second PCIe communication path between a selected PCIe device and the target PCIe device configured according to the configuration data.

Abstract: Methods, systems, and computer storage media for providing a Shell PCIe Bridge (SPB) and shared-link-interface services that support a shared common PCIe physical link between SPB clients in a PCIe system. In operation, shared-link-interface operations include accessing, at a Shell PCIe Bridge (SPB), an outbound transaction for a PCIe endpoint vendor IP or an inbound transaction for an SPB client. The SPB supports a shared common PCIe physical link based on a shared-link-interface comprising vendor-agnostic downstream custom interface and a vendor-specific upstream PCIe endpoint interface. The shared-link-interface operations further include processing the outbound transaction or the inbound transaction based on shared-link-interface services. In this way, processing transaction comprises executing shared-link-interface operations that provide protection enhancements associated with sharing a physical PCIe link.