Peripheral Bus Coupling (e.g., Pci, Usb, Isa, And Etc.) Patents (Class 710/313)
  • Patent number: 10430362
    Abstract: According to one embodiment, a system includes first and second devices. The first device detects whether a cable is connected to the first device in a first state or a second state. The first device receives, from the second device, status information indicative of whether the cable is connected to the second device in the first state or the second state. The first device switches allocation of signal lines to contact pins of a connector of the first device to which the cable is connected, based on connection states of the first and second devices. The second device detects whether the cable is connected to the second device in the first state or the second state. The second device transmits, to the first device, a result of detection as the status information.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 1, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Client Solutions Co., Ltd.
    Inventors: Hiroaki Chiba, Koichi Senuma
  • Patent number: 10430369
    Abstract: The disclosure is related to an interface card module which is configured to be inserted into a PCIe slot on a motherboard and to be inserted with a cable electrically connected to a function chip. The interface card module includes an adapter card and a function card. The adapter card includes a mainboard, a first PCIe male connector, a socket and at least one cable connector. The first PCIe male connector, the socket and the cable connector are respectively disposed on different sides of the mainboard. The first PCIe male connector is configured to be inserted into the PCIe slot on the motherboard. The at least one cable connector is inserted with the cable. The function card has a second PCIe male connector configured to be inserted into the socket of the adapter card. In addition, the disclosure is also related to an adapter card.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 1, 2019
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Shih-Tse Chen, Ching-Chuan Huang, Chao-Hsiang Huang
  • Patent number: 10425360
    Abstract: A system that includes (i) a device having connectors connected to pluggable modules external to the device and (ii) the pluggable modules exchanging signals with the device via the connectors. In particular, the pluggable modules includes a first pluggable module and a second pluggable module that further exchange a supplemental signal with each other and bypassing the connectors.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: September 24, 2019
    Assignee: Ciena Corporation
    Inventors: Kevin Estabrooks, Daniel Rivaud, Michael J. Windgrove
  • Patent number: 10417168
    Abstract: According to an embodiment, a system, a method, and/or a computer program product is provided to allow a choice of allocating resources of a processor host bridge (PHB) at initial setup of a computer system to a group of peripheral component interconnect express (PCI-E) slots via a PCI-E switch, or alternatively to allocate resources of the PHB directly to a single PCI-E slot. The system may include a PHB, a first switch connected to the PHB, where the first switch is a simple circuit, a second switch connected to the first switch, where the second switch is a simple circuit, a PCI-E switch connected to the first switch and connected to the second switch, and a first PCI-E slot connected to the second switch.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Daniel Larson, Timothy J. Schimke
  • Patent number: 10417160
    Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 17, 2019
    Assignee: FutureWei Technologies, Inc.
    Inventor: Wesley Shao
  • Patent number: 10417144
    Abstract: A bridge device including a first connector, a first transceiver, a second connector, a second transceiver, a voltage processor, and a controller is provided. The first connector is configured to couple to a host and includes a first pin. The first transceiver is coupled between the first pin and a node and includes a first current limiter. The second connector is configured to couple to a peripheral device and includes a second pin. The second transceiver is coupled between the node and the second pin and includes a second current limiter. The voltage processor processes the voltage of the node to generate an operation voltage. The controller receives the operation voltage to determine whether to turn on at least one of the first and second transceivers.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 17, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Tze-Shiang Wang
  • Patent number: 10387346
    Abstract: A system and method for dynamic reconfiguration of at least one peripheral bus switch of a system includes a management controller that detects whether a server system is connected to each peripheral bus slot of the system. The management controller selects a peripheral bus switch topology for the at least one peripheral bus switch, based on the detecting. The management controller sets each port of the at least one peripheral bus switch to either an upstream port configuration or a downstream port configuration, based on the peripheral bus switch topology.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 20, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventors: Hsiao-Tsu Ni, Shuen-Hung Wang, Chia-Ju Lee
  • Patent number: 10387182
    Abstract: Methods, systems, or apparatus may be directed to hosting, by a virtual machine manager of a local machine, a virtual machine having a device driver. A virtual machine manager may obtain, from a stub driver on a remote machine, information about the I/O device on the remote machine. The I/O device may be bound to a stub driver on the remote machine. The virtual machine manager may instantiate a virtual I/O device on the local machine corresponding to the I/O device on the remote machine. The virtual machine manager may then collaborate with the stub driver on the remote machine to effectuate a real access to the I/O device on the remote machine for an access to the virtual I/O device by the device driver on behalf of a program on the local machine.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Zhefu Jiang, Shoumeng Yan, Gansha Wu
  • Patent number: 10380041
    Abstract: A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster and configures the computer cluster to provide resources for the applications in accordance with the allocation. The cluster may include a Peripheral Component Interconnect express (PCIe) fabric. The cluster manager may configure PCIe multi-root input/output (I/O) virtualization topologies of the computer cluster. The allocations may satisfy Quality of Service requirements, including priority class and maximum latency requirements. The allocations may involve splitting I/O traffic.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: August 13, 2019
    Assignee: Dell Products, LP
    Inventors: Shyamkumar Iyer, Matthew L. Domsch
  • Patent number: 10382432
    Abstract: A method of reading out access authorizations or ID's from at least one customer medium by at least one reader (3, 4, 5) of an access control device (2) and evaluating the selected ID's or access authorizations. All readers are activated and perform a scan for ID's or access authorizations, which can be contained or stored in at least one customer medium. The selected ID's or access authorizations are transmitted to a controller which temporarily stores and transmits them to an evaluation unit (1) while the readers continue to scan for possible ID's or access authorizations. If an evaluation in the evaluation unit finds that a selected access authorization is valid or allocated to a selected ID, the readers are deactivated, and access is granted. If, after a prescribed time, no further ID's or access authorizations are read out, transmitted and recognized as valid, then access is denied.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 13, 2019
    Assignee: Skidata AG
    Inventors: Anders Malmborg, Thomas Grasmann, Andreas Fellner
  • Patent number: 10372650
    Abstract: Circuits, methods, and apparatus that may improve networking techniques for transferring data among various electronic devices. One example may provide sharing data among various devices by daisy-chaining devices together. That is, several devices may be connected to each other through a series of cables to form a chain of devices. In this physical configuration, data may be shared among multiple devices using a series of single-hop virtual tunnels. Alternatively, a number of tunnels may be formed by a host device, each having a target device in the daisy chain. Each tunnel may originate at the host device and terminate at their target device. Each tunnel may bypass devices between the host device and the tunnel's target device. These two techniques may also be combined. Another example may provide a method of simplifying the routing of high-speed data signals through a network topology.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 6, 2019
    Assignee: APPLE INC.
    Inventor: Eric W. Anderson
  • Patent number: 10372644
    Abstract: Provided is a programmable controller capable of simplifying handshake processing between control devices. The programmable controller, which performs the handshake processing in conjunction with a reception-side device, is provided with an output signal area in which a signal to be output to the reception-side device is held, an input signal area in which a signal output by the reception-side device is held, a sequential program execution part configured to execute a sequential program, an output signal temporary area in which an output signal from the sequential program is held, and a handshake processing part configured to copy a signal state of the output signal temporary area in the output signal area and hold the signal state of the output signal area so that the input signal area is notified of a completion signal.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 6, 2019
    Assignee: FANUC CORPORATION
    Inventor: Akihiro Matsumoto
  • Patent number: 10366037
    Abstract: Present disclosure relates to a method for managing a docking device and the docking device thereof. The docking device is configured with a processor and at least two coupling ports. The method comprises following steps: electrically coupling a computer and/or at least one peripheral device to the at least two coupling ports respectively; retrieving a plurality of characteristic profiles by the processor, wherein each of the characteristic profiles is retrieved from each of the at least two coupling ports; receiving, by the processor, an input signal from the computer or the at least one peripheral device; and changing the characteristic profiles based on the input signal by the processor.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 30, 2019
    Assignee: I/O INTERCONNECT, LTD.
    Inventors: Johnny Hsiang-Yu Chen, Chih-Hsiung Chang, Tsung-Min Chen, Hsiang-Ling Wang
  • Patent number: 10360092
    Abstract: A hybrid approach using hardware and software is used for report management in peripheral component interconnect (PCI) express devices. The device hardware detects an error associated with a transaction with a host computer. The device software identifies a function associated with the error and determines various attributes of the error. The device software then exposes the attributes of the error in the PCI express and the advanced error reporting (AER) capabilities. The error can be reported in a message transaction to the host computer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: July 23, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Hani Ayoub, Adi Habusha, Itay Poleg
  • Patent number: 10318443
    Abstract: According to the computer device and the configuration and management method of a computer device that are provided in the embodiments of the present invention, an SMM and a CPU are controlled to connect to a PCIE Switch at different stages of system startup, so that management of a PCIE device does not rely on involvement of the CPU of the computer device. In this way, the PCIE device can be configured and managed without involvement of an operating system of the computer device, and CPU resources are saved. Manageability of the computer device is improved, meeting a requirement of a large data center for simplifying computing device management. In addition, the PCIE device is connected to the PCIE Switch by using a downstream port, with no need to configure a special interface to connect to the SMM, thereby simplifying system configuration.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Dexian Su
  • Patent number: 10310985
    Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 4, 2019
    Assignee: ATI Technologies ULC
    Inventors: Dhirendra Partap Singh Rana, Conrad Lai, Jeffrey G. Cheng
  • Patent number: 10223321
    Abstract: When client-side USB redirection techniques redirect an interface as a simple device, multiple redirected interfaces can be combined on the server side into a single composite device. When redirecting an interface, the client-side proxy can include an interface hint identifying the interface number in the device arrival notification sent to the server-side agent. Upon receiving multiple device arrival notifications that each include an interface hint, the agent can recombine the appropriate information to generate composite device information which will represent a composite device that includes each interface. The agent can then provide this composite device information to the virtual bus driver to initiate the process of loading the appropriate drivers for the composite device. Accordingly, even though each redirected interface of the composite device is reported to the server-side agent individually, the operating system on the server will still see a composite device.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 5, 2019
    Assignee: DELL PRODUCTS L.P.
    Inventor: Gokul Thiruchengode Vajravel
  • Patent number: 10223012
    Abstract: A determination is made that data stored in an extent of a first storage resource is to be moved to an extent of a second storage resource. Operations that are still awaiting to start execution in the first storage resource after the data stored in the extent of the first storage resource has been moved to the extent of the second storage resource, are configured for execution in the second storage resource.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Clint A. Hardy, Matthew J. Kalos, Karl A. Nielsen, Richard B. Stelmach, Hui Zhang
  • Patent number: 10216676
    Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: February 26, 2019
    Assignee: FutureWei Technologies, Inc.
    Inventor: Wesley Shao
  • Patent number: 10210124
    Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: February 19, 2019
    Assignee: FutureWei Technologies, Inc.
    Inventor: Wesley Shao
  • Patent number: 10205537
    Abstract: A system and method are disclosed for providing electrically isolated communications between two USB2 devices. Two isolating eUSB2 repeaters are utilized to implement a digital isolation barrier between the two USB2 devices. The isolating eUSB2 repeaters are configured to broker isolated communications between the two USB2 devices using a modified eUSB2 protocol that allows the two isolating eUSB2 repeaters to interoperate across the isolating barrier. The modified eUSB2 protocol allows the two isolating eUSB2 repeaters to broker isolating communications on behalf of the USB2 devices without the use of an accurate clock signal. The modified eUSB2 protocol utilized by the isolating eUSB2 repeaters is configured in particular to support certain end-of-packet translations between USB2 data and the modified eUSB2 protocol, management of certain USB2 bus state transitions and assignment of roles to the two isolating eUSB2 repeaters.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win N. Maung, Suzanne M. Vining
  • Patent number: 10198305
    Abstract: Methods, apparatuses, and computer program products for managing a storage device using a hybrid controller are provided where the storage device comprises an internal peripheral component interconnect express (PCIe) interface to control solid state memory within the storage device. In particular embodiments, the storage device includes a first external interface configured to establish an external PCIe link and a second external interface configured to establish at least one of an external serial attached small computer system interface (SAS) link and an external serial advanced technology attachment (SATA) link. Embodiments include receiving from an external source, by the hybrid controller, a first command at the first external interface and a second command at the second external interface; and concurrently implementing, by the hybrid controller, the first command using a PCIe protocol and the second command using one of a SAS protocol and a SATA protocol.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: February 5, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Gary D. Cudak, Christopher J. Hardee, Randall C. Humes, Adam Roberts
  • Patent number: 10191867
    Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM), and an interface circuit for interfacing the system to an external posted transaction bus. Each processor has the same address map. Each fetches instructions from SLMEM, and accesses data from/to SLMEM. A processor can initiate a read transaction on the posted transaction bus by doing an AHB-S bus write to a particular address. The AHB-S write determines the type of transaction initiated and also specifies an address in a shared memory in the interface circuit. The interface circuit uses information from the AHB-S write to generate a command of the correct format. The interface circuit outputs the command onto the posted transaction bus, and then receives read data back from the posted transaction bus, and then puts the read data into the shared memory at the address specified by the processor in the original AHB-S bus write.
    Type: Grant
    Filed: September 4, 2016
    Date of Patent: January 29, 2019
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 10185690
    Abstract: Methods and systems are provided routing access requests produced by a function to a physical sharing machine on a computer interconnect fabric. Access requests are routed through a switch that includes an NTB, the NTB using an address-lookup table to ensure that access requests made by multiple physical sharing machines are appropriately isolated from one another.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 22, 2019
    Assignee: Google LLC
    Inventor: Benjamin C. Serebrin
  • Patent number: 10163508
    Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Woojong Han, Mohamed Arafa, Brian S. Morris, Mani Prakash, James K. Pickett, John K. Grooms, Bruce Querbach, Edward L Payton, Dong Wang
  • Patent number: 10152448
    Abstract: Embodiments of a resistor module of a USB interface device and a method for operating a resistor module of a USB interface device are described. In an embodiment, a resistor module of a USB interface device includes a pull-down resistor connectable to a USB power-sourcing device, a switch connected between the pull-down resistor and a fixed reference voltage, an energy storage unit connectable to the USB power-sourcing device and configured to store electrical energy in response to a current from the USB power-sourcing device, a switch control unit connected to the energy storage unit and configured to control the switch with a control signal in response to a voltage of the energy storage unit, and a glitch filter connected to the switch and to the switch control unit and configured to remove a glitch in the control signal. Other embodiments are also described.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 11, 2018
    Assignee: NXP B.V.
    Inventor: Madan Mohan Reddy Vemula
  • Patent number: 10133695
    Abstract: A High Speed Link System providing network and data transfer capabilities, implemented via standard input/output (I/O) device controllers, protocols, cables and components, to connect one or more Host computing systems, comprising a System, Apparatus and Method is claimed; and described in one or more embodiments. An illustrative embodiment of the invention connects two or more Host systems via USB 3.0 ports and cables, establishing Network, Control, Data Exchange, and Power management required to route and transfer data at high speeds, as well as resource sharing. A Link System established using USB 3.0 operates at the full 4.8 Gbps, eliminating losses inherent when translating to, or encapsulating within, a network protocol, such as the Internet Protocol. Method claimed herein describes how two or more connected Host systems, detect one another, and establish separate communication and data exchange bridges, wherein control sequences from the Hosts' application direct the operation of the Apparatus.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: November 20, 2018
    Assignee: CROSSPORT NETWORK SOLUTIONS INC.
    Inventors: Christopher Whittington, Renato Condotta
  • Patent number: 10129281
    Abstract: A method and apparatus for detecting covert routing is disclosed. In the method and apparatus, data addressed to a remote computer system are forwarded over a first network path, whereby the data is associated with a computer system of a plurality of computer systems. Further, a plurality of first network performance metrics is obtained. A likelihood of covert routing is determined based at least in part on the plurality of first network performance metrics.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: November 13, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Nicholas Alexander Allen
  • Patent number: 10120593
    Abstract: A method of controlling a temperature of a non-volatile storage device includes determining whether the temperature of the non-volatile storage device is greater than a control engagement temperature, and adjusting a data I/O performance level P when the temperature of the non-volatile storage device is greater than the control engagement temperature. The non-volatile storage device may operate at the maximum performance level in a range in which the non-volatile storage device is protected from heat.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-beom Byun, Hu Zhao, Jong-gyu Park, Do-il Kong, Chung-hyun Ryu, Eok-soo Shim
  • Patent number: 10110691
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a management controller communicatively coupled to the processor and configured to provide out-of-band management of the information handling system. The management controller may be further configured to receive video data from an external graphics controller external to a motherboard upon which the processor resides, wherein each of the external graphics controller and the management controller are endpoints of a root complex instantiated on the processor and forward the video data to a remote management console communicatively coupled to the management controller via a network.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 23, 2018
    Assignee: Dell Products L.P.
    Inventors: Janorious Rabeela, Chandrasekhar Puthillathe, Rajeshkumar Ichchhubhai Patel
  • Patent number: 10095437
    Abstract: The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Rezaul Haque, Lady Nataly Pinilla Pico
  • Patent number: 10095648
    Abstract: An apparatus includes a circuit card substrate that is associated with a network interface card. The circuit card substrate includes a connector edge to be received in a connector that is nominally associated with a slot to receive an expansion card that, when installed in a computing device, is physically enclosed within the computing device. The apparatus includes a port connector that is mounted to the circuit card substrate. The port connector is to be accessible from a region outside of the computing device when the connector edge of the circuit card substrate is received in the connector.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: October 9, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Randol D. Aldridge, James Smalls
  • Patent number: 10089260
    Abstract: A system for accessing data among at least two different electronic devices is provided. The system includes a demanding electronic device and a providing electronic device. The demanding electronic device is utilized to establish an input virtual device to execute an application on the demanding electronic device. The providing electronic device is utilized to establish an output virtual device for transmitting data from the providing electronic device to the demanding electronic device via the output virtual device, wherein the data corresponds to the application, and the providing electronic device is physically separated from the demanding electronic device. The input virtual device is established to use a first peripheral of the providing electronic device as a built-in peripheral of the demanding electronic device.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 2, 2018
    Assignee: MEDIATEK INC.
    Inventors: JenChieh Lo, Yu-Cheng Chang, Shu-Hsin Chang, Chun-Hsiung Hu, Ching-Chieh Wang
  • Patent number: 10084698
    Abstract: A port of a first integrated circuit is coupled to a first communication path. Configuration information is communicated between a connector coupled to a second device and a second integrated circuit through the port and the first communication path. The port is decoupled from the first communication path. The port is coupled to a second communication path. Data is communicated between the connector and the second integrated circuit through the port and the second communication path.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Teong Guan Yew
  • Patent number: 10083146
    Abstract: In one example in accordance with the present disclosure, a system comprises a first computing device comprising a first baseboard management controller (BMC), a second computing device comprising a second BMC, a first universal serial bus (USB) port coupled to the first BMC, a second USB port coupled to the second BMC, a multiplexor coupled to the first USB port and the second USB port, a shared USB port coupled to the multiplexor, and a chassis manager coupled to the first computing device and the second computing device. The chassis manager may connect, with the multiplexor, the shared port to the first USB port or the second USB port.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 25, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Chin-Jung Tsao, Kang-Jong Peng, Chih-Sheng Liao, Chao-Lin Hsiao
  • Patent number: 10078616
    Abstract: A system, USB Type-C connector and method are provided herein to transmit encoded data across a USB cable from a transmitter circuit included within a transmitting port of a USB Type-C connector. The method described herein may generally include detecting a voltage generated at a configuration channel (CC) pin of a transmitting port of a USB Type-C connector, setting a voltage at an output node of the transmitter circuit equal to the voltage detected at the CC pin before the output node of the transmitter circuit is connected to the CC pin, subsequently connecting the output node of the transmitter circuit to the CC pin, and transmitting the encoded data from the transmitter circuit through the CC pin to the USB cable.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 18, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Ricky Setiawan, Rex Wong Tak Ying
  • Patent number: 10073662
    Abstract: An image forming apparatus and a method of recovering errors of the image forming apparatus connectable to a server for supporting a service for error recovery of the image forming apparatus are provided. The method includes connecting, when connection with the server through a first network is restricted, to a mobile apparatus through a second network different from the first network, transmitting state information required for error recovery of the image forming apparatus to the connected mobile apparatus through the second network, receiving a control command required for error recovery of the image forming apparatus from the mobile apparatus through the second network, in response to the transmitted state information, and recovering errors of the image forming apparatus according to the received control command.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 11, 2018
    Assignee: S-Printing Solution Co., Ltd.
    Inventor: Hyun-wook Park
  • Patent number: 10067554
    Abstract: VCONN pull-down circuits and related methods are disclosed for USB Type-C connections. A device is connected through a USB Type-C connection to a separate device using connections including a CC (configuration channel) pin and a VCONN (connection power) pin. The device pulls down the VCONN pin to ground through a resistance (Ra) by applying the voltage on the CC pin to close a switch coupled between the VCONN pin and ground. The device can also be operated in a dead-battery mode where no supply voltage is present for the device. The device can also stop the pull-down on the VCONN pin after a connection is established, for example, using additional switches coupled to a pull-down control signal to remove the CC voltage and open the switch. The voltage on the CC pin can also be clamped to a desired voltage or voltage range using a voltage clamp.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 4, 2018
    Assignee: Silicon Laboratories Inc.
    Inventor: Obaida Mohammed Khaled Abu Hilal
  • Patent number: 10042777
    Abstract: Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral component interconnect express PCIE) endpoint (EP). A memory management unit (MMU), which is a hardware element, is included in the host system to provide address translation according to at least one TLB. In one aspect, the MMU is configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from the PCIE EP. In another aspect, the PCIE EP is configured to determine that the at least one TLB needs to be invalidated and provide the TLB invalidation command to invalidate the at least one TLB. By implementing hardware-based TLB invalidation in the host system, it is possible to reduce TLB invalidation delay, thus leading to increased data throughput, reduced power consumption, and improved user experience.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Assaf Shacham, Shaul Yohai Yifrach, Thomas Zeng
  • Patent number: 10045266
    Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). An operating method of a user equipment (UE) in a mobile communication system is provided. The operating method includes receiving a service through a first enhanced node B (eNB) for a first time interval period from a first timing point; and receiving the service through a second eNB for a second time interval period from a second timing point, wherein the first timing point is different from the second timing point.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jeong Kang, Sun-Heui Ryoo, Jung-Soo Jung, Jong-Hyung Kwun, Suk-Won Kim, Bong-Jhin Shin, Sung-Jin Lee
  • Patent number: 10015710
    Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). An operating method of a user equipment (UE) in a mobile communication system is provided. The operating method includes receiving a service through a first enhanced node B (eNB) for a first time interval period from a first timing point; and receiving the service through a second eNB for a second time interval period from a second timing point, wherein the first timing point is different from the second timing point.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jeong Kang, Sun-Heui Ryoo, Jung-Soo Jung, Jong-Hyung Kwun, Suk-Won Kim, Bong-Jhin Shin, Sung-Jin Lee
  • Patent number: 10014957
    Abstract: A system and method are disclosed for providing electrically isolated communications between two USB2 devices. Two isolating eUSB2 repeaters are utilized to implement a digital isolation barrier between the two USB2 devices. The isolating eUSB2 repeaters are configured to broker isolated communications between the two USB2 devices using a modified eUSB2 protocol that allows the two isolating eUSB2 repeaters to interoperate across the isolating barrier. The modified eUSB2 protocol allows the two isolating eUSB2 repeaters to broker isolating communications on behalf of the USB2 devices without the use of an accurate clock signal. The modified eUSB2 protocol utilized by the isolating eUSB2 repeaters is configured in particular to support certain end-of-packet translations between USB2 data and the modified eUSB2 protocol, management of certain USB2 bus state transitions and assignment of roles to the two isolating eUSB2 repeaters.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATION
    Inventors: Win N. Maung, Suzanne M. Vining
  • Patent number: 9991866
    Abstract: Disclosed herein is a common mode filter including: at least four coil layers, each layer having a primary coil and a secondary coil; and discontinuous parts made of an insulating material each extending between starting points of each of the primary coil and the secondary coil positioned on the lowest layer among the coil layers to ending points of each of the primary coil and the secondary coil positioned on the highest layer among the coil layers. The primary coils are connected in series from the lowest layer to the highest layer, and the secondary coils are connected in series from the lowest layer to the highest layer. The common mode filter is able to be miniaturized and has improved impedance characteristics.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: June 5, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Geon Se Chang, Won Chul Sim, Jeong Min Cho
  • Patent number: 9984024
    Abstract: A USB hub device includes an upstream port and a downstream port. A USB control circuit of the USB control circuit includes an upstream interface; a downstream interface; a first switch circuit for coupling with the upstream port; a second switch circuit for coupling with the downstream port; a control signal transmission interface coupled with the first switch circuit and the second switch circuit; and a control unit, coupled with the control signal transmission interface, configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples one of the upstream interface and the second switch circuit with the upstream port, while the second switch circuit selectively couples one of the downstream interface and the first switch circuit with the downstream port.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 29, 2018
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Neng-Hsien Lin, Luo-Bin Wang, Chong Liu, Jian-Jhong Zeng
  • Patent number: 9964595
    Abstract: A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 8, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masanori Iijima, Yuji Shintomi, Satoshi Matsumura
  • Patent number: 9965436
    Abstract: A technique, as well as select implementations thereof, pertaining to a cost-effective device interface for data input and output is described. A device may include a first circuit, a plurality of Universal Serial Bus (USB) Type C connections, and a multiplexer coupled between the first circuit and the USB Type C connections. The first circuit may include a first connection and a second connection. The USB Type C connections may include at least a SBU1 connection and a SBU2 connection. The multiplexer may be configured to switch the SBU1 and SBU2 connections of the USB Type C connections to alternatively connect to either the first connection or the second connection of the first circuit in response to receiving a switch signal.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 8, 2018
    Assignee: MEDIATEK INC.
    Inventor: Chih-Chun Lin
  • Patent number: 9934192
    Abstract: Aspects disclosed in the detailed description include peripheral component interconnect express (PCIe) hosts adapted to support remote PCIe endpoints. In this regard, a PCIe host is configured to determine a temporal distance to an attached PCIe endpoint and compare the temporal distance to a predetermined threshold value. In one aspect, the PCIe host defines a first configuration parameter for the attached PCIe endpoint if the temporal distance is greater than the predetermined threshold value. In another aspect, the PCIe host defines a second configuration parameter different from the first configuration parameter for the attached PCIe endpoint if the temporal distance is less than or equal to the predetermined threshold value. By differentiating the attached PCIe endpoints based on temporal distances, the PCIe host can support compatibly a plurality of attached PCIe endpoints regardless of physical connection distances with the attached PCIe endpoints.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 3, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Jian Shen
  • Patent number: 9921555
    Abstract: Devices can be controlled by group even when multiple devices compatible with different interface standards are connected. An iProduct identifier enabling recognition by the host side as interfaces in the same group is set in the USB 2.0 hub and USB 3.0 hub in the same publisher. The host side determines if the hubs belong to the same group based on the iProduct identifier, and coordinates operation of the USB devices to connected to the USB 2.0 hub and USB 3.0 hub determined to be in the same group.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 20, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Kawamori, Sadaaki Horiuchi, Ryu Kamei
  • Patent number: 9904642
    Abstract: A detection circuit of Universal Serial Bus (USB) is provided. A port of the USB has a first configuration channel pin and a second configuration channel pin, and the first and second configuration channel pins are disposed on opposite sides. The detection circuit includes a switch unit and a detection unit. The switch unit is coupled to the first and second configuration channel pins to sequentially provide a first voltage level of the first configuration channel pin and a second voltage level of the second configuration channel pin. The detection unit is coupled to the switch unit and correspondingly provides a state reference signal according to the first and second voltage levels.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 27, 2018
    Assignee: ITE TECH. INC.
    Inventors: Yi-Chung Chou, Dong-Shan Chen, Chih-Chieh Wu
  • Patent number: 9894509
    Abstract: A system may receive, from a dongle device (“dongle”), a connection request to receive mobile communication service (“service”) associated with a service campaign (“campaign”) for a mobile device: the mobile device being associated with a first service provider (“SP”); the dongle being associated with a second SP and the campaign; the dongle being configured to provide the service from the second SP to the mobile device; and the connection request including a dongle device identifier (“identifier”) associated with the dongle. The system may compare the identifier with stored identifiers associated with the campaign. The system may determine that the identifier is associated with the campaign if the identifier matches one of the stored identifiers and may cause a connection to be established to provide the service to the mobile device via the dongle based on the identifier being associated with the campaign.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: February 13, 2018
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Jeremy Nacer, Musa Kazim Guven, Danny C. Lui, Christopher M. Schmidt