Peripheral Bus Coupling (e.g., Pci, Usb, Isa, And Etc.) Patents (Class 710/313)
  • Patent number: 11175938
    Abstract: A hypervisor managing a virtual machine (VM) running on a host computer system, modifies a virtual machine control structure (VMCS) associated with the VM to trigger a VM exit upon detecting a transition of the VM to a specified power state. Upon detection of the VM exit, a timer is initialized to trigger another VM exit, and execution of the VM in the specified power state is resumed.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: November 16, 2021
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11108919
    Abstract: An image processing apparatus, which complies with a particular setting protocol including a procedure to receive setting information for a first communication system from an OS of an information processing device, includes a first communication interface for a first communication system, a second communication interface for a second communication system, and a controller configured to transmit, to the information processing device via the second communication interface, compliance information representing that the image processing apparatus complies with the particular setting protocol, after sharing mutual compliance recognition with the information processing device through transmitting the compliance information, receive the setting information from the OS via the second communication interface in accordance with the particular setting protocol, the mutual compliance recognition being recognition that the image processing apparatus and the OS comply with the particular setting protocol, and configure sett
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 31, 2021
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Takafumi Kai
  • Patent number: 11099623
    Abstract: Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: August 24, 2021
    Assignee: INTEL CORPORATION
    Inventors: Tarakesava Reddy K, Phani K Alaparthi, Ranganadh K S S, Shobhit Chahar
  • Patent number: 11093428
    Abstract: A convertible I/O signal processor is convertible between different operating configurations for connecting multiple field devices to the I/O signal processor by selectable types of electrical connectors such as cables, terminal blocks, and the like. The I/O signal processor includes a signal processing module connected to a signal processor and an interface module removably connected to the signal processing module. The interface module includes electrical connectors for receiving/transmitting I/O signals from and to field devices. The interface module and the signal processing module define I/O channels extending between the electrical connectors and the signal processor. The interface module in embodiments includes I/O module connectors that enable removable I/O modules to be interposed in the I/O channels.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 17, 2021
    Assignee: Phoenix Contact Development and Manufacturing, Inc.
    Inventors: Brian John Gillespie, Davis Mathews
  • Patent number: 11080221
    Abstract: A switching system includes a first switching device and a second switching device. The first switching device and the second switching device are coupled using a network. The first switching device includes a plurality of PCIe upstream ports configured to connect to at least one host, the second switching device comprises at least one PCIe downstream port configured to connect to at least one input/output (I/O) device, and the second switching device is configured to receive a first data packet from the first switching device using the network, convert the first data packet to a second data packet complying with a PCIe protocol, and transmit the second data packet to a target I/O device of the second data packet.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 3, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Hongcan Fang
  • Patent number: 11080259
    Abstract: A reliable and scalable data repository service can be supporting cooperative transactions. In an example, multiple data producers may use the data repository service to upload data in one or more transactions. Data contained in one transaction may be treated as an atomic unit. In an embodiment, the data repository service manages multiple candidate transactions associated with an election transaction such that at most one candidate transaction may begin and/or commit a given time. During a commit of a candidate transaction, the data uploaded during the candidate transaction may become associated with the election transaction. The data repository service may maintain metadata associated with each of the candidate transactions. In response to a request for data associated with the election transaction, the metadata may be used, in conjunction with a user-specified isolation level, to locate the data uploaded some of the candidate transactions for the election transaction.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 3, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Nathaniel Jonah Beckford, Seung Hyok Choi, John Kenneth White
  • Patent number: 11068427
    Abstract: An electronic device according to an embodiment of the present invention comprises: a universal serial bus (USB) interface; a processor electrically connected to the USB interface; and a memory electrically connected to the processor, wherein the memory may store instructions configured to, when executed, cause the processor to: enter a security mode; in the security mode, receive, from an external device connected to the electronic device via the USB interface, a USB class code corresponding to the external device; determine whether the USB class code is included in a white list of connectable devices allowed to be connected to the electronic device in the security mode; and control a communication connection between the external device and the electronic device according to whether the USB class code is included in the white list. Other embodiments are also possible.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Jun Kim, Dong-Rak Shin, Woo-Kwang Lee, Jae-Jin Lee
  • Patent number: 11055444
    Abstract: The disclosed computer-implemented method for controlling access to a peripheral device may include receiving an input/output request related to a process attempting to access the peripheral device. The method can also include determining an access state for the process indicative of whether the process will be allowed to gain access to the peripheral device. The access state can be based on a context property of the process. The method can further include responding to the input/output request with initiation of a virtual peripheral output from a virtual peripheral device if the access state is indicative of the process not being allowed access to the peripheral device. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: July 6, 2021
    Assignee: NortonLifeLock Inc.
    Inventor: Boovaragavan Dasarathan
  • Patent number: 11057468
    Abstract: A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: July 6, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John D. Davis, John Hayes
  • Patent number: 11016817
    Abstract: A virtualization system includes at least one storage device, a plurality of computing nodes, each computing node coupled to at least one of the storage devices, each computing node comprising a physical function (PF) agent, and a plurality of virtual machines, where the PF agent of a first computing node of the computing nodes is configured to receive from a virtual machine of the virtual machines a request for retrieving or writing data and to obtain placement information indicating a second computing node of the computing nodes for retrieving or writing data, and the PF Agent of the first computing node is configured to communicate with the PF Agent of the second computing node to retrieve data from the second computing node or write data to the second computing node based on the placement information.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 25, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Igor Vyacheslavovich Druzhinin, Peter Sergeevich Krinov, Mikhail Evgenyevich Mysov, Mikhail Valerevich Zenkovich
  • Patent number: 11003230
    Abstract: An electronic device includes a connector that includes a first terminal for receiving power from a power supply apparatus, a second terminal, a third terminal, and a fourth terminal; a control unit that controls power received from the power supply apparatus via the first terminal; and a determination unit that determines a power supply capability of the power supply apparatus by using the second terminal or the third terminal and the fourth terminal, wherein the determination unit determines the power supply capability of the power supply apparatus by using the third terminal and the fourth terminal before a predetermined transition occurs in the second terminal.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 11, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroki Kitanosako
  • Patent number: 10996734
    Abstract: An electronic device includes a connector that includes a first terminal for receiving power from a power supply apparatus, a second terminal, a third terminal, and a fourth terminal; a receiving power control unit that controls power received from the power supply apparatus via the first terminal; a determination unit that determines a power supply capability of the power supply apparatus by using the second terminal or the third terminal and the fourth terminal; and a control unit that restricts, before the power supply capability of the power supply apparatus is determined by using the third terminal and the fourth terminal, power to be received from the power supply apparatus via the first terminal when a predetermined transition occurs in the second terminal.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 4, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroki Kitanosako
  • Patent number: 10970246
    Abstract: Technologies for network interface controllers (NICs) include a computing device having a NIC coupled to a root FPGA via an I/O link. The root FPGA is further coupled to multiple worker FPGAs by a serial link with each worker FPGA. The NIC may receive a remote direct memory access (RDMA) message from a remote host and send the RDMA message to the root FPGA via the I/O link. The root FPGA determines a target FPGA based on a memory address of the RDMA message. Each FPGA is associated with a part of a unified address space. If the target FPGA is a worker FPGA, the root FPGA sends the RDMA message to the worker FPGA via the corresponding serial link, and the worker FPGA processes the RDMA message. If the root FPGA is the target, the root FPGA may process the RDMA message. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Paul H. Dormitzer, Susanne M. Balle, Sujoy Sen, Evan Custodio
  • Patent number: 10951055
    Abstract: An energy-saving hub is connected to an electronic device, an AC power source and a mobile device. The energy-saving hug includes a power supply interface, a power module, an upstream connector, a downstream connector, a main control circuit, and a system circuit. The power supply interface is used to connect to the AC power source, the power module is connected to the power supply interface, the upstream connector and the downstream are connected to the power module, and the main control circuit is connected to the power module and the upstream connector. The system circuit is connected to the upstream connector, the downstream connector and the main control circuit, wherein the system circuit is maintained in a sleep mode. When the energy-saving hub connects to the electronic device or the mobile device, the main control circuit transmits a wake-up signal to the system circuit to wake up the system circuit.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: March 16, 2021
    Assignee: Simpower Technology Inc.
    Inventor: Dong-Sheng Li
  • Patent number: 10922259
    Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 16, 2021
    Assignee: Futurewei Technologies, Inc.
    Inventor: Wesley Shao
  • Patent number: 10867643
    Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hingkwan Huen, Changho Choi
  • Patent number: 10860520
    Abstract: A system that allows access to a virtualized device is disclosed. The system may include a device, a processor, and a communication unit coupled to the device via a communication link. The device may include hardware resources configured to be shared by multiple threads executing on the processor. The communication unit may be configured to detect a request to access the device by the processor. In response to the detection of the request, the communication unit may send one or more instructions to the device via the communication link using a communication protocol.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 8, 2020
    Assignee: Oracle International Corporation
    Inventors: Rahoul Puri, Rick C. Hetherington, Harry Stuimer, Hongping Li, John R. Feehrer
  • Patent number: 10860507
    Abstract: An electronic system includes a serial system bus interface having a root complex and an end point, a command bus and a data bus coupled to the serial system bus interface, a memory device coupled to the data bus, and a direct memory access (DMA) controller coupled to both the command bus and the data bus to directly access the memory device in response to request commands which are transmitted from the root complex to the end point. The DMA controller includes a command queue in which the request commands stand by.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Wooyoung Choe
  • Patent number: 10853271
    Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Tessil Thomas, Jamshed Jalal, Andrea Pellegrini, Anitha Kona
  • Patent number: 10853303
    Abstract: An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 1, 2020
    Assignee: Oracle International Corporation
    Inventors: John R. Feehrer, Matthew Cohen, Rahoul Puri, John Johnson, Alan Adamson, Julia Harper
  • Patent number: 10853284
    Abstract: A method of handling message signaled interrupts in a computer system that uses an internal bus for communication between peripheral devices, using shared peripheral interrupt (SPI) vectors. The method includes determining whether a message signaled interrupt (MSI) needs to be allocated for a PCI-e device for an interrupt to be sent to a host. If it is determined that MSI needs to be allocated for the PCI-e device, a determination is made as to whether a Locality Specific Interrupt (LPI) register or an Interrupt Translation Service (ITS) is available to process the interrupt. If it is determined that neither the LPI register nor the Interrupt Translation Service (ITS) is available to process the interrupt, the PCI-e device is configured for SPI-based MSI generation to route the interrupt by determining an available SPI vector and assigning the available SPI vector to the PCI-e device.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 1, 2020
    Assignee: VMware, Inc.
    Inventors: Andrei Warkentin, Ye Li, Alexander Fainkichen, Cyprien Laplace
  • Patent number: 10839088
    Abstract: A method for managing embedded software modules for an electronic computer embedded in an electrical switching device for switching an electric current includes acquiring a software module including a runnable code and a service contract declaring the hardware resources required by the runnable code when it is run by the computer; installing the software module inside a host receptacle intended to form an environment for running a software module and including a memory location defined statically inside a memory of the computer and being associated with a subset of hardware resources of the computer; running the software module including a step consisting in verifying whether the operation of running of the software module respects the service contract, the running operation being allowed to continue if the service contract is respected and, otherwise, a recovery step is implemented in order to interrupt the running operation.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: November 17, 2020
    Assignee: SCHNEIDER ELECTRIC INDUSTRIES SAS
    Inventors: Vincent Bufferne, Vladimir Popovic
  • Patent number: 10795851
    Abstract: A first end point and a second end point are provided. The first end point receives data from a root complex of a first platform among platforms, each serving as a computer that executes arithmetic processing. The second end point transfers the data to a root complex of a second platform among the platforms, the data to be transferred being received at the second end point by tunneling from the first end point.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 6, 2020
    Assignee: FUJITSU CLIENT COMPUTING LIMITED
    Inventors: Tomohiro Ishida, Masatoshi Kimura
  • Patent number: 10789188
    Abstract: The disclosed system may include a central processing unit (CPU) interface board including a first standard port and a second standard port, a first peripheral board including a first augmented interface, the first augmented interface including first standard interface control signals and first additional interface control signals based on a first standard communication protocol, and a second peripheral board including a second augmented interface, the second augmented interface including second standard interface control signals and second additional interface control signals, the first standard interface control signals being connected to the first standard port, the second standard interface control signals being connected to the second standard port, and at least one of the first additional interface control signals being connected to a respective at least one of the second additional interface control signals. Various other methods, systems, and apparatus are also disclosed.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: September 29, 2020
    Assignee: Facebook, Inc.
    Inventors: Howard Winter, Peter John Richard Gilbert Bracewell, Oliver Pell
  • Patent number: 10747699
    Abstract: A bus control circuit configured to transfer access commands for performing exclusive access between a first bus specification and a second bus specification by converting from a first exclusive access command applying to the first bus specification which deals with exclusive access, into a second exclusive access command of the second bus specification which doesn't deal with the exclusive access.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 18, 2020
    Assignee: SOCIONEXT INC
    Inventors: Takayuki Otani, Teruhiko Kamigata, Takashi Kawasaki, Eiichi Nimoda
  • Patent number: 10720770
    Abstract: The disclosure provides a power supply circuit including an external power source, an ID pin provided in a universal serial bus (USB) port on a printed circuit board (PCB), and an internal power and signal management subsystem. The external power source is configured to power the internal power and signal management subsystem via the ID pin. A power supply method and a portable device are also disclosed.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: July 21, 2020
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Roger Luo, Percy Shi, Kevin Yang
  • Patent number: 10719397
    Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rekha Pitchumani, Yang Seok Ki
  • Patent number: 10678736
    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
  • Patent number: 10664417
    Abstract: Devices, systems, and methods for selectively pairing an upstream facing USB port device (UFP device) and a downstream facing USB port device (DFP device) over a network are disclosed. A controller device sends pairing commands to a selected UFP device and a selected DFP device, which then establish a connection with each other over a network. The controller device may subsequently cause the UFP device and/or the DFP device to remove the existing pairing and to instead pair with a different UFP device or DFP device. A pairing between a UFP device and a DFP device allows a host device coupled to the UFP device and a USB device coupled to the DFP device to communicate via a USB-compatible protocol.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: May 26, 2020
    Assignee: Icron Technologies Corporation
    Inventors: Sukhdeep Singh Hundal, David Patrick Frey, David Robert Meggy
  • Patent number: 10664175
    Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wentao Wu, Sompong Paul Olarig
  • Patent number: 10657090
    Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: May 19, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Win Naing Maung, Bhupendra Sharma, Huanzhang Huang, Douglas Edward Wente, Suzanne Mary Vining, Mustafa Ulvi Erdogan
  • Patent number: 10635624
    Abstract: Embodiments are generally directed to dual role capable connectors for a separable portion of a computing apparatus. An embodiment of an apparatus includes a separable physical connection to a second apparatus; a first electronic connector, the first electronic connector providing data connections for the physical connection; a plurality of additional electronic connectors, the plurality of additional connectors being supported by the first electronic connector; and a control logic to control operation of the plurality of additional electronic connectors, wherein operation of the plurality of additional electronic connectors includes each additional electronic connector being capable to operate in both a host role and a device role for the interconnection of computing systems, wherein the host role and device role may be for a first connector mode or a second connector mode, and an alternative connector mode.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 28, 2020
    Assignee: INTEL CORPORATION
    Inventor: Vijaykumar Kadgi
  • Patent number: 10592291
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a disaggregated computing architecture is presented. The method includes, receiving user commands to establish compute units among a plurality of physical computing components, each of the compute units comprising one or more of the plurality of physical computing components selected from among central processing units (CPUs), graphics processing units (GPUs), storage modules, and network interface modules. The method also includes forming the compute units based at least on logical partitioning within a Peripheral Component Interconnect Express (PCIe) fabric communicatively coupling the plurality of physical computing components, wherein each of the compute units have visibility over the PCIe fabric to the one or more of the plurality of physical computing components assigned to the associated compute units using the logical partitioning within the PCIe fabric.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: March 17, 2020
    Assignee: Liqid Inc.
    Inventors: Jason Breakstone, Christopher R. Long, James Scott Cannata
  • Patent number: 10573356
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Young-Hun Seo, Kwang-Il Park, Seung-Jun Bae
  • Patent number: 10552355
    Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: February 4, 2020
    Assignee: Icron Technologies Corporation
    Inventors: Sukhdeep Singh Hundal, Mohsen Nahvi, Remco van Steeden
  • Patent number: 10545773
    Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Vinay Raghav, Reuven Rozic, David J. Harriman
  • Patent number: 10515016
    Abstract: Examples implementations described herein involve systems and methods wherein the storage software is configured to consider the capabilities of the underlying hardware to determine the caching data method at run time. Some examples of capabilities that are considered in the example implementations include whether non-volatile memory (NVM) is available and how much NVM is available. Some examples of caching methods used include using both dynamic random access memory (DRAM) and NVM to cache write data and using only NVM to cache write data.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 24, 2019
    Assignee: HITACHI, LTD.
    Inventors: Hideo Saito, Keisuke Hatasaki
  • Patent number: 10509753
    Abstract: A peripheral component interconnect express (PCIe) physical function is coupled to a controller. The controller is configured to allocate a first portion of resources for use by the PCIe physical function. A PCIe virtual function is coupled to the controller. The is configured to allocate a second portion of resources for use by the PCIe virtual function based, at least in part, on a total number of PCIe physical functions and a total number of PCIe virtual functions associated with the apparatus.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kevin R. Duncan
  • Patent number: 10455272
    Abstract: An entertainment device initiates a configuration process of a controlling device in response to a change in an audio visual entertainment system configuration in which at least one of a plurality devices is connected to the entertainment device as an audio and/or visual source and at least one of the plurality of devices is connected to the entertainment device as an audio and/or visual output destination for the entertainment device.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 22, 2019
    Assignee: Universal Electronics Inc.
    Inventors: Paul D. Arling, Patrick H. Hayes
  • Patent number: 10452570
    Abstract: A system provides remote computing services using physical or virtualized computing resource instances on various host machines. An enhanced PCIe endpoint card connected to a given host machine may include a local processor (e.g., on an SOC device) that emulates PCIe compliant hardware (e.g., a USB controller) in software. A client receiving computing services from the system may redirect USB traffic from a locally-attached physical USB device (e.g., an input/output, storage, or security device) over the Internet to the enhanced PCIe endpoint card. The enhanced PCIe endpoint card may present an emulated USB controller to an application executing on the host (on the client's behalf) as a device that is locally attached at the given host machine, and the application may access the functionality of the physical USB device by exchanging commands or data with the emulated USB controller through a PCIe controller on the enhanced PCIe endpoint card.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: October 22, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Anthony Nicholas Liguori
  • Patent number: 10430362
    Abstract: According to one embodiment, a system includes first and second devices. The first device detects whether a cable is connected to the first device in a first state or a second state. The first device receives, from the second device, status information indicative of whether the cable is connected to the second device in the first state or the second state. The first device switches allocation of signal lines to contact pins of a connector of the first device to which the cable is connected, based on connection states of the first and second devices. The second device detects whether the cable is connected to the second device in the first state or the second state. The second device transmits, to the first device, a result of detection as the status information.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 1, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Client Solutions Co., Ltd.
    Inventors: Hiroaki Chiba, Koichi Senuma
  • Patent number: 10430369
    Abstract: The disclosure is related to an interface card module which is configured to be inserted into a PCIe slot on a motherboard and to be inserted with a cable electrically connected to a function chip. The interface card module includes an adapter card and a function card. The adapter card includes a mainboard, a first PCIe male connector, a socket and at least one cable connector. The first PCIe male connector, the socket and the cable connector are respectively disposed on different sides of the mainboard. The first PCIe male connector is configured to be inserted into the PCIe slot on the motherboard. The at least one cable connector is inserted with the cable. The function card has a second PCIe male connector configured to be inserted into the socket of the adapter card. In addition, the disclosure is also related to an adapter card.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 1, 2019
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Shih-Tse Chen, Ching-Chuan Huang, Chao-Hsiang Huang
  • Patent number: 10425360
    Abstract: A system that includes (i) a device having connectors connected to pluggable modules external to the device and (ii) the pluggable modules exchanging signals with the device via the connectors. In particular, the pluggable modules includes a first pluggable module and a second pluggable module that further exchange a supplemental signal with each other and bypassing the connectors.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: September 24, 2019
    Assignee: Ciena Corporation
    Inventors: Kevin Estabrooks, Daniel Rivaud, Michael J. Windgrove
  • Patent number: 10417168
    Abstract: According to an embodiment, a system, a method, and/or a computer program product is provided to allow a choice of allocating resources of a processor host bridge (PHB) at initial setup of a computer system to a group of peripheral component interconnect express (PCI-E) slots via a PCI-E switch, or alternatively to allocate resources of the PHB directly to a single PCI-E slot. The system may include a PHB, a first switch connected to the PHB, where the first switch is a simple circuit, a second switch connected to the first switch, where the second switch is a simple circuit, a PCI-E switch connected to the first switch and connected to the second switch, and a first PCI-E slot connected to the second switch.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Ellen M. Bauman, Daniel Larson, Timothy J. Schimke
  • Patent number: 10417160
    Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 17, 2019
    Assignee: FutureWei Technologies, Inc.
    Inventor: Wesley Shao
  • Patent number: 10417144
    Abstract: A bridge device including a first connector, a first transceiver, a second connector, a second transceiver, a voltage processor, and a controller is provided. The first connector is configured to couple to a host and includes a first pin. The first transceiver is coupled between the first pin and a node and includes a first current limiter. The second connector is configured to couple to a peripheral device and includes a second pin. The second transceiver is coupled between the node and the second pin and includes a second current limiter. The voltage processor processes the voltage of the node to generate an operation voltage. The controller receives the operation voltage to determine whether to turn on at least one of the first and second transceivers.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 17, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Tze-Shiang Wang
  • Patent number: 10387182
    Abstract: Methods, systems, or apparatus may be directed to hosting, by a virtual machine manager of a local machine, a virtual machine having a device driver. A virtual machine manager may obtain, from a stub driver on a remote machine, information about the I/O device on the remote machine. The I/O device may be bound to a stub driver on the remote machine. The virtual machine manager may instantiate a virtual I/O device on the local machine corresponding to the I/O device on the remote machine. The virtual machine manager may then collaborate with the stub driver on the remote machine to effectuate a real access to the I/O device on the remote machine for an access to the virtual I/O device by the device driver on behalf of a program on the local machine.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Zhefu Jiang, Shoumeng Yan, Gansha Wu
  • Patent number: 10387346
    Abstract: A system and method for dynamic reconfiguration of at least one peripheral bus switch of a system includes a management controller that detects whether a server system is connected to each peripheral bus slot of the system. The management controller selects a peripheral bus switch topology for the at least one peripheral bus switch, based on the detecting. The management controller sets each port of the at least one peripheral bus switch to either an upstream port configuration or a downstream port configuration, based on the peripheral bus switch topology.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 20, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventors: Hsiao-Tsu Ni, Shuen-Hung Wang, Chia-Ju Lee
  • Patent number: 10382432
    Abstract: A method of reading out access authorizations or ID's from at least one customer medium by at least one reader (3, 4, 5) of an access control device (2) and evaluating the selected ID's or access authorizations. All readers are activated and perform a scan for ID's or access authorizations, which can be contained or stored in at least one customer medium. The selected ID's or access authorizations are transmitted to a controller which temporarily stores and transmits them to an evaluation unit (1) while the readers continue to scan for possible ID's or access authorizations. If an evaluation in the evaluation unit finds that a selected access authorization is valid or allocated to a selected ID, the readers are deactivated, and access is granted. If, after a prescribed time, no further ID's or access authorizations are read out, transmitted and recognized as valid, then access is denied.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: August 13, 2019
    Assignee: Skidata AG
    Inventors: Anders Malmborg, Thomas Grasmann, Andreas Fellner
  • Patent number: 10380041
    Abstract: A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster and configures the computer cluster to provide resources for the applications in accordance with the allocation. The cluster may include a Peripheral Component Interconnect express (PCIe) fabric. The cluster manager may configure PCIe multi-root input/output (I/O) virtualization topologies of the computer cluster. The allocations may satisfy Quality of Service requirements, including priority class and maximum latency requirements. The allocations may involve splitting I/O traffic.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: August 13, 2019
    Assignee: Dell Products, LP
    Inventors: Shyamkumar Iyer, Matthew L. Domsch