Peripheral Bus Coupling (e.g., Pci, Usb, Isa, And Etc.) Patents (Class 710/313)
  • Patent number: 8856555
    Abstract: A system and method of coordinating power states between two detachable units is disclosed. Only the primary unit has a user-controllable power control. The secondary unit is not directly user controllable. The power states of the two units are coordinated using an actuator mechanism when the units are attached. When the two units are detached, the state of the secondary unit is dependent upon the state of the primary unit and any subsequent commands transmitted by the primary unit to the secondary unit.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: October 7, 2014
    Assignee: Fluke Corporation
    Inventors: Paul H. Heydron, Christopher Rayburn, Jeffrey C. Hudson
  • Publication number: 20140298072
    Abstract: A method of determining the downstream propagation time of signals from a USB Host Controller across one or more USB cables and one or more USB Hubs to a SuperSpeed USB device, including locking a clock of the SuperSpeed USB device to information that includes a first timestamp, transmitting a plurality of signals to the USB Host Controller, each of the signals containing a second timestamp indicative of a local time of the SuperSpeed USB device when the respective signal was generated by the SuperSpeed device; the USB Host Controller creating a third timestamp indicative of a time of reception from the SuperSpeed USB device; determining a time period from one or more respective time differences between corresponding second and third timestamps, the time period being indicative of a sum of a downstream propagation time and an upstream propagation time; and determining the downstream propagation time from the time period.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Inventor: Peter Graham FOSTER
  • Publication number: 20140297915
    Abstract: An electronic device includes a peripheral component interface (PCI) port, a first storage unit storing a basic input/output system (BIOS), a second storage unit storing a relationship table defining a number of register values and PCI setting information, and a processing unit. The PCI port is used to connect to at least one PCI device. The first storage unit stores a basic input/output system (BIOS). The processing unit runs the BIOS when the electronic device is starting up. When the BIOS is running, the BIOS reads a register value from the PCI device connected to the PCI port and determines a setting information of the PCI port corresponding to the register value according to the relationship table. The BIOS then sets the pins the PCI port according to the determined setting information.
    Type: Application
    Filed: December 6, 2013
    Publication date: October 2, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHIH-HUANG WU
  • Patent number: 8850098
    Abstract: A method and apparatus is described herein for supporting direct memory accesses between peer I/O devices. It is determined whether a guest physical address (GPA) referenced by an access generated from an I/O device, is within a range of GPAs associated with local I/O devices based at least in part on a GPA base and a GPA window size. If the GPA is within the window, then the GPA is translated to an HPA based at least in part on a base HPA associated with a local device and then forwarded to that local device. However, if the GPA is not within the window, then the access is forwarded upstream.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Rajesh Madukkarumukumana, James A. Sutton, II, Ioannis Schoinas, Richard Uhlig
  • Patent number: 8850250
    Abstract: Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Lily Pao Looi, Stephan J. Jourdan, Selim Bilgin, Sin S. Tan, Anant S. Deval, Srikanth T. Srinivasan
  • Patent number: 8843689
    Abstract: Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: David R. Engebretsen, Brian G. Holthaus, Jonathan L. Kaus, Eric G. Thiemann, Robert W. Todd
  • Patent number: 8843688
    Abstract: Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: David R. Engebretsen, Brian G. Holthaus, Jonathan L. Kaus, Eric G. Thiemann, Robert W. Todd
  • Publication number: 20140281110
    Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.
    Type: Application
    Filed: December 9, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jerome F. DULUK, Jr., Cameron BUSCHARDT, James Leroy DEMING, Brian FAHS, Mark HAIRGROVE, John MASHEY
  • Publication number: 20140281106
    Abstract: A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCIe driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCIe controller to the host system as well as from the host system to the PCIe controller. The PCIe controller processes the I/O request descriptors and determines which device is involved in the specified movement of data. The PCIe controller generates I/O commands that contain routing information for the device (e.g., memory addresses and steering information) to route the data between the memory address of the host system and the memory address of the device, bypassing a memory of the PCIe controller.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LSI CORPORATION
    Inventors: Eugene Saghi, Richard Solomon, Timothy E. Hoglund
  • Publication number: 20140281109
    Abstract: A microcontroller for a peripheral hub includes a plurality of host bus interface microdrivers and a corresponding plurality of host transports. A first manager client, associated with a supported peripheral device, processes messages from a first host. A host manager module routes asynchronous communications, including but not limited to HID input reports, from a client to a host via one of a plurality of supported transports via a targeted transport indicated in the communication. The host manager modules routes synchronous communications from a host to a client via a targeted transport selected from a plurality of transports.
    Type: Application
    Filed: March 16, 2013
    Publication date: September 18, 2014
    Applicant: Intel Corporation
    Inventor: James Trethewey
  • Publication number: 20140281108
    Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Akshay G. Pethe, Mahesh Wagh, Manjari Kulkarni
  • Publication number: 20140281107
    Abstract: A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Luiz Andre Barroso, James Laudon
  • Publication number: 20140281104
    Abstract: According to certain aspects, the present invention relates to a system and method of sending PCI Express video data over a lower speed Ethernet connection. In embodiments, a system according to the invention includes bridges at either end of an Ethernet connection that is disposed between a PCIe host and a PCIe device. According to aspects of the invention, the slower Ethernet connection can be used by forcing the faster PCIe link to operate at a slower rate than is possible, forcing a PCIe device with a large number of lanes to use only a single lane, forcing a PCIe link to use the shortest possible packet size and/or controlling the time when UpdateFC DLLP packets are sent.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventor: Sofin Raskin
  • Patent number: 8838865
    Abstract: An adapter card adapting the ad hoc resource add/removal inherent to a host PCI or PCI Express-based system to a wireless link and wireless endpoint. The adaptation allows mobile PCI Express resources to ingress and be allocated system resources within a host's PCI system and then egress and have the allocated resources freed up for re-use/reassignment, emulating the hot plug insertion and removal of an adapter card. The invention leverages the i-PCI protocol as defined by U.S. patent application Ser. No. 12/148,712, filed Apr. 21, 2008, the teachings which are incorporated by reference.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: September 16, 2014
    Assignee: Nuon, Inc.
    Inventor: David A. Daniel
  • Patent number: 8838867
    Abstract: A means for extending a PCI System of a host computer via software-centric virtualization. A Root Complex is virtualized at the host computer, and physically separated with a portion located remotely at an Endpoint, such as at a Remote Bus Adapter. One aspect of the invention avoids the need for a Host Bus Adapter. The invention utilizes 1 Gbps-10 Gbps or greater connectivity via the host's existing standard LAN adapter along with unique software to form the virtualization solution. The invention works within a host's PCI Express topology, extending the topology by adding an entire virtual I/O hierarchy via virtualization. The invention enables I/O virtualization in those implementations where a specialized host bus may not be desirable or feasible. Some examples of this may be a laptop computer, an embedded design, a cost-sensitive design, or a blade host where expansion slots are not available or accessible.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 16, 2014
    Assignee: Nuon, Inc.
    Inventor: David A. Daniel
  • Patent number: 8838868
    Abstract: A communication port and connector are described. A mobile computing device may include a hardware element, with the hardware element being communicatively coupled to a connection. The connection is communicatively coupled to a communication port, and the communication port includes a first pin and a second pin. Additionally, at least one of the first pin and the second pin is comprised of a ferromagnetic material. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Matthew Tippett
  • Patent number: 8838869
    Abstract: In one embodiment, a multi-protocol communication circuit is provided. The communication circuit includes a plurality of protocol bridge circuits, each configured to convert data between a first format and a respective second format corresponding to a respective communication protocol. A switch network provides routable connections between the protocol bridge circuits and one or more interface circuits. Each interface circuit is configured to convert data between the first format and a raw data format. Due to the common first format, an interface circuit may be configured for select ones of different communication protocols by routing data in the first format between the interface circuit and a protocol bridge circuit corresponding to the select one of the different communication protocols.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: September 16, 2014
    Assignee: Xilinx, Inc.
    Inventor: Kiran S. Puranik
  • Publication number: 20140258584
    Abstract: A bus relay apparatus includes: an upstream port unit to which a USB host is connected; a downstream port unit to which a USB device is connected; an upstream port control unit; a downstream port control unit; and a relay unit configured to relay a packet transferred between the upstream port unit and the downstream port unit. In the bus relay apparatus, the downstream port unit reproduces a bus status detected by the upstream port unit and transmits the bus status, and the upstream port unit reproduces a bus status detected by the downstream port unit and transmits the bus status.
    Type: Application
    Filed: February 24, 2014
    Publication date: September 11, 2014
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Takuya ISHIDA
  • Patent number: 8832470
    Abstract: Described embodiments provide for a regulated voltage supply to a Universal Serial Bus (USB) system. The regulator comprises a pass device that might be coupled to a host device providing a bus voltage. An integrated USB physical layer (PHY) is coupled to the pass device through a control voltage signal pin. A regulation circuit is coupled to the integrated USB PHY, and the regulation circuit supplies about 3.3V from the bus voltage.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 9, 2014
    Assignee: LSI Corporation
    Inventors: Brian K. Mueller, Ricky F. Bitting
  • Publication number: 20140250254
    Abstract: An apparatus performs a method for connecting a mobile terminal to an external device. The method includes determining a connection method of the external device among a plurality of connection methods based on values of at least two ports among a plurality of ports included in a connector, and switching at least one switch included in the connection unit so as to connect to the external device according to the determined connection method of the external device.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 4, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: One-Gun Lee, Woo-Jong Yoo, Hyun-Ho Park, Ju-Pyo Hong
  • Publication number: 20140250253
    Abstract: Particular embodiments described herein can offer an electronic fabric for a processing system that includes a fabric adapter to couple to a first fabric associated with a first system and to couple to a second fabric associated with a second system. The fabric adapter is configured to pass bidirectional communications between the first system and the second system. The electronic fabric can further include an address translation agent configured to map a first physical address in a first address space of the first system to a second physical address in a second address space of the second system.
    Type: Application
    Filed: October 3, 2012
    Publication date: September 4, 2014
    Inventors: Sai Luo, Xin Zhou, Chunxiao Lin, Yingzhe Shen, Li Shang
  • Patent number: 8823403
    Abstract: An exemplary load circuit includes a switch unit and a current dividing circuit. The switch unit includes a number of switches. The current dividing circuit includes a number of sub-circuits. A terminal of a resistance module of each of the sub-circuits is connected to both a power terminal and a terminal of a corresponding one of the switches. The other terminal of the resistance module of each of the sub-circuits is connected to a drain of a transistor of each of the sub-circuits. A source of the transistor is connected to ground. A gate of the transistor is connected to ground, and is also connected to another terminal of the corresponding switch.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: September 2, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Zhen-Sen Li, Jian-She Shen
  • Publication number: 20140244888
    Abstract: An adapter includes a network interface module configured to interface the adapter to a network and a Peripheral Component Interconnect Express (PCIe) interface module configured to interface the adapter to a PCIe bus. The PCIe interface module comprises registers in PCIe extended configuration space. The registers are configured to receive ioctls from the PCIe bus. The adapter also includes an ioctl processing module configured to receive the ioctls from the registers, to perform the ioctls, and to provide results of the ioctls to the registers for provision by the registers to the PCIe bus. The ioctls comprise commands that relate to transceiving of frames by the adapter on the network. The network interface may be Ethernet, Fibre Channel, Infiniband, etc. Examples of the ioctls include retrieving operation or error statistics, setting virtual channel tag and priorities, and setting a protocol address associated with a port of the adapter.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 28, 2014
    Applicant: EMULEX DESIGN AND MANUFACTURING CORP.
    Inventor: Jayamohan Kallickal
  • Patent number: 8819319
    Abstract: A PCI card's HBA identifier table held in an IODC in an IO slot expansion unit is read and recorded on a PCIe switch register of a PCIe switch. After a server blade is powered on so that an EFI is activated, the EFI reads the HBA identifier table recorded on the PCIe switch register and updates an HBA identifier of an HBA mounted in each PCI card. The HBA mounted in the PCI card operates with the updated HBA identifier of the PCI card. Thus, even when the PCI card is replaced by a new PCI card because of failure or the like, the new PCI card can operate with the same HBA identifier as that before the replacement. Therefore, a user does not have to register the HBA identifier of the PCI card newly in a device connected to the PCI card.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: August 26, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihide Shirai, Mitsuaki Watanabe
  • Publication number: 20140237154
    Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.
    Type: Application
    Filed: April 25, 2014
    Publication date: August 21, 2014
    Inventors: Arvind Mandhani, Woojong Han, Ken Shoemaker, Madhu Athreya, Mahesh Wagh, Shreekant S. Thakkar
  • Publication number: 20140237155
    Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.
    Type: Application
    Filed: April 25, 2014
    Publication date: August 21, 2014
    Inventors: Ken Shoemaker, Mahesh Wagh, Woojong Han, Madhu Athreya, Arvind Mandhani, Shreekant S. Thakkar
  • Publication number: 20140237153
    Abstract: A method for sending readiness notification messages to a root complex in a peripheral component interconnect express (PCIe) subsystem. The method includes receiving a device-ready-status (DRS) message in a downstream port that is coupled to an upstream port in a PCIe component. The method further includes setting a bit in the downstream port indicating that the DRS message has been received.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 21, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Stephen David GLASER, Christian Edward RUNHAAR
  • Patent number: 8812760
    Abstract: An example method is provided and includes receiving a first signal transmitted to an address on a two-wire bus from a master device, where the two-wire bus couples the master device with a first slave and a second slave that share the address such that the first slave and the second slave receive the first signal. The method includes blocking a second signal from the second slave to the master device using digital isolation buffers. In particular embodiments, the digital isolation buffers are configured between the master device and the second slave. In addition, the two-wire bus may include a clock line and a data line. The digital isolation buffers may include a first digital isolation buffer located on the clock line between the master device and the second slave, and a second digital isolation buffer located on the data line between the master device and the second slave.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Harold E. Bamford, Ted R. Mila
  • Patent number: 8813098
    Abstract: A method to interact with a local USB device is disclosed. Messages are transmitted to a remote host controller driver from a host controller associated with the local USB device. Messages are received from the remote host controller driver for the host controller. In some embodiments, a transfer descriptor prototype is received from the remote host controller driver. A completed transfer descriptor is received from the remote host controller driver. The completed transfer descriptor and the transfer descriptor prototype are transformed into a modified transfer descriptor in part by using a collection of rules. The modified transfer descriptor is submitted to the local host controller without intervention from the remote host controller driver.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nils Bunger, Aly E. Orady, Matthew B. Debski, Pankaj Garg, Dali Kilani, Teju Khubchandani, Himadri Choudhury
  • Patent number: 8806100
    Abstract: Circuits, methods, and apparatus that reduce the power consumed by transactions initiated by a number of USB host controllers. Peripheral devices on a number of USB networks are accessed in a coordinated manner in order to reduce power dissipated by a CPU and other circuits when reading data needed by the host controllers. The resulting memory reads are temporally clustered. This allows the CPU to process a greater number of requests each time it leaves a low-power state. As a result, the CPU may possibly remain in a sleep state for a longer period of time, thus saving power. This is accomplished at the host controller level by synchronizing the time frames used by each host controller in a system. The synchronizing signal may be one or more bits of a frame count provided by one host controller to a number of other frame controllers.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: August 12, 2014
    Assignee: NVIDIA Corporation
    Inventors: John Berendsen, Robert Chapman
  • Patent number: 8799548
    Abstract: An I/O bridge device includes: a command receiver that receives a command signal indicating a command to a memory controller from a peripheral component; a converter that converts the command signal into a command packet including the command and identification information for identifying the command signal; a command transmitter that transmits the command packet to the memory controller; a response receiver that receives, from the memory controller, a response packet to the command packet, the response packet including the identification information; and a write command transmitter that transmits a write command signal to the peripheral component that is a transmission source of the command signal, the write command signal indicating a command for the writing a content of the response packet to an internal memory of the peripheral component.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 5, 2014
    Assignee: NEC Corporation
    Inventor: Toshio Oohira
  • Patent number: 8799549
    Abstract: A method for transmitting data between two storage virtualization controllers (SVCs) is disclosed in the present invention.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: August 5, 2014
    Assignee: Infortrend Technology, Inc.
    Inventors: Wei-Shun Huang, Teh-Chern Chou
  • Publication number: 20140215096
    Abstract: Provided is a programmable logic system for controlling an external device including a first processor and one or more system input/output (I/O) modules coupled to the processor via an interface. The programmable logic system also includes a configurable hardware module coupled to the processor and the I/O modules via the interface.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: GE INTELLIGENT PLATFORMS, INC.
    Inventor: Gary Lawrence Pratt
  • Patent number: 8793425
    Abstract: A USB device and a detection method therefor. It can be detected whether the USB device is a master device or a slave device without the use of an ID pin, thereby saving the pin resources of the USB device.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: July 29, 2014
    Assignee: Shanghai Actions Semiconductor Co., Ltd.
    Inventors: Jing Yu, Shaobin Huang, Kui Du
  • Publication number: 20140207991
    Abstract: A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 24, 2014
    Applicant: Qualcomm Innovation Center, Inc.
    Inventors: Vinod H. Kaushik, Igor Malamant, Sergio Kolor
  • Patent number: 8788734
    Abstract: Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: July 22, 2014
    Assignee: Icron Technologies Corporation
    Inventor: Terence C. Sosniak
  • Publication number: 20140201419
    Abstract: A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 17, 2014
    Applicant: International Business Machines Corporation
    Inventors: Avraham Ayzenfeld, Emmanuel Elder, Ilya Granovsky
  • Publication number: 20140201418
    Abstract: A configurable system for translating, exchanging and integrating data and services among disparate software applications is provided. The system includes a first connection that interfaces with an enterprise system, a second connection that interfaces with a legacy system, and an adapter module coupled to the first and second connections. The adapter module is configured to receive data from the first connection and pass data to the second connection. The system may also include a transform module configured to manipulate data received at the second connection. The adapter module may be single-channel or multi-channel. A multi-channel adapter module is able to interface with multiple legacy systems and/or multiple enterprise systems.
    Type: Application
    Filed: November 14, 2011
    Publication date: July 17, 2014
    Applicant: United States Government, as represented by the Secretary of the Navy
    Inventors: Thomas G. Turner, James Alan Thomas
  • Patent number: 8781656
    Abstract: A vehicular interface may include an electromechanical interface between a handheld electronic device and subsystems on a vehicular bus or network. In selected embodiments the interface may operate in a “master mode” when a handheld device, such as a tablet computer or smart-phone, is not inserted therein. In this mode the interface may serve as a master controller and accesses and controls various subsystems on a vehicle (such as engine control subsystems, media controllers, navigation systems, sensors and transducers) as a master controller. In one embodiment, when a tablet device is inserted into the interface, the interface may automatically switch to “slave mode” in which it acts as an adapter or interface between the tablet device and the vehicular subsystems. In this mode of operation the user's exclusive interface is through the tablet computer and the tablet computer serves as the master controller for the system.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: July 15, 2014
    Assignee: Nordic Capital Partners, LLC
    Inventors: David Lieberman, Robert Turgeon, Byron Tietjen, Greg Gardella
  • Patent number: 8782319
    Abstract: An expandable hybrid storage device for a computer system includes a first storage unit, an expanded storage device including a disk controller and a second storage coupled to the disk controller via a second data transmission interface, and a selection unit coupled to the first storage unit via a first data transmission interface for selectively connecting the first storage unit to a south bridge circuit of the computer system or the expanded storage device, wherein when the expanded storage device connects to the computer system, the selection unit switches the first storage unit to the expanded storage device so that the disk controller is capable of controlling access to the first storage unit or the second storage unit.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Wistron Corporation
    Inventors: Chih-Li Wang, Pin-Hsien Su, Wen-Chin Wu
  • Patent number: 8782315
    Abstract: An expansion card and method for controlling a radio system integrates PCDD operations into a PCMCIA or ExpressCard which can be inserted into an external display, smart screen PCMCIA slot, or laptop ExpressCard or PCMCIA slot to allow an operator to control the radio system with a computer without any modification of the computer.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: July 15, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Jeffrey B. Canter, Boris Radovcic, Michael Christoff
  • Patent number: 8782318
    Abstract: Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Chandra P. Joshi, Gurushankar Rajamani
  • Patent number: 8782321
    Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Maxim Dan
  • Publication number: 20140195713
    Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.
    Type: Application
    Filed: March 13, 2014
    Publication date: July 10, 2014
    Applicant: ACQIS LLC
    Inventor: William W. Y. Chu
  • Publication number: 20140195712
    Abstract: A processor module includes at least one storage device, at least one central processing unit (CPU) that uses a preset interface, and a module controller to relay a connection between a common interface bus formed on the based board and an interface used by the CPU.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 10, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Ha-uk RYU
  • Publication number: 20140195711
    Abstract: Certain embodiments of the present disclosure are directed to a baseboard management controller (BMC) that includes a PCI express (PCIe) interface controller configured to provide access to a PCIe channel over a PCIe link, and firmware. The firmware includes a PCIe module being configured to access the PCIe channel through the PCIe interface controller and registered as a PCIe function. A software stack of the BMC communicates, through the PCIe module, with a PCIe device over the PCIe channel.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: AMERICAN MEGATRENDS, INC.
    Inventors: Anurag Bhatia, Rama Bisa
  • Patent number: 8775712
    Abstract: A detecting unit detects a connection of an external device to a connection port and stores the connection in a bridge state storage unit. This setting is autonomously completed by a device before an initial configuration is started by a host. A data transfer unit receives initial configuration data of a link-connection bridge from the host. Data is transferred to the linked-uplink-connection bridge with reference to the bridge state storage unit, data to a bridge which is not linked up is wasted, or an Unsupported Request is returned to the host to represent the absence of the link-connection bridge.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: July 8, 2014
    Assignee: NEC Corporation
    Inventors: Jun Suzuki, Youichi Hidaka, Takashi Yoshikawa
  • Patent number: 8775691
    Abstract: An indication of a version of a firmware stored in an input/output adapter may be provided by a method that includes detecting whether a first pin is connected to an external circuit, detecting whether a second pin is unconnected to an external circuit, and causing the indication to be provided if the first pin is connected and the second pin is unconnected. The indication may be provided on the first pin. The first pin may include a power supply pin and the indication may be an average rate of power supplied to the input/output adapter.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cary L. Bates, Justin K. King, Lee Nee, Michelle A. Schlicht
  • Patent number: 8774055
    Abstract: A method for providing identifiers for virtual devices in a network. The method comprises receiving a discovery data packet directed to a physical network node associated with a physical endpoint device. A response to the discovery data packet directed to a physical network node is provided, the response comprising an identifier of a virtual device. At least one further discovery data packet directed at least to said virtual device is received. A response to a first one of the further discovery data packets is provided, the response comprising an identifier of a virtual endpoint device. At least some functionality of the virtual endpoint device is provided by the physical endpoint device.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Finbar Naven, Marek Piekarski
  • Patent number: 8769180
    Abstract: Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Gregg, David F. Craddock, Eric N. Lais