Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Abstract: A serial attached SCSI (SAS) system may include a host bus adaptor, a bus expander, and a multi-layer data transmission medium coupled between the host bus adaptor and the bus expander. The multi-layer data transmission medium may include a first microstrip structure located at a top surface portion of the multi-layer data transmission medium and a first stripline structure located within a first internal portion of the multi-layer data transmission medium. The microstrip structure provides, among other things, a repeaterless high-speed serial communications link between the host bus adaptor and the bus expander.

Abstract: A data storage device including a first storage unit comprising a first media of a first type and an enclosure defining an aperture, a printed circuit board assembly (“PCBA”) located below the first storage unit, wherein the PCBA comprises a bridge unit and a host interface for connecting the data storage device to a host, and a second storage unit located above the first storage unit and comprising a second media of a second type different than the first type and a communications interface configured to be connected to the bridge unit through the aperture.

Abstract: Methods and apparatus, including computer program products, are provided for connector interface mapping. In one aspect there is provided a method. The method may include detecting, at a first device, an orientation of a data connector connectable to a data interface, the data interface having a first portion and a second portion, the first portion coupled to a single port of a first type at the first device; sending, by the first device, the detected orientation information to a second device; and receiving, at the first device including the single port, data sent by the second device to the single port. Related apparatus, systems, methods, and articles are also described.

Abstract: A Universal Serial Bus (USB) apparatus for USB communication is provided. The USB apparatus includes a Printed Circuit Board (PCB) including a circuit for communicating data with an external device according to a USB communication standard, a connector for connecting to a USB terminal of the external device, and a noise reduction circuit connected between an output terminal of the PCB and the connector for reducing noise of a data signal. The noise reduction circuit includes a common-mode filter for removing harmonic components generated between a ‘+’ data signal and a ‘?’ data signal and passing the ‘+’ data signal and the ‘?’ data signal, which operate in a differential mode.

Abstract: A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module.

Abstract: A system for managing internal-computer system communications including a processor, an SPI controller, an interconnector, and an SPI cluster containing multiple SPI interfaces, with the SPI interfaces being connected to one or more devices in the computer system or environment. The SPI cluster includes SPI interfaces that can convert communications to/from a plurality of device's formats to serialized digital formats suitable for ingest and actuation for the SPI controllers. The interconnector may use a differentially, optically, galvanometrically, inductively coupled driven wire and to enable communications between the SPI cluster constituents and the SPI controller. The SPI controller manages communications to the SPI interfaces that act as coordinated intermediates for device control and communications, thus insulating the computer system's processor from the increased workload of managing all internal system communications.

Abstract: (EN) The invention relates to an authentication device (TK) set to identify itself to a computer (PC) as a native human interface device. It also relates to a system comprising an authentication device (TK) and a computer (PC), as well as to a method to have a computer (PC) recognize an authentication device (TK).

Abstract: A data bus system includes a plurality of recording apparatuses, a transmission path, and a management apparatus. The plurality of recording apparatuses are configured to record and hold data. The transmission path is connected to the plurality of recording apparatuses by wireless communication and configured to transmit the data. The management apparatus is configured to manage the plurality of recording apparatuses and the transmission path.

Abstract: According to one aspect, a backplane controller of a storage backplane is disclosed, the storage backplane having a plurality of drive slots configured to operatively connect to a corresponding plurality of mass storage devices. In one embodiment, the backplane controller is operative to perform functions that include detecting activity status on a first serial interface that is configured to operatively connect one or more sets of a plurality of drive slots on the storage backplane to a host bus adapter (HBA), according to a first drive slot assignment. The backplane controller is further operative to detect an activity status on a second serial interface that is configured to operatively connect one or more sets of a plurality of drive slots on the storage backplane to the HBA, according to a second drive slot assignment.

Abstract: A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other.

Abstract: A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising logic circuits responsive to the processor, the scheduler circuit configured to transfer data packets to the at least one data channel via a packet based serial data communication interface and according to the first data structure.

Abstract: Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.

Abstract: An expansion card includes a PCIe connector, a non-PCIe connector, a signal switching module, and a signal processing module. The signal switching module includes a signal receiving unit and a signal transmitting unit. The PCIe connector is connected to the signal receiving unit and the signal transmitting unit. The non-PCIe connector is connected to the signal receiving unit and the signal transmitting unit. The signal processing module is connected to the signal receiving unit and the signal transmitting unit. When both of the signal receiving unit and the signal transmitting unit receive a high-level signal, the PCIe connector is connected to the signal processing module. When both of the signal receiving unit and the signal transmitting unit receive a low-level signal, the non-PCIe connector is connected to the signal processing module.

Abstract: A first circuit and a second circuit perform communication using a first end point. The second circuit and an external device perform communication using a second end point. Upon receiving receive data from the external device with communication using the second end point, the second circuit gives first information indicating the second end point to the receive data. The second circuit sends the receive data given the first information to the first circuit with communication using the first end point. The first circuit interprets the second end point based on the first information given to the received receive data.

Abstract: In general, embodiments of the present invention provide a home storage system and method of production. Specifically, in a typical embodiment, the home storage system includes a main controller that is coupled to a display controller, an external memory controller, an external interface, and a PCI-Express-based hybrid RAID controller. Further, a set of semiconductor storage device (SSD) memory units and a set of hard disk drive (HDD/Flash) memory units are coupled to the hybrid RAID controller. The external interface allows the storage system to establish network connectivity, while the external memory controller allows the storage device to be coupled to different types of external memory devices.

Abstract: Methods and devices for running network protocols over Peripheral Component Interconnect Express are disclosed. The methods and devices may receive an electronic signal comprising data. The methods and devices may also determine the data corresponds to a protocol selected from a set comprising a PCIe protocol and a network protocol. In addition, the methods and devices may also configure a CPU based on the determined protocol. The methods and devices may also receive a second electronic signal comprising second data at a pin or land of the CPU, wherein the pin or land is connected to a PCIe lane and wherein the second data is formatted in accordance with determined protocol. In addition, the methods and devices may process the second data in accordance with the determined protocol.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage cache memory in multi-cache environments. A disclosed apparatus includes a remote cache manager to identify a remote cache memory communicatively connected to a bus, a delegation manager to constrain the remote cache memory to share data with a host cache memory via the bus, and a lock manager to synchronize the host cache memory and the remote cache memory with a common lock state.

Abstract: Provided is a universal serial bus (USB) memory including a non-insertion type connector that comes into non-insertion contact with a non-insertion type port of an electronic device using magnetism and enables data transmission/reception with the electronic device, wherein the non-insertion type connector includes: a magnetic coupling member that is formed on a contact surface of a body and comes into surface contact with a magnetic coupling member formed on a contact surface of the non-insertion type port using magnetism; and a contact terminal that is formed on the contact surface and comes into non-insertion contact with the contact terminal when the magnetic coupling members are coupled to each other using magnetism, thereby enabling reciprocal power supply and data transmission.

Abstract: The disclosed inventions relate to the field of power control electronics. More specifically the disclosed inventions pertain to Power Stack Control Systems which are used to control the generation of AC power from a DC or AC input voltage. The disclosed Power Stack Control Systems include a serial interface connection, the serial interface connection being in serial electrical communication with a plurality of power stacks, the plurality of power stacks comprising at least one interface board and at least one IGBT driver board, the at least one interface board being in parallel communication with at least one IGBT driver board.

Abstract: A plug connector with external contacts is provided. The connector has one pair of contacts for transmitting data and one pair of contacts for receiving data. All data transmitted and received using the plug connector is serialized/de-serialized to enable data transmission at a very high rate. A corresponding receptacle connector has configurable contacts that are configured based on the orientation of the plug connector with respect to the receptacle connector. The receptacle connector may be included in a host device and has associated circuitry to detect orientation of the plug connector and to configure the contacts of the receptacle connector.

Abstract: Methods and systems are disclosed herein for providing a universal PCIe port. In one example, the same port is configured to accept a PCIe connection as a host or an endpoint symmetrically. Downstream transactions towards an endpoint can be intercepted and a virtual address in the downstream transaction can be translated to a local address using a mapping. The downstream transactions can be forwarded to the endpoint using the local address instead of the virtual address. For endpoints that share the same local address with multiple hosts, a reverse lookup may be provided to determine which one of the hosts a local address corresponds when forwarding upstream transactions. PCIe over Ethernet is provided as one embodiment for allowing remote PCIe endpoints to be associated with a local host transparently.

Abstract: Methods and systems are disclosed herein for providing a universal PCIe port. In one example, the same port is configured to accept a PCIe connection as a host or an endpoint symmetrically. Downstream transactions towards an endpoint can be intercepted and a virtual address in the downstream transaction can be translated to a local address using a mapping. The downstream transactions can be forwarded to the endpoint using the local address instead of the virtual address. For endpoints that share the same local address with multiple hosts, a reverse lookup may be provided to determine which one of the hosts a local address corresponds when forwarding upstream transactions. PCIe over Ethernet is provided as one embodiment for allowing remote PCIe endpoints to be associated with a local host transparently.

Abstract: Methods and systems are disclosed herein for providing a universal PCIe port. The same port can be configured to accept a PCIe component as a host or an endpoint (device) symmetrically. The PCIe port can be connected to the host interface or the root complex interface if the PCIe connection is to be configured as a host or an endpoint, respectively. A virtual topology can be provided for a host that associates the host with corresponding endpoints. A mapping between virtual addresses of the corresponding endpoints in the virtual topology and local addresses of the corresponding endpoints is provided.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: Several embodiments including methods, systems, and physical computer-readable storage media are configured to multiplex a single end-point memory (EPM) structure between a HS USB interface and a SS USB interface, which includes determining whether the SS USB interface is enabled, if the SS USB interface is enabled, detecting the SS USB interface, selecting the HS USB interface, if the SS USB interface is enabled, but not detected, and multiplexing between a functionality of a HS USB device interface and a functionality of a HS USB host interface, if the SS USB interface is not enabled.

Abstract: Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device.

Abstract: A motherboard includes a connector, an identification module, a Serial Advanced Technology Attachment (SATA) signal module, a Universal Serial Bus (USB) signal module, and a selection module. The connector is used to determine compatibility and connect a SATA-type external device with a SATA connector and a USB-type external device with a USB connector. The identification module is coupled to the connector. The identification module outputs a first signal when the connector is coupled to the SATA-type external device and outputs a second signal when the connector is coupled to the USB-type external device. The selection module connects either the SATA signal module or the USB signal module to the connector as appropriate.

Abstract: The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table.

Abstract: A communication connector is described that provides an increase in the number and type of communication circuits available on an electronic device without increasing the number and type of physical connectors. The communication connector electrically includes a set of inputs to couple to both a USB 2.0 connector and a HDMI connector. A set of outputs from the communication connector provides a third connector with a pin out specification compatible with a USB 3.0 connector or a PCIe connector.

Abstract: According to one embodiment, a first controller is connected to one of a plurality of terminals. A detector is configured to detect a connection between each of the plurality of terminals and an MHL cable. A power supply module supplies electric power to a first connected apparatus connected via a first MHL cable in response to a first connection detection between a first terminal and the first MHL cable. A second controller is configured to connect the first terminal and the first controller, in response to the first connection detection, and to connect a second terminal and the first controller, when a signal is not received from the first connected apparatus via the first terminal at a timing of a second connection detection between the second terminal and a second MHL cable.

Abstract: A method, apparatus, and system for a secondary/adjunct interface between two Integrated Circuits (ICs) already having a Peripheral Component Interconnection Express (PCIe) interface, where the PCIe interface performs high-throughput data transfers and the adjunct/secondary interface performs low-throughput data transfers, thereby reducing power consumption for the low-throughput data transfers, are described.

Abstract: A multi-protocol multiplexer provides signals according to different protocols for accessing a storage subsystem to a connector, where the signals according to a first protocol are to be routed over a first subset of channels of an interconnect to the storage subsystem, and the signals according to a second protocol are routed over a second subset of channels of the interconnect.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.

Abstract: An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.

Abstract: Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag information inserted into the MRds responsive to detecting the reset. Additionally, the control unit analyzes tag information of received MRCs to determine whether it is the revised tag information or is old tag information, returns completion data from MRCs having the revised tag information to the host device, and discards completion data from received MRCs having the old tag information.

Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.

Abstract: A network switch, based on the PCI Express protocol, is disclosed. The switch is in communication with a processor, local memory and includes a plurality of non-transparent bridges and, optionally transparent bridges, leading to PCI Express endpoints. By configuring the non-transparent bridges appropriately, the network switch can facilitate simultaneous communication between any two sets of servers without needing to store any data in the local memory or FIFO resources of the switch. For example, the network switch may configure the non-transparent bridges so as to have access to the physical memory of every server attached to it. It can then move data from the memory of any server to the memory of any other server.

Abstract: According to one aspect, a data storage system is disclosed.

Abstract: Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral.

Abstract: According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

Abstract: Techniques for performing positioning in a cellular network are described. In one design, a first base station (e.g., a home base station) determines its position based on position information for at least one user equipment (UE) within radio coverage of the first base station and a second base station. The first base station sends at least one position request for the at least one UE to the second base station, receives position information for the at least one UE from the second base station, and determines a position estimate for itself based on the position information. In another design, the second base station receives a position request for the first base station, obtains position information for at least one UE, determines a position estimate for the first base station based on the position information, and sends the position estimate to the first base station.

Abstract: A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-state memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory.

Abstract: A connector assembly for connecting a peripheral device to a computer includes a male connector having a plurality of first connecting pins and a female connector having a plurality of second connecting pins. The plurality of first connecting pins is configured to connect to the peripheral device. The plurality of second connecting pins is configured to connect to the computer. The plurality of second connecting pins is defined on the first circuit board in a second row and a third row. The plurality of second connecting pins comprises a plurality of differential pairs, and each differential pair comprises two differential transmission lines. The two differential transmission lines of each of the plurality of differential pairs are defined on a single row of the second and third rows.

Abstract: An apparatus and method are disclosed in which unrelated completion operations intended for a single destination (requestor) are coalesced to improve achievable data bandwidth. During transmission, the completion operations are collected and compressed into a single packet and transmitted along the link. At a receiving end of the link, the single packet is decompressed and the previously unrelated packets are returned to their initial state before receipt by the requestor. The method can be implemented in the root complex, end points, and/or switches, in the case of a PCIe implementation, but can also be applied to other protocols besides PCIe.

Abstract: An image processing apparatus includes a chipset unit which processes data; a connector which includes a plurality of terminals, and is configured to connect with a cable so that the chipset unit can transmit and receive a signal to and from an external device; a switching unit which supplies power to the external device through a first terminal of the connector, and selectively controls a switching operation regarding whether or not to supply power to the first terminal on the basis of a signal state of a second terminal of the connector when the cable is connected to the connector. A control method of the image processing apparatus is also disclosed.

Abstract: The method relates to a Universal Plug and Play AV system, which comprises a media server included in a server device having a digital interface, to which a removable storage device is coupled, a media renderer included in a display device and a control point included in a control device for controlling the server device and the display device via Universal Plug and Play AV actions. The method comprises the steps of arranging an unmount icon in the display of the control device, unmounting the storage device in case said unmount icon is operated, and providing a feedback on the display device and/or the control device after said unmount action was performed on the server device.

Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a data packet for communication along an interconnect and to transmit the data packet. This data packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.