Abstract: An energy-saving hub is connected to an electronic device, an AC power source and a mobile device. The energy-saving hug includes a power supply interface, a power module, an upstream connector, a downstream connector, a main control circuit, and a system circuit. The power supply interface is used to connect to the AC power source, the power module is connected to the power supply interface, the upstream connector and the downstream are connected to the power module, and the main control circuit is connected to the power module and the upstream connector. The system circuit is connected to the upstream connector, the downstream connector and the main control circuit, wherein the system circuit is maintained in a sleep mode. When the energy-saving hub connects to the electronic device or the mobile device, the main control circuit transmits a wake-up signal to the system circuit to wake up the system circuit.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

Abstract: An electronic system includes a serial system bus interface having a root complex and an end point, a command bus and a data bus coupled to the serial system bus interface, a memory device coupled to the data bus, and a direct memory access (DMA) controller coupled to both the command bus and the data bus to directly access the memory device in response to request commands which are transmitted from the root complex to the end point. The DMA controller includes a command queue in which the request commands stand by.

Abstract: A system that allows access to a virtualized device is disclosed. The system may include a device, a processor, and a communication unit coupled to the device via a communication link. The device may include hardware resources configured to be shared by multiple threads executing on the processor. The communication unit may be configured to detect a request to access the device by the processor. In response to the detection of the request, the communication unit may send one or more instructions to the device via the communication link using a communication protocol.

Abstract: A method of handling message signaled interrupts in a computer system that uses an internal bus for communication between peripheral devices, using shared peripheral interrupt (SPI) vectors. The method includes determining whether a message signaled interrupt (MSI) needs to be allocated for a PCI-e device for an interrupt to be sent to a host. If it is determined that MSI needs to be allocated for the PCI-e device, a determination is made as to whether a Locality Specific Interrupt (LPI) register or an Interrupt Translation Service (ITS) is available to process the interrupt. If it is determined that neither the LPI register nor the Interrupt Translation Service (ITS) is available to process the interrupt, the PCI-e device is configured for SPI-based MSI generation to route the interrupt by determining an available SPI vector and assigning the available SPI vector to the PCI-e device.

Abstract: An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.

Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.

Abstract: A method for managing embedded software modules for an electronic computer embedded in an electrical switching device for switching an electric current includes acquiring a software module including a runnable code and a service contract declaring the hardware resources required by the runnable code when it is run by the computer; installing the software module inside a host receptacle intended to form an environment for running a software module and including a memory location defined statically inside a memory of the computer and being associated with a subset of hardware resources of the computer; running the software module including a step consisting in verifying whether the operation of running of the software module respects the service contract, the running operation being allowed to continue if the service contract is respected and, otherwise, a recovery step is implemented in order to interrupt the running operation.

Abstract: A first end point and a second end point are provided. The first end point receives data from a root complex of a first platform among platforms, each serving as a computer that executes arithmetic processing. The second end point transfers the data to a root complex of a second platform among the platforms, the data to be transferred being received at the second end point by tunneling from the first end point.

Abstract: The disclosed system may include a central processing unit (CPU) interface board including a first standard port and a second standard port, a first peripheral board including a first augmented interface, the first augmented interface including first standard interface control signals and first additional interface control signals based on a first standard communication protocol, and a second peripheral board including a second augmented interface, the second augmented interface including second standard interface control signals and second additional interface control signals, the first standard interface control signals being connected to the first standard port, the second standard interface control signals being connected to the second standard port, and at least one of the first additional interface control signals being connected to a respective at least one of the second additional interface control signals. Various other methods, systems, and apparatus are also disclosed.

Abstract: A bus control circuit configured to transfer access commands for performing exclusive access between a first bus specification and a second bus specification by converting from a first exclusive access command applying to the first bus specification which deals with exclusive access, into a second exclusive access command of the second bus specification which doesn't deal with the exclusive access.

Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

Abstract: The disclosure provides a power supply circuit including an external power source, an ID pin provided in a universal serial bus (USB) port on a printed circuit board (PCB), and an internal power and signal management subsystem. The external power source is configured to power the internal power and signal management subsystem via the ID pin. A power supply method and a portable device are also disclosed.

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.

Abstract: Devices, systems, and methods for selectively pairing an upstream facing USB port device (UFP device) and a downstream facing USB port device (DFP device) over a network are disclosed. A controller device sends pairing commands to a selected UFP device and a selected DFP device, which then establish a connection with each other over a network. The controller device may subsequently cause the UFP device and/or the DFP device to remove the existing pairing and to instead pair with a different UFP device or DFP device. A pairing between a UFP device and a DFP device allows a host device coupled to the UFP device and a USB device coupled to the DFP device to communicate via a USB-compatible protocol.

Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

Abstract: Embodiments are generally directed to dual role capable connectors for a separable portion of a computing apparatus. An embodiment of an apparatus includes a separable physical connection to a second apparatus; a first electronic connector, the first electronic connector providing data connections for the physical connection; a plurality of additional electronic connectors, the plurality of additional connectors being supported by the first electronic connector; and a control logic to control operation of the plurality of additional electronic connectors, wherein operation of the plurality of additional electronic connectors includes each additional electronic connector being capable to operate in both a host role and a device role for the interconnection of computing systems, wherein the host role and device role may be for a first connector mode or a second connector mode, and an alternative connector mode.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a disaggregated computing architecture is presented. The method includes, receiving user commands to establish compute units among a plurality of physical computing components, each of the compute units comprising one or more of the plurality of physical computing components selected from among central processing units (CPUs), graphics processing units (GPUs), storage modules, and network interface modules. The method also includes forming the compute units based at least on logical partitioning within a Peripheral Component Interconnect Express (PCIe) fabric communicatively coupling the plurality of physical computing components, wherein each of the compute units have visibility over the PCIe fabric to the one or more of the plurality of physical computing components assigned to the associated compute units using the logical partitioning within the PCIe fabric.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.

Abstract: Examples implementations described herein involve systems and methods wherein the storage software is configured to consider the capabilities of the underlying hardware to determine the caching data method at run time. Some examples of capabilities that are considered in the example implementations include whether non-volatile memory (NVM) is available and how much NVM is available. Some examples of caching methods used include using both dynamic random access memory (DRAM) and NVM to cache write data and using only NVM to cache write data.

Abstract: A peripheral component interconnect express (PCIe) physical function is coupled to a controller. The controller is configured to allocate a first portion of resources for use by the PCIe physical function. A PCIe virtual function is coupled to the controller. The is configured to allocate a second portion of resources for use by the PCIe virtual function based, at least in part, on a total number of PCIe physical functions and a total number of PCIe virtual functions associated with the apparatus.

Abstract: An entertainment device initiates a configuration process of a controlling device in response to a change in an audio visual entertainment system configuration in which at least one of a plurality devices is connected to the entertainment device as an audio and/or visual source and at least one of the plurality of devices is connected to the entertainment device as an audio and/or visual output destination for the entertainment device.

Abstract: A system provides remote computing services using physical or virtualized computing resource instances on various host machines. An enhanced PCIe endpoint card connected to a given host machine may include a local processor (e.g., on an SOC device) that emulates PCIe compliant hardware (e.g., a USB controller) in software. A client receiving computing services from the system may redirect USB traffic from a locally-attached physical USB device (e.g., an input/output, storage, or security device) over the Internet to the enhanced PCIe endpoint card. The enhanced PCIe endpoint card may present an emulated USB controller to an application executing on the host (on the client's behalf) as a device that is locally attached at the given host machine, and the application may access the functionality of the physical USB device by exchanging commands or data with the emulated USB controller through a PCIe controller on the enhanced PCIe endpoint card.

Abstract: According to one embodiment, a system includes first and second devices. The first device detects whether a cable is connected to the first device in a first state or a second state. The first device receives, from the second device, status information indicative of whether the cable is connected to the second device in the first state or the second state. The first device switches allocation of signal lines to contact pins of a connector of the first device to which the cable is connected, based on connection states of the first and second devices. The second device detects whether the cable is connected to the second device in the first state or the second state. The second device transmits, to the first device, a result of detection as the status information.

Abstract: The disclosure is related to an interface card module which is configured to be inserted into a PCIe slot on a motherboard and to be inserted with a cable electrically connected to a function chip. The interface card module includes an adapter card and a function card. The adapter card includes a mainboard, a first PCIe male connector, a socket and at least one cable connector. The first PCIe male connector, the socket and the cable connector are respectively disposed on different sides of the mainboard. The first PCIe male connector is configured to be inserted into the PCIe slot on the motherboard. The at least one cable connector is inserted with the cable. The function card has a second PCIe male connector configured to be inserted into the socket of the adapter card. In addition, the disclosure is also related to an adapter card.

Abstract: A system that includes (i) a device having connectors connected to pluggable modules external to the device and (ii) the pluggable modules exchanging signals with the device via the connectors. In particular, the pluggable modules includes a first pluggable module and a second pluggable module that further exchange a supplemental signal with each other and bypassing the connectors.

Abstract: According to an embodiment, a system, a method, and/or a computer program product is provided to allow a choice of allocating resources of a processor host bridge (PHB) at initial setup of a computer system to a group of peripheral component interconnect express (PCI-E) slots via a PCI-E switch, or alternatively to allocate resources of the PHB directly to a single PCI-E slot. The system may include a PHB, a first switch connected to the PHB, where the first switch is a simple circuit, a second switch connected to the first switch, where the second switch is a simple circuit, a PCI-E switch connected to the first switch and connected to the second switch, and a first PCI-E slot connected to the second switch.

Abstract: A bridge device including a first connector, a first transceiver, a second connector, a second transceiver, a voltage processor, and a controller is provided. The first connector is configured to couple to a host and includes a first pin. The first transceiver is coupled between the first pin and a node and includes a first current limiter. The second connector is configured to couple to a peripheral device and includes a second pin. The second transceiver is coupled between the node and the second pin and includes a second current limiter. The voltage processor processes the voltage of the node to generate an operation voltage. The controller receives the operation voltage to determine whether to turn on at least one of the first and second transceivers.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A system and method for dynamic reconfiguration of at least one peripheral bus switch of a system includes a management controller that detects whether a server system is connected to each peripheral bus slot of the system. The management controller selects a peripheral bus switch topology for the at least one peripheral bus switch, based on the detecting. The management controller sets each port of the at least one peripheral bus switch to either an upstream port configuration or a downstream port configuration, based on the peripheral bus switch topology.

Abstract: Methods, systems, or apparatus may be directed to hosting, by a virtual machine manager of a local machine, a virtual machine having a device driver. A virtual machine manager may obtain, from a stub driver on a remote machine, information about the I/O device on the remote machine. The I/O device may be bound to a stub driver on the remote machine. The virtual machine manager may instantiate a virtual I/O device on the local machine corresponding to the I/O device on the remote machine. The virtual machine manager may then collaborate with the stub driver on the remote machine to effectuate a real access to the I/O device on the remote machine for an access to the virtual I/O device by the device driver on behalf of a program on the local machine.

Abstract: A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster and configures the computer cluster to provide resources for the applications in accordance with the allocation. The cluster may include a Peripheral Component Interconnect express (PCIe) fabric. The cluster manager may configure PCIe multi-root input/output (I/O) virtualization topologies of the computer cluster. The allocations may satisfy Quality of Service requirements, including priority class and maximum latency requirements. The allocations may involve splitting I/O traffic.

Abstract: A method of reading out access authorizations or ID's from at least one customer medium by at least one reader (3, 4, 5) of an access control device (2) and evaluating the selected ID's or access authorizations. All readers are activated and perform a scan for ID's or access authorizations, which can be contained or stored in at least one customer medium. The selected ID's or access authorizations are transmitted to a controller which temporarily stores and transmits them to an evaluation unit (1) while the readers continue to scan for possible ID's or access authorizations. If an evaluation in the evaluation unit finds that a selected access authorization is valid or allocated to a selected ID, the readers are deactivated, and access is granted. If, after a prescribed time, no further ID's or access authorizations are read out, transmitted and recognized as valid, then access is denied.

Abstract: Provided is a programmable controller capable of simplifying handshake processing between control devices. The programmable controller, which performs the handshake processing in conjunction with a reception-side device, is provided with an output signal area in which a signal to be output to the reception-side device is held, an input signal area in which a signal output by the reception-side device is held, a sequential program execution part configured to execute a sequential program, an output signal temporary area in which an output signal from the sequential program is held, and a handshake processing part configured to copy a signal state of the output signal temporary area in the output signal area and hold the signal state of the output signal area so that the input signal area is notified of a completion signal.

Abstract: Circuits, methods, and apparatus that may improve networking techniques for transferring data among various electronic devices. One example may provide sharing data among various devices by daisy-chaining devices together. That is, several devices may be connected to each other through a series of cables to form a chain of devices. In this physical configuration, data may be shared among multiple devices using a series of single-hop virtual tunnels. Alternatively, a number of tunnels may be formed by a host device, each having a target device in the daisy chain. Each tunnel may originate at the host device and terminate at their target device. Each tunnel may bypass devices between the host device and the tunnel's target device. These two techniques may also be combined. Another example may provide a method of simplifying the routing of high-speed data signals through a network topology.

Abstract: Present disclosure relates to a method for managing a docking device and the docking device thereof. The docking device is configured with a processor and at least two coupling ports. The method comprises following steps: electrically coupling a computer and/or at least one peripheral device to the at least two coupling ports respectively; retrieving a plurality of characteristic profiles by the processor, wherein each of the characteristic profiles is retrieved from each of the at least two coupling ports; receiving, by the processor, an input signal from the computer or the at least one peripheral device; and changing the characteristic profiles based on the input signal by the processor.

Abstract: A hybrid approach using hardware and software is used for report management in peripheral component interconnect (PCI) express devices. The device hardware detects an error associated with a transaction with a host computer. The device software identifies a function associated with the error and determines various attributes of the error. The device software then exposes the attributes of the error in the PCI express and the advanced error reporting (AER) capabilities. The error can be reported in a message transaction to the host computer.

Abstract: According to the computer device and the configuration and management method of a computer device that are provided in the embodiments of the present invention, an SMM and a CPU are controlled to connect to a PCIE Switch at different stages of system startup, so that management of a PCIE device does not rely on involvement of the CPU of the computer device. In this way, the PCIE device can be configured and managed without involvement of an operating system of the computer device, and CPU resources are saved. Manageability of the computer device is improved, meeting a requirement of a large data center for simplifying computing device management. In addition, the PCIE device is connected to the PCIE Switch by using a downstream port, with no need to configure a special interface to connect to the SMM, thereby simplifying system configuration.

Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.

Abstract: When client-side USB redirection techniques redirect an interface as a simple device, multiple redirected interfaces can be combined on the server side into a single composite device. When redirecting an interface, the client-side proxy can include an interface hint identifying the interface number in the device arrival notification sent to the server-side agent. Upon receiving multiple device arrival notifications that each include an interface hint, the agent can recombine the appropriate information to generate composite device information which will represent a composite device that includes each interface. The agent can then provide this composite device information to the virtual bus driver to initiate the process of loading the appropriate drivers for the composite device. Accordingly, even though each redirected interface of the composite device is reported to the server-side agent individually, the operating system on the server will still see a composite device.

Abstract: A determination is made that data stored in an extent of a first storage resource is to be moved to an extent of a second storage resource. Operations that are still awaiting to start execution in the first storage resource after the data stored in the extent of the first storage resource has been moved to the extent of the second storage resource, are configured for execution in the second storage resource.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A system and method are disclosed for providing electrically isolated communications between two USB2 devices. Two isolating eUSB2 repeaters are utilized to implement a digital isolation barrier between the two USB2 devices. The isolating eUSB2 repeaters are configured to broker isolated communications between the two USB2 devices using a modified eUSB2 protocol that allows the two isolating eUSB2 repeaters to interoperate across the isolating barrier. The modified eUSB2 protocol allows the two isolating eUSB2 repeaters to broker isolating communications on behalf of the USB2 devices without the use of an accurate clock signal. The modified eUSB2 protocol utilized by the isolating eUSB2 repeaters is configured in particular to support certain end-of-packet translations between USB2 data and the modified eUSB2 protocol, management of certain USB2 bus state transitions and assignment of roles to the two isolating eUSB2 repeaters.

Abstract: Methods, apparatuses, and computer program products for managing a storage device using a hybrid controller are provided where the storage device comprises an internal peripheral component interconnect express (PCIe) interface to control solid state memory within the storage device. In particular embodiments, the storage device includes a first external interface configured to establish an external PCIe link and a second external interface configured to establish at least one of an external serial attached small computer system interface (SAS) link and an external serial advanced technology attachment (SATA) link. Embodiments include receiving from an external source, by the hybrid controller, a first command at the first external interface and a second command at the second external interface; and concurrently implementing, by the hybrid controller, the first command using a PCIe protocol and the second command using one of a SAS protocol and a SATA protocol.

Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM), and an interface circuit for interfacing the system to an external posted transaction bus. Each processor has the same address map. Each fetches instructions from SLMEM, and accesses data from/to SLMEM. A processor can initiate a read transaction on the posted transaction bus by doing an AHB-S bus write to a particular address. The AHB-S write determines the type of transaction initiated and also specifies an address in a shared memory in the interface circuit. The interface circuit uses information from the AHB-S write to generate a command of the correct format. The interface circuit outputs the command onto the posted transaction bus, and then receives read data back from the posted transaction bus, and then puts the read data into the shared memory at the address specified by the processor in the original AHB-S bus write.