Abstract: Methods, systems, and computer storage media for providing a Shell PCIe Bridge (SPB) and shared-link-interface services that support a shared common PCIe physical link between SPB clients in a PCIe system. In operation, shared-link-interface operations include accessing, at a Shell PCIe Bridge (SPB), an outbound transaction for a PCIe endpoint vendor IP or an inbound transaction for an SPB client. The SPB supports a shared common PCIe physical link based on a shared-link-interface comprising vendor-agnostic downstream custom interface and a vendor-specific upstream PCIe endpoint interface. The shared-link-interface operations further include processing the outbound transaction or the inbound transaction based on shared-link-interface services. In this way, processing transaction comprises executing shared-link-interface operations that provide protection enhancements associated with sharing a physical PCIe link.

Abstract: A firmware enumerates the buses of root bridges in the computing system. If an OOR condition occurs during enumeration of the buses, the firmware determines the number of required buses for each root bridge causing an OOR condition. The number of required buses for bridge devices connected to each root bridge causing an OOR condition can be identified using the same set of bus numbers. Once the firmware has determined the number of buses required by each root bridge, including those not causing an OOR condition, the firmware reallocates the number of available buses between the root bridges such that each root bridge is allocated a number of the available buses greater than or equal to the number of required buses. The firmware stores data identifying the allocation and restarts the computing device. Upon rebooting, the computing system utilizes the new allocation of bus numbers to eliminate the OOR condition.

Abstract: Hardware transactions or other techniques, such as custom PCIe handling devices, are used to atomically move pages from one host's memory to another host's memory. The hosts are connected by one or two non-transparent bridges (NTBs), which make each host's memory and devices available to the other, while allowing each host to reboot independently.

Abstract: A management method for managing a memory storage device compatible with a PCIe (PCI Express) standard is disclosed. The memory storage device has a plurality of pins configured to couple to a host system. The management method includes: transmitting a first command to the memory storage device through at least one first pin among the pins to control the memory storage device to enter a target link status; and when the memory storage device is in the target link status, transmitting a second command to the memory storage device through a second pin among the pins to control the memory storage device to leave the target link status. The second pin is not a pin dedicated to control the memory storage device to enter or leave the target link status.

Abstract: A USB device and a firmware updating method for the USB device are provided. The firmware updating method includes the following steps. Firstly, a communication protocol is provided. Then, the communication protocol is installed in the at least one microcontroller unit of the USB device. Then, an application program is produced according to the communication protocol. The application program is installed in an electronic computer. The application program contains at least one update firmware information. Then, the at least one update firmware information is transmitted from the electronic computer to the at least one microcontroller unit through the communication protocol. Consequently, at least one original firmware information in the at least one microcontroller unit is replaced by the at least one update firmware information.

Abstract: An audio-visual transmission device connected with a camera and a receiver is provided and includes a wireless module, a processor and a universal serial bus (USB) port. The wireless module is used for wireless connection with the camera to receive an audio-visual data transmitted from the camera. The processor transmits a connection request signal to the camera through the wireless module. The universal serial bus (USB) port is used for transmitting the audio-visual data. The camera transmits a connection acknowledgment signal and the audio-visual data back to the processor via the wireless module according to the connection request signal, and the receiver is connected to the audio-visual transmission device through the USB port to receive the audio-visual data.

Abstract: An electronic device including a PDIC, a charging IC, and a processor. The PDIC determines whether an external device is connected to the USB port, through a first pin of a USB port. The charging IC outputs a first voltage, which is a voltage obtained by boosting a voltage provided by a battery, to the external device through a second pin, when the external device is connected to the USB port. The processor is configured to determine whether the external device connected to the USB port is a first external device having a specified VID and a specified PID, through a third pin of the USB port, and to transmit a first signal, which controls the charging IC to output a second voltage having a magnitude less than the first voltage, to the charging IC when the first external device is connected to the USB port.

Abstract: A system includes a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on a status of a signal at the second interface based on instructions received from the host device.

Abstract: Apparatuses, methods, and computer-readable media are provided for operating a port manager to detect a first link condition or a second link condition of a circuitry. Under the first link condition, a first link between a downstream port of the circuitry and an upstream port of a switch is compatible to a first protocol, and a second link between a downstream port of the switch and an upstream port of a device is compatible to the second protocol. Under the second link condition, the first link exists and is compatible to the first protocol, while there is no second link being compatible to the second protocol. The port manager is to operate the downstream port of the circuitry according to the second protocol on detection of the first link condition, or according to the first protocol on detection of the second link condition. Other embodiments may be described and/or claimed.

Abstract: A front adapter for connecting to a control device, has a connection device connected to a predetermined system cable for connecting at least one field component, at least one wireless communication interface for wirelessly transmitting and receiving signals to or from at least one wireless one transmitting and/or receiving device which can be connected to a first field unit, and/or at least one bus-capable communication interface for transmitting and receiving signals via a signal bus to or from at least one bus-capable transmitting and/or receiving device which can be connected to a second field device, and a control and/or evaluation device which is adapted to control the transmitting of signals between the control device and the at least one wireless transmitting and/or receiving device and/or the at least one bus-capable transmitting and/or receiving device.

Abstract: The present disclosure provides an information handling system (IHS) and related methods that provide secure shared memory access (SMA) to shared memory locations within a Peripheral Component Interconnect (PCI) device of an IHS. The IHS and methods disclosed herein provide secure SMA to one or more operating system (OS) applications that are granted access to the shared memory. According to one embodiment, the disclosed method provides secure SMA to one or more OS applications by receiving a secure runtime request from at least one OS application to access shared memory locations within a PCI device, authenticating the secure runtime request received from the OS application, creating a secure session for communicating with the OS application, and providing the OS application secure runtime access to the shared memory locations within the PCI device.

Abstract: A hypervisor managing a virtual machine (VM) running on a host computer system, modifies a virtual machine control structure (VMCS) associated with the VM to trigger a VM exit upon detecting a transition of the VM to a specified power state. Upon detection of the VM exit, a timer is initialized to trigger another VM exit, and execution of the VM in the specified power state is resumed.

Abstract: An image processing apparatus, which complies with a particular setting protocol including a procedure to receive setting information for a first communication system from an OS of an information processing device, includes a first communication interface for a first communication system, a second communication interface for a second communication system, and a controller configured to transmit, to the information processing device via the second communication interface, compliance information representing that the image processing apparatus complies with the particular setting protocol, after sharing mutual compliance recognition with the information processing device through transmitting the compliance information, receive the setting information from the OS via the second communication interface in accordance with the particular setting protocol, the mutual compliance recognition being recognition that the image processing apparatus and the OS comply with the particular setting protocol, and configure sett

Abstract: Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.

Abstract: A convertible I/O signal processor is convertible between different operating configurations for connecting multiple field devices to the I/O signal processor by selectable types of electrical connectors such as cables, terminal blocks, and the like. The I/O signal processor includes a signal processing module connected to a signal processor and an interface module removably connected to the signal processing module. The interface module includes electrical connectors for receiving/transmitting I/O signals from and to field devices. The interface module and the signal processing module define I/O channels extending between the electrical connectors and the signal processor. The interface module in embodiments includes I/O module connectors that enable removable I/O modules to be interposed in the I/O channels.

Abstract: A reliable and scalable data repository service can be supporting cooperative transactions. In an example, multiple data producers may use the data repository service to upload data in one or more transactions. Data contained in one transaction may be treated as an atomic unit. In an embodiment, the data repository service manages multiple candidate transactions associated with an election transaction such that at most one candidate transaction may begin and/or commit a given time. During a commit of a candidate transaction, the data uploaded during the candidate transaction may become associated with the election transaction. The data repository service may maintain metadata associated with each of the candidate transactions. In response to a request for data associated with the election transaction, the metadata may be used, in conjunction with a user-specified isolation level, to locate the data uploaded some of the candidate transactions for the election transaction.

Abstract: A switching system includes a first switching device and a second switching device. The first switching device and the second switching device are coupled using a network. The first switching device includes a plurality of PCIe upstream ports configured to connect to at least one host, the second switching device comprises at least one PCIe downstream port configured to connect to at least one input/output (I/O) device, and the second switching device is configured to receive a first data packet from the first switching device using the network, convert the first data packet to a second data packet complying with a PCIe protocol, and transmit the second data packet to a target I/O device of the second data packet.

Abstract: An electronic device according to an embodiment of the present invention comprises: a universal serial bus (USB) interface; a processor electrically connected to the USB interface; and a memory electrically connected to the processor, wherein the memory may store instructions configured to, when executed, cause the processor to: enter a security mode; in the security mode, receive, from an external device connected to the electronic device via the USB interface, a USB class code corresponding to the external device; determine whether the USB class code is included in a white list of connectable devices allowed to be connected to the electronic device in the security mode; and control a communication connection between the external device and the electronic device according to whether the USB class code is included in the white list. Other embodiments are also possible.

Abstract: A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.

Abstract: The disclosed computer-implemented method for controlling access to a peripheral device may include receiving an input/output request related to a process attempting to access the peripheral device. The method can also include determining an access state for the process indicative of whether the process will be allowed to gain access to the peripheral device. The access state can be based on a context property of the process. The method can further include responding to the input/output request with initiation of a virtual peripheral output from a virtual peripheral device if the access state is indicative of the process not being allowed access to the peripheral device. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A virtualization system includes at least one storage device, a plurality of computing nodes, each computing node coupled to at least one of the storage devices, each computing node comprising a physical function (PF) agent, and a plurality of virtual machines, where the PF agent of a first computing node of the computing nodes is configured to receive from a virtual machine of the virtual machines a request for retrieving or writing data and to obtain placement information indicating a second computing node of the computing nodes for retrieving or writing data, and the PF Agent of the first computing node is configured to communicate with the PF Agent of the second computing node to retrieve data from the second computing node or write data to the second computing node based on the placement information.

Abstract: An electronic device includes a connector that includes a first terminal for receiving power from a power supply apparatus, a second terminal, a third terminal, and a fourth terminal; a control unit that controls power received from the power supply apparatus via the first terminal; and a determination unit that determines a power supply capability of the power supply apparatus by using the second terminal or the third terminal and the fourth terminal, wherein the determination unit determines the power supply capability of the power supply apparatus by using the third terminal and the fourth terminal before a predetermined transition occurs in the second terminal.

Abstract: An electronic device includes a connector that includes a first terminal for receiving power from a power supply apparatus, a second terminal, a third terminal, and a fourth terminal; a receiving power control unit that controls power received from the power supply apparatus via the first terminal; a determination unit that determines a power supply capability of the power supply apparatus by using the second terminal or the third terminal and the fourth terminal; and a control unit that restricts, before the power supply capability of the power supply apparatus is determined by using the third terminal and the fourth terminal, power to be received from the power supply apparatus via the first terminal when a predetermined transition occurs in the second terminal.

Abstract: Technologies for network interface controllers (NICs) include a computing device having a NIC coupled to a root FPGA via an I/O link. The root FPGA is further coupled to multiple worker FPGAs by a serial link with each worker FPGA. The NIC may receive a remote direct memory access (RDMA) message from a remote host and send the RDMA message to the root FPGA via the I/O link. The root FPGA determines a target FPGA based on a memory address of the RDMA message. Each FPGA is associated with a part of a unified address space. If the target FPGA is a worker FPGA, the root FPGA sends the RDMA message to the worker FPGA via the corresponding serial link, and the worker FPGA processes the RDMA message. If the root FPGA is the target, the root FPGA may process the RDMA message. Other embodiments are described and claimed.

Abstract: An energy-saving hub is connected to an electronic device, an AC power source and a mobile device. The energy-saving hug includes a power supply interface, a power module, an upstream connector, a downstream connector, a main control circuit, and a system circuit. The power supply interface is used to connect to the AC power source, the power module is connected to the power supply interface, the upstream connector and the downstream are connected to the power module, and the main control circuit is connected to the power module and the upstream connector. The system circuit is connected to the upstream connector, the downstream connector and the main control circuit, wherein the system circuit is maintained in a sleep mode. When the energy-saving hub connects to the electronic device or the mobile device, the main control circuit transmits a wake-up signal to the system circuit to wake up the system circuit.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.

Abstract: An electronic system includes a serial system bus interface having a root complex and an end point, a command bus and a data bus coupled to the serial system bus interface, a memory device coupled to the data bus, and a direct memory access (DMA) controller coupled to both the command bus and the data bus to directly access the memory device in response to request commands which are transmitted from the root complex to the end point. The DMA controller includes a command queue in which the request commands stand by.

Abstract: A system that allows access to a virtualized device is disclosed. The system may include a device, a processor, and a communication unit coupled to the device via a communication link. The device may include hardware resources configured to be shared by multiple threads executing on the processor. The communication unit may be configured to detect a request to access the device by the processor. In response to the detection of the request, the communication unit may send one or more instructions to the device via the communication link using a communication protocol.

Abstract: An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.

Abstract: A method of handling message signaled interrupts in a computer system that uses an internal bus for communication between peripheral devices, using shared peripheral interrupt (SPI) vectors. The method includes determining whether a message signaled interrupt (MSI) needs to be allocated for a PCI-e device for an interrupt to be sent to a host. If it is determined that MSI needs to be allocated for the PCI-e device, a determination is made as to whether a Locality Specific Interrupt (LPI) register or an Interrupt Translation Service (ITS) is available to process the interrupt. If it is determined that neither the LPI register nor the Interrupt Translation Service (ITS) is available to process the interrupt, the PCI-e device is configured for SPI-based MSI generation to route the interrupt by determining an available SPI vector and assigning the available SPI vector to the PCI-e device.

Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.

Abstract: A method for managing embedded software modules for an electronic computer embedded in an electrical switching device for switching an electric current includes acquiring a software module including a runnable code and a service contract declaring the hardware resources required by the runnable code when it is run by the computer; installing the software module inside a host receptacle intended to form an environment for running a software module and including a memory location defined statically inside a memory of the computer and being associated with a subset of hardware resources of the computer; running the software module including a step consisting in verifying whether the operation of running of the software module respects the service contract, the running operation being allowed to continue if the service contract is respected and, otherwise, a recovery step is implemented in order to interrupt the running operation.

Abstract: A first end point and a second end point are provided. The first end point receives data from a root complex of a first platform among platforms, each serving as a computer that executes arithmetic processing. The second end point transfers the data to a root complex of a second platform among the platforms, the data to be transferred being received at the second end point by tunneling from the first end point.

Abstract: The disclosed system may include a central processing unit (CPU) interface board including a first standard port and a second standard port, a first peripheral board including a first augmented interface, the first augmented interface including first standard interface control signals and first additional interface control signals based on a first standard communication protocol, and a second peripheral board including a second augmented interface, the second augmented interface including second standard interface control signals and second additional interface control signals, the first standard interface control signals being connected to the first standard port, the second standard interface control signals being connected to the second standard port, and at least one of the first additional interface control signals being connected to a respective at least one of the second additional interface control signals. Various other methods, systems, and apparatus are also disclosed.

Abstract: A bus control circuit configured to transfer access commands for performing exclusive access between a first bus specification and a second bus specification by converting from a first exclusive access command applying to the first bus specification which deals with exclusive access, into a second exclusive access command of the second bus specification which doesn't deal with the exclusive access.

Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

Abstract: The disclosure provides a power supply circuit including an external power source, an ID pin provided in a universal serial bus (USB) port on a printed circuit board (PCB), and an internal power and signal management subsystem. The external power source is configured to power the internal power and signal management subsystem via the ID pin. A power supply method and a portable device are also disclosed.

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Abstract: Devices, systems, and methods for selectively pairing an upstream facing USB port device (UFP device) and a downstream facing USB port device (DFP device) over a network are disclosed. A controller device sends pairing commands to a selected UFP device and a selected DFP device, which then establish a connection with each other over a network. The controller device may subsequently cause the UFP device and/or the DFP device to remove the existing pairing and to instead pair with a different UFP device or DFP device. A pairing between a UFP device and a DFP device allows a host device coupled to the UFP device and a USB device coupled to the DFP device to communicate via a USB-compatible protocol.

Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.

Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

Abstract: Embodiments are generally directed to dual role capable connectors for a separable portion of a computing apparatus. An embodiment of an apparatus includes a separable physical connection to a second apparatus; a first electronic connector, the first electronic connector providing data connections for the physical connection; a plurality of additional electronic connectors, the plurality of additional connectors being supported by the first electronic connector; and a control logic to control operation of the plurality of additional electronic connectors, wherein operation of the plurality of additional electronic connectors includes each additional electronic connector being capable to operate in both a host role and a device role for the interconnection of computing systems, wherein the host role and device role may be for a first connector mode or a second connector mode, and an alternative connector mode.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a disaggregated computing architecture is presented. The method includes, receiving user commands to establish compute units among a plurality of physical computing components, each of the compute units comprising one or more of the plurality of physical computing components selected from among central processing units (CPUs), graphics processing units (GPUs), storage modules, and network interface modules. The method also includes forming the compute units based at least on logical partitioning within a Peripheral Component Interconnect Express (PCIe) fabric communicatively coupling the plurality of physical computing components, wherein each of the compute units have visibility over the PCIe fabric to the one or more of the plurality of physical computing components assigned to the associated compute units using the logical partitioning within the PCIe fabric.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.

Abstract: Examples implementations described herein involve systems and methods wherein the storage software is configured to consider the capabilities of the underlying hardware to determine the caching data method at run time. Some examples of capabilities that are considered in the example implementations include whether non-volatile memory (NVM) is available and how much NVM is available. Some examples of caching methods used include using both dynamic random access memory (DRAM) and NVM to cache write data and using only NVM to cache write data.

Abstract: A peripheral component interconnect express (PCIe) physical function is coupled to a controller. The controller is configured to allocate a first portion of resources for use by the PCIe physical function. A PCIe virtual function is coupled to the controller. The is configured to allocate a second portion of resources for use by the PCIe virtual function based, at least in part, on a total number of PCIe physical functions and a total number of PCIe virtual functions associated with the apparatus.

Abstract: According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.