Abstract: A system and method are directed towards a pseudo multi-master operation on a serial bus. The pseudo multi-master operation allows multiple devices without standard multi-master functionality to operate on the serial bus as masters. In a disclosed example, the serial bus is an Inter-Integrated Circuit (I2C) bus, which is isolated when an adapter card requires access to the I2C bus, such as to update vital product data (VPD) to a memory device, and to cache the updated VPD to a chassis management module.

Abstract: A method of providing high density expansion of a USB network, the method comprising: attaching a plurality of USB hubs to adjacent slots in a PXI instrumentation chassis; configuring one of the USB hubs as a primary USB Hub; connecting an upstream port of the primary USB Hub to a USB network; configuring a first downstream port of the primary USB Hub to communicate across a first PXI Local Bus to a first adjacent USB Hub of the USB Hubs other than the primary USB Hub, the first adjacent USB Hub being adjacent to the primary USB Hub; configuring a plurality of other downstream ports of the primary USB Hub to provide expansion of the primary USB Hub; connecting an upstream port of the first adjacent USB Hub to the first PXI Local Bus, wherein the first PXI Local Bus is in the direction of the primary USB Hub; configuring a first downstream port of the first adjacent USB Hub to communicate across a second PXI Local Bus to a second adjacent USB Hub of the USB Hubs other than the primary USB Hub, the second adjac

Abstract: A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.

Abstract: A solution for setup and optimization of a data transfer path in extended computer systems, where the I/O system is virtualized. The solution achieves advantageous results via a mechanism that automates the configuration of multiple data path components. The solution achieves initial optimization and then automates continual optimization of the data path through monitoring of changes and through dynamic adjustment of system resources and data transfer characteristics.

Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Abstract: Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity.

Abstract: Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

Abstract: An avionics data storage device and data transfer system are provided. The data storage device, has a slanted, “shark-like” door, which provides an environmental seal when not installed in the data transfer system. The storage device and data transfer system maintain environmental seals at all times other than installation. The storage device and transfer system can implement a variety of identification and authentication methods, including electrical, physical, and optical authentication or identification.

Abstract: A system for implementing non-standard I/O adapters in a standardized I/O architecture, the system comprising an I/O hub communicatively coupled to an I/O bus and at least one I/O adapter, the I/O hub including logic for implementing a method, the method comprising receiving a request to perform an operation on the I/O adapter from a requester at a requester address, the I/O adapter at a destination address, determining that the request is in a format other than a format supported by the I/O bus, the I/O bus expecting a requester identifier at a first location in a header of the request, reformatting the request into the format supported by the I/O bus, the reformatting comprising storing the requester address, the destination address and an operation code at the first location in the header of the reformatted request, and sending the reformatted request to the I/O adapter.

Abstract: A processing node of a server rack includes a processor to generate processing node management requests and to process responses to the node management requests, and a communication module to receive the processing node management requests, to transmit over a communication link to a management controller of the server rack external to the processing node a processing node management request, to receive over the communication link from the management controller processing node management information, and to transmit the processing node management information to the processor.

Abstract: In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system.

Abstract: A host device is managed that communicates with a peripheral device via an interface on the basis of a high frequency clock; the host device is in a suspended state in which the high frequency clock is deactivated. At the host device, an activation state of the peripheral device is detected (21) on the interface. Then the duration of a period of time (T1) since the detection of the activation state is counted, on the basis of a low frequency clock. Then this activation state is maintained on the interface (23) by means of hardware before the period of time expires.

Abstract: Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router. Embodiments of the invention allow for devices to be “merged” into a single device for the host OS. For example, a peripheral devices coupled to the host system via a PCIe link may be “merged” with a peripheral devices coupled to the host system via another PCIe link or a SATA link.

Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

Abstract: In a method for adjusting bus bandwidth applied on a computing device, the computing device includes a bus controller and several graphics processing units (GPUs). The bus controller establishes a data flow of each signal channel of the peripheral component interconnect express (PCI-E) bus connected to each GPU, and obtains a total data flow of the PCI-E bus connected to each GPU according to the data flow of each of the signal channels. If there is a fully-utilized GPU according to the total data flow of the PCI-E bus; the method locates an available idle signal channel of the PCI-E bus according to the data flow of each of signal channels, and reroutes the data flow of the fully-utilized GPU to the idle signal channel using a switch of the bus controller.

Abstract: A collaboration request may be sent to a host or a peripheral when a job is to be processed. The job may include one or more tasks. The host determines which device is better suited to act as host by analyzing the type of task or job to be executed and the capabilities of the host and peripheral. If the peripheral is better suited to act as host, the host and peripheral swap roles and control of a task or job is transferred to the peripheral. The host and peripheral may return to their default roles once the task or job is complete.

Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.

Abstract: A Flexray gateway comprising a first and a second bus interface for connecting a first and a second Flexray bus, wherein the Flexray gateway comprises coupling means for coupling a first and a second Flexray bus and for transmitting bus messages between the first and the second Flexray bus, wherein the Flexray gateway comprises a Flexray controller with a first and a second channel interface for transmitting and receiving bus messages of a first and a second channel type of a Flexray bus.

Abstract: The disclosure describes a novel method and apparatus for allowing a controller to access a bus router using a communication occurring in response to one edge of a clock to select one or more devices for access using a communication occurring on the opposite edge of the clock. Additional embodiments are also provided and described in the disclosure.

Abstract: The present invention provides a information transmission device including: a transmission section that transmits information to a first transmission path that transmit information serially; a reception section that receives information from a second transmission path; a waveform shaping section that, according to setting information, shapes at least one of a signal waveform of the information for transmission, and/or a signal waveform of the information for reception; and a controller that, when establishing communication, controls the transmission section to transmit predetermined first information that requests communication establishment, and effects control to change the first setting information and controls the transmission section to re-transmit the first setting information when the reception section has not received the first information within an interval that from the beginning of transmission of the first information until a predetermined duration required for communication establishment has elap

Abstract: Embodiments of the present invention provide a hybrid RAID controller with multi PCI bus switching for a storage device of a PCI-Express (PCI-e) type that supports a low-speed data processing speed for a host. Specifically, embodiments of this invention provide a hybrid RAID controller having multiple (e.g., two or more) sets of RAID circuitry that are interconnected/coupled to on another via a PCI bus to enable real-time switching. Each set of RAID circuitry is coupled to a one or more (i.e., a set of) semiconductor storage device (SSD) memory disk units and/or HDD/Flash memory units.

Abstract: A HUB control chip implemented in a specific package is provided. The HUB control chip includes a plurality of transmission modules and a plurality of pins. The plurality of the pins include: a plurality of data pin groups coupled to one of the plurality of transmission modules respectively. Each of the plurality of data pin groups includes: a first sub-group, receiving and transmitting a first pair of differential signals conforming to the USB 2.0 standard; a second sub-group, receiving a second pair of differential signals conforming to the USB 3.0 standard; and a third sub-group, transmitting a third pair of differential signals conforming to the USB 3.0 standard. The number of the plurality of the pins is less than or equal to 52.

Abstract: A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

Abstract: A switching circuit connected to an I/O device having a plurality of functions, the switching circuit comprising: a processing unit that includes tables, each of which corresponds to one of the function of the I/O device, when the processing unit receives a packet that instructs to add a function to the I/O device, configured to select the table that contains a bus number of a destination of the received packet, and configured to notify a number of the selected table; and a filter configured to change a function number of the destination of the received packet to the number of the table notified from the processing unit.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A computer includes an enclosure, an internal mass storage device within the enclosure, and a redundancy controller within the enclosure. At least one port enables direct connection of the computer to at least one external mass storage device. The redundancy controller is configured to provide data redundancy using the internal mass storage device and the at least one external storage device if the at least one external mass storage device is connected to the at least one port.

Abstract: A translation and loopback test for input/output ports is described. In one example, a method includes receiving a test packet on an output of a high speed processor link, looping the test packet back to an input of the high speed processor link, and detecting the receipt of the looped back test packet to test operation of the high speed link.

Abstract: A wireless USB device that performs a communication conforming to a wireless USB standard with a plurality of wireless USB hosts includes a reception-time-information receiving unit that receives reception time information indicating a data reception time specified by each of the wireless USB hosts, a configuration determining unit that determines, when the reception-time-information receiving unit receives the reception time information from a wireless USB host, whether a configuration is set for the wireless USB host, and a configuration unit that sets, when the configuration determining unit determines that the configuration is not set for the wireless USB host that transmitted the reception time information, the configuration for the wireless USB host that transmitted the reception time information.

Abstract: In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.

Abstract: A connection is established between a host device and an internal memory of a computing device. A voltage is received by the computing device from the host device. Upon receiving the regulated voltage, the internal memory of the computing device can exchange data with the host device.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: Embodiments of the invention describe an apparatus, system and method for slave devices to “self-select” their own Inter-Integrated Circuit/System Management Bus (I2C/SMBus) slave addresses upon initialization. Embodiments of the invention describe logic/modules to retrieve a first SMBus slave address included in non-volatile memory for a slave device, wherein said slave device is communicatively coupled to a host system via an SMBus. A first message (e.g., a ping) is transmitted to the first SMBus slave address via the SMBus. If a response to the first message is not received, the first SMBus slave address is selected for the slave device. If a response to the first message is received, the first SMBus slave address is changed by an offset value to determine a second SMBus slave address for transmitting a second message via the SMBus.

Abstract: A method and system for providing computer input/output (I/O) functionality within a remote computing environment. The system comprises a host audio controller and a remote audio controller for bridging audio data between a host computing system and at least one remote audio device, a host USB controller and a remote USB controller for bridging USB data between the host computing system and at least one remote USB device, and an encoder module and a remote display decoder for bridging a digital video signal from the host computing system to a remote display, wherein the host audio controller, the host USB controller, and the encoder module are communicatively coupled to the remote audio controller, the remote USB controller, and the remote display decoder, respectively, via a computer network.

Abstract: The present invention concerns a control device (1) provided for smart card readers (SCR), a smart card reading activation device (2) and associated products including a set-top box and a daisy chain. The control device comprises means for communicating (11) with at least two smart card reading devices (SCR3, SCR4, SCR5), means for processing (12) information received from those reading devices and means for activating (13) at least one of those reading devices for a current communication. The activating means are intended to send selection data (SD) towards all those reading devices, those selection data enabling each of the reading devices to determine if it is selected or not for the current communication.

Abstract: A transceiver apparatus includes a process, a first type of transceiver circuit for data transmission, a second type of transceiver circuit for data transmission, and a communications interface for communicating between the first type of transceiver circuit and an external device. The first type of transceiver circuit is co-located with a physical layer associated with the first type of transceiver circuit. In some embodiments, the first type of transceiver circuit can be, for example, a USB 2.0 transceiver circuit, and the second type of transceiver circuit can be a USB 3.0 transceiver circuit. The aforementioned external device can be an external USB device.

Abstract: The present invention relates to a PCIe switch apparatus and a method of controlling the connection thereof. The PCIe switch apparatus includes a PCIe photoconversion unit for converting an electrical signal input from a local host into packet data and converting the converted packet data into an optical signal. A PCIe slot board unit reconverts the optical signal into the packet data, reconverts the packet data into the electrical signal, and outputs the electrical signal to a PCIe-based device. An optical cable connects the PCIe photoconversion unit and the PCIe slot board unit to each other. The PCIe switch apparatus controls a long-distance communication interface between the local host and the PCIe-based device.

Abstract: An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for coupling to a first pair of differential pins of the USB receptacle, a second group for coupling to a second pair of differential pins of the USB receptacle, a third group for coupling to a third pair of differential pins to the USB receptacle, a ground pin, a first and second power pins. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the USB 2.0 or USB 3.0 signals.

Abstract: Self-authorizing tokens are disclosed. Typical embodiments employ a secure element and a secure element interrogator. Such tokens may be used for authorization of financial payments and other secure transactions. In some embodiments the secure element is provisioned with information about a particular payment card holder account. A secure element reader interrogates the smart element and derives information needed to authorize a transaction. In some embodiments the secure element and the secure element interrogator communicate using communications formatted according to ISO 7816-4.

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

Abstract: Systems and methods schedule periodic and non-periodic transactions in a multi-speed bus environment that includes in a downstream hub a data forwarding component, such as a USB transaction translator, which accommodates communication speed shifts at the hub. The method may comprise receiving a split packet request defining a transaction with a device, tagging the request with an identifier allocated to the data forwarding component, storing the request in a transaction list associated with the identifier, initiating transfer of payload data, and updating a counter associated with the identifier to reflect an amount of payload data for which transfer was initiated. The identifier may have associated therewith a counter for tracking a number of bytes-in-progress to the data forwarding component and one or more transaction lists configured to store a plurality of split packet requests awaiting execution and state information regarding an execution status of the requests.

Abstract: An exemplary Peripheral Component Interconnect Express (PCIE) interface card is electrically coupled to a CPU. The PCIE interface card includes a circuit board, a first PCIE interface module arranged on the circuit board, at least one second PCIE interface module arranged on the circuit board, and a PCIE switch arranged on the circuit board. The PCIE switch is electrically coupled to the first PCIE interface module and the at least one second PCIE interface module. The PCIE switch transmits data from the CPU to the first PCIE interface module, and exchanges data between the CPU and the at least one second PCIE interface module.

Abstract: An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the received address in a register, so as to be identified by the address. A method of address assignment in a master/slave system, the system comprises at least one master, a plurality of slaves, and an I2C or I2C compatible bus. The method comprises sending a first address by the master on the I2C bus to a first of the plurality of slaves and storing the first address on the first slave to identify the first slave by the first address. The method further comprises sending a second address by the master on the I2C bus to a second of the plurality of slaves and storing the second address on the second slave to identify the second slave by the second address. The steps of sending and storing are repeated until all slaves of the system have stored an address.

Abstract: An improved PCI Express multiplier device is disclosed. The PCI Express multiplier device comprises two or more device attachers to attach at least two identical PCI Express devices; a root complex attacher to attach a PCI Express root complex; a copier to copy and forward PCI Express data packets from the root complex to all of the attached identical devices; a collector to collect PCI Express data packets sent from the attached identical devices to the root complex; a selector responsive to the collector to select and forward PCI Express data packets from the collected PCI Express data packets to the root complex.

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

Abstract: System and method for a USB host to determine whether or not a USB device provides power via a USB coupling between the USB host and the USB device. At a first time, it may be determined that the USB device is coupled to the USB host via a USB coupling and does not provide power. Power may be provided to the USB device via the USB coupling. At a second time it may be determined that the USB device does provide power via the USB coupling. Power may no longer be provided to the USB device via the USB coupling after it is determined that the USB device does provide power via the USB coupling. A battery of the USB host may be charged using power provided by the USB device via the USB coupling based on determining that the USB device does provide power via the USB coupling.

Abstract: Systems and methods according to the present invention provide serial communication devices which are pin-configurable at power on to operate as either a root (20) or endpoint (22) device. In conjunction with, for example, PCI Express specified I/O data buses (24), such devices provide for efficient transfer of serial data between systems and devices.

Abstract: An apparatus for peer-to-peer communication over a Universal Serial Bus (USB) link, the apparatus comprising a USB 3.0 compliant switch to be coupled between a first peer unit and a second peer unit to form a first path, wherein each of the first peer unit and the second peer unit supports a USB type of communication a USB 2.0 compliant bridge to be coupled between the first peer unit and the second peer unit to form a second path a detector to detect the USB type of each of the first peer unit and the second peer unit and a controller to establish the USB type of communication between the first peer unit and the second peer unit over a USB link via the first path or the second path, wherein the controller is configure to selectively switch the USB link to the first path or the second path based on the USB types of the first peer unit and the second peer unit.

Abstract: The present invention is directed to a method for implementing firmware in an expander system in such a way that a single hardware component (ex.—a chip) of the expander system may be presented as multiple virtual expanders to both upstream connected devices (ex.—HBAs) as well as downstream connected devices (ex.—disk drives).