Abstract: A PCI card's HBA identifier table held in an IODC in an IO slot expansion unit is read and recorded on a PCIe switch register of a PCIe switch. After a server blade is powered on so that an EFI is activated, the EFI reads the HBA identifier table recorded on the PCIe switch register and updates an HBA identifier of an HBA mounted in each PCI card. The HBA mounted in the PCI card operates with the updated HBA identifier of the PCI card. Thus, even when the PCI card is replaced by a new PCI card because of failure or the like, the new PCI card can operate with the same HBA identifier as that before the replacement. Therefore, a user does not have to register the HBA identifier of the PCI card newly in a device connected to the PCI card.

Abstract: A method for sending readiness notification messages to a root complex in a peripheral component interconnect express (PCIe) subsystem. The method includes receiving a device-ready-status (DRS) message in a downstream port that is coupled to an upstream port in a PCIe component. The method further includes setting a bit in the downstream port indicating that the DRS message has been received.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: An example method is provided and includes receiving a first signal transmitted to an address on a two-wire bus from a master device, where the two-wire bus couples the master device with a first slave and a second slave that share the address such that the first slave and the second slave receive the first signal. The method includes blocking a second signal from the second slave to the master device using digital isolation buffers. In particular embodiments, the digital isolation buffers are configured between the master device and the second slave. In addition, the two-wire bus may include a clock line and a data line. The digital isolation buffers may include a first digital isolation buffer located on the clock line between the master device and the second slave, and a second digital isolation buffer located on the data line between the master device and the second slave.

Abstract: A method to interact with a local USB device is disclosed. Messages are transmitted to a remote host controller driver from a host controller associated with the local USB device. Messages are received from the remote host controller driver for the host controller. In some embodiments, a transfer descriptor prototype is received from the remote host controller driver. A completed transfer descriptor is received from the remote host controller driver. The completed transfer descriptor and the transfer descriptor prototype are transformed into a modified transfer descriptor in part by using a collection of rules. The modified transfer descriptor is submitted to the local host controller without intervention from the remote host controller driver.

Abstract: Circuits, methods, and apparatus that reduce the power consumed by transactions initiated by a number of USB host controllers. Peripheral devices on a number of USB networks are accessed in a coordinated manner in order to reduce power dissipated by a CPU and other circuits when reading data needed by the host controllers. The resulting memory reads are temporally clustered. This allows the CPU to process a greater number of requests each time it leaves a low-power state. As a result, the CPU may possibly remain in a sleep state for a longer period of time, thus saving power. This is accomplished at the host controller level by synchronizing the time frames used by each host controller in a system. The synchronizing signal may be one or more bits of a frame count provided by one host controller to a number of other frame controllers.

Abstract: An I/O bridge device includes: a command receiver that receives a command signal indicating a command to a memory controller from a peripheral component; a converter that converts the command signal into a command packet including the command and identification information for identifying the command signal; a command transmitter that transmits the command packet to the memory controller; a response receiver that receives, from the memory controller, a response packet to the command packet, the response packet including the identification information; and a write command transmitter that transmits a write command signal to the peripheral component that is a transmission source of the command signal, the write command signal indicating a command for the writing a content of the response packet to an internal memory of the peripheral component.

Abstract: A method for transmitting data between two storage virtualization controllers (SVCs) is disclosed in the present invention.

Abstract: Provided is a programmable logic system for controlling an external device including a first processor and one or more system input/output (I/O) modules coupled to the processor via an interface. The programmable logic system also includes a configurable hardware module coupled to the processor and the I/O modules via the interface.

Abstract: A USB device and a detection method therefor. It can be detected whether the USB device is a master device or a slave device without the use of an ID pin, thereby saving the pin resources of the USB device.

Abstract: A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels.

Abstract: Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.

Abstract: A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result.

Abstract: A configurable system for translating, exchanging and integrating data and services among disparate software applications is provided. The system includes a first connection that interfaces with an enterprise system, a second connection that interfaces with a legacy system, and an adapter module coupled to the first and second connections. The adapter module is configured to receive data from the first connection and pass data to the second connection. The system may also include a transform module configured to manipulate data received at the second connection. The adapter module may be single-channel or multi-channel. A multi-channel adapter module is able to interface with multiple legacy systems and/or multiple enterprise systems.

Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.

Abstract: An expansion card and method for controlling a radio system integrates PCDD operations into a PCMCIA or ExpressCard which can be inserted into an external display, smart screen PCMCIA slot, or laptop ExpressCard or PCMCIA slot to allow an operator to control the radio system with a computer without any modification of the computer.

Abstract: A vehicular interface may include an electromechanical interface between a handheld electronic device and subsystems on a vehicular bus or network. In selected embodiments the interface may operate in a “master mode” when a handheld device, such as a tablet computer or smart-phone, is not inserted therein. In this mode the interface may serve as a master controller and accesses and controls various subsystems on a vehicle (such as engine control subsystems, media controllers, navigation systems, sensors and transducers) as a master controller. In one embodiment, when a tablet device is inserted into the interface, the interface may automatically switch to “slave mode” in which it acts as an adapter or interface between the tablet device and the vehicular subsystems. In this mode of operation the user's exclusive interface is through the tablet computer and the tablet computer serves as the master controller for the system.

Abstract: An expandable hybrid storage device for a computer system includes a first storage unit, an expanded storage device including a disk controller and a second storage coupled to the disk controller via a second data transmission interface, and a selection unit coupled to the first storage unit via a first data transmission interface for selectively connecting the first storage unit to a south bridge circuit of the computer system or the expanded storage device, wherein when the expanded storage device connects to the computer system, the selection unit switches the first storage unit to the expanded storage device so that the disk controller is capable of controlling access to the first storage unit or the second storage unit.

Abstract: Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.

Abstract: Certain embodiments of the present disclosure are directed to a baseboard management controller (BMC) that includes a PCI express (PCIe) interface controller configured to provide access to a PCIe channel over a PCIe link, and firmware. The firmware includes a PCIe module being configured to access the PCIe channel through the PCIe interface controller and registered as a PCIe function. A software stack of the BMC communicates, through the PCIe module, with a PCIe device over the PCIe channel.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: A processor module includes at least one storage device, at least one central processing unit (CPU) that uses a preset interface, and a module controller to relay a connection between a common interface bus formed on the based board and an interface used by the CPU.

Abstract: A method for providing identifiers for virtual devices in a network. The method comprises receiving a discovery data packet directed to a physical network node associated with a physical endpoint device. A response to the discovery data packet directed to a physical network node is provided, the response comprising an identifier of a virtual device. At least one further discovery data packet directed at least to said virtual device is received. A response to a first one of the further discovery data packets is provided, the response comprising an identifier of a virtual endpoint device. At least some functionality of the virtual endpoint device is provided by the physical endpoint device.

Abstract: A detecting unit detects a connection of an external device to a connection port and stores the connection in a bridge state storage unit. This setting is autonomously completed by a device before an initial configuration is started by a host. A data transfer unit receives initial configuration data of a link-connection bridge from the host. Data is transferred to the linked-uplink-connection bridge with reference to the bridge state storage unit, data to a bridge which is not linked up is wasted, or an Unsupported Request is returned to the host to represent the absence of the link-connection bridge.

Abstract: An indication of a version of a firmware stored in an input/output adapter may be provided by a method that includes detecting whether a first pin is connected to an external circuit, detecting whether a second pin is unconnected to an external circuit, and causing the indication to be provided if the first pin is connected and the second pin is unconnected. The indication may be provided on the first pin. The first pin may include a power supply pin and the indication may be an average rate of power supplied to the input/output adapter.

Abstract: The present invention provides a method and apparatus for controlling the operating condition of a peripheral device based on the mode of interconnection of the peripheral device of a host device. The apparatus includes a first connector for connecting the peripheral device, a second connector for connecting the host device and a coupling system operatively interconnecting contacts of the first connector and contacts of the second connector. The coupling system is further configured to provide a supply signal to the peripheral device via the first connector, wherein the supply signal is at least in part indicative of one or more characteristics of the power available to the peripheral device from the host device. The supply signal may provide a means for the peripheral device to control operation thereof in light of the characteristics of the power available.

Abstract: Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system.

Abstract: An interface extension device is disclosed. The interface extension device includes a USB port, a USB hub and a first interface conversion circuit. The USB hub has a first port connected to the USB port. The first interface conversion circuit includes first and second USB hosts. The first USB host is connected to the USB hub and is connected to the USB port through the USB hub. The second host has a bus and is directly connected to the USB port without routing though any USB hub.

Abstract: Embodiments of the present invention provide a system and a method for transmitting data based on Peripheral Component Interconnect Express 9PCIe). The system includes: a PCIe switching network, multiple switch terminal devices, a managing unit, multiple host processing units, multiple terminal processing units, multiple hosts, and multiple terminal devices. After a PCIe data packet sent by a host is processed by a host processing unit, a new PCIe data packet that can be transmitted in a PCIe switch is constructed, and is transferred, by using a switch terminal device and a terminal processing unit, to a terminal device. The embodiments can break through a limitation about a single root node of PCIe and implement sharing of a PCIe switching network by multiple hosts.

Abstract: A control circuit (comprising, for example, a part of a charging hub for a portable electronic communications device) that is not configured to support USB On-The-Go-compatible Host Negotiation Protocol is operably coupled to a USB-ID connector and is configured to transmit an identifier via that USB-ID connector to prompt a USB device in function mode to serve as a USB host. A locally-available power supply can then serve to provide power to that USB device notwithstanding the latter's role as the host.

Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.

Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

Abstract: A signal processing apparatus and a control method thereof are provided. The signal processing apparatus includes a signal processor which processes a video signal and/or an audio signal; a power supply which generates a power signal; a first connector configured to be connected with an external second connector; and a control circuit which outputs the video signal and/or audio signal and the power signal if the external second connector is connected to the first connector, and performs a shutoff operation to not output the power signal if the first connector is not connected to the external second connector.

Abstract: In a method for registering identification information of network interface cards (NICs) in an operating system of a computing device, each of the NICs is respectively and uniquely labeled with a number. A peripheral component interconnect (PCI) device identification (ID) of each of the NICs is allocated according to the labeled number of each NIC using a basic input output system (BIOS) of the computing device when the BIOS is booted up. Then identification information of each of the NICs is registered in the operating system according to the PCI device ID of each NIC using a NIC driver of the computing device, when the NIC driver is driven by the operating system during the booting up process of the operating system.

Abstract: Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.

Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

Abstract: The present invention discloses a method to identify whether a USB or a charger is plugged into a mobile terminal and an identification device thereof. The identification device comprises a USB interface module connected with an external power supply device, an interface detection and control module, an electronic switch module, a charging switch module, an identification module and a baseband USB data transceiving module. With the method to identify whether a USB or a charger is plugged into a mobile terminal and an identification device thereof provided by the present invention, when an external power supply is plugged in, the identification device makes the terminal to preferentially enter a USB mode, while, according to the ultimately detected D-signal state, interrupt responses can be flexibly generated to accurately determine the presence of a USB or a charger. It can quickly and accurately identify the type of USB or charger plugged into the terminal.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: The disclosed inventions relate to the field of power control electronics. More specifically the disclosed inventions pertain to Power Stack Control Systems which are used to control the generation of AC power from a DC or AC input voltage. The disclosed Power Stack Control Systems include a serial interface connection, the serial interface connection being in serial electrical communication with a plurality of power stacks, the plurality of power stacks comprising at least one interface board and at least one IGBT driver board, the at least one interface board being in parallel communication with at least one IGBT driver board.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A multifunctional mobile telephone handset is connected to a PC using a Universal Serial Bus. During bus enumeration, a device class descriptor is returned by the handset to the PC. The PC's operating system receives information relating to one of the functions of the handset and assigns an appropriate device driver.

Abstract: Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.

Abstract: The present invention relates to amounting structure for Mini PCI-E equipment is provided. The mounting structure comprises a Mini PCI-E slot and a fixing bracket, wherein the Mini PCI-E slot is welded on surface of a motherboard with an opening upward and perpendicular to the motherboard, the fixing bracket is close to the Mini PCI-E slot and fixed vertically on the motherboard. The fixing bracket includes a first fixing device which includes at least two mounting holes at the same height. The present invention also disclosed a computer using the above mounting structure. The mounting structure of the present invention could significantly reduce the area on the motherboard occupied by the Mini PCI-E equipment via setting the Mini PCI-E slots and the mounting bracket perpendicular to the motherboard. The above mounting structure could also improve the performance of heat dissipation of the Mini PCI-E equipment.

Abstract: An embodiment may include circuitry to (a) convert, at least in part, at least one serial storage protocol compatible frame into at least one packet that is compatible, at least in part, with a multi-lane input/output (I/O) protocol, and/or (b) convert, at least in part, the at least one packet into the at least one frame. The at least one packet may be transmitted via a physical layer that is compatible, at least in part, with the multi-lane I/O protocol. The at least one packet may comprise frame information structure (FIS) information of the at least one frame.

Abstract: A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters at I/O adapter addresses, the I/O hub including logic for implementing a method comprising receiving requests from the plurality of I/O adapters, storing the I/O adapter addresses of a requester along with their corresponding target recipient addresses and operation codes, receiving a response from a responder, the response indicating that a request has been completed, determining that the response is in a format other than a format supported by the I/O bus, transforming the response into the format supported by the I/O bus, locating a stored I/O adapter address having a corresponding target recipient address that matches the responder address and a corresponding operation code that matches the responder operation code, and transmitting the response to the stored I/O adapter address.

Abstract: A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.

Abstract: A USB-to-SDIO bridge (UTSB) to efficiently transmit SD/SDIO commands in USB packets. The UTSB may allow the majority of the device drivers for a given SD/SDIO device to remain intact, requiring changes only in the lowest hardware adaptation layer to put a USB wrapper around native SD commands. These commands may be sent over USB-to-SD card reader devices that may include various embodiments of a UTSB, where they may be unwrapped and transmitted to the SD port as if the port were native to the host controller. Additionally, the SD/SDIO commands may be packaged into groups of commands, or transactions, to optimize performance. The host driver may instruct the UTSB bridge device to repeatedly read data from the SDIO device until a communications FIFO on the device is empty (corresponding to a termination condition), and return the collected data to the host.

Abstract: An electronic apparatus includes a first communication unit configured to perform I2C bidirectional communication with an external apparatus using two signal lines included in a transmission path as I2C communication lines, a second communication unit configured to perform bidirectional differential communication with the external apparatus using the two signal lines as high-speed data communication lines, a switching unit configured to select a first communication state in which the first communication unit is connected to the two signal lines or a second communication state in which the second communication unit is connected to the two signal lines, and a controller configured to control operation of the switching unit.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.