Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.

Abstract: Embodiments using a distributed bus arbiter for one cycle channel selection with inter-channel ordering constraints. A distributed bus arbiter that orders one or more memory bus transactions originating from a plurality of master bus components to a plurality of shared remote slaves over shared serial channels attached to differing interconnect instances may be implemented.

Abstract: A computer device includes a central processing unit (CPU), a network adapter, a bus, and an intermediate device, where the intermediate device is coupled to both the CPU and the network adapter through the bus, and is configured to establish a correspondence between address information of an agent unit and address information of a function unit, and implement forwarding of a packet between the CPU and the network adapter based on the correspondence.

Abstract: Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.

Abstract: Systems and methods of operating a distributed cache in a fast producer, slow consumer environment are disclosed. A system implements a distributed cache including a plurality of shards. Each shard includes a set of item containers selected from a plurality of containers. A first event related to a first item container in the set of item containers is received and the first item container is updated to include the first event. The first item container is positioned in at least one consumption queue. A second event related to the first item container in the set of item containers is received and the first item container is updated without changing the position of the first item container in the at least one consumption queue.

Abstract: System and method for sharing a PCIe endpoint device with a plurality of host computers, by allocating a quantum of time to a host computer of a plurality of host computers coupled to a PCIe switch, wherein the quantum of time identifies a duration of time during which the host computer has exclusive access to a shareable PCIe endpoint device coupled to the PCIe switch. Requests from the host computer are transmitted to an emulated PCIe endpoint device of the PCIe switch during the quantum of time and the requests are then redirected from the emulated PCIe endpoint device to the shareable PCIe endpoint device during the quantum of time allocated to the host computer.

Abstract: A user interface and method. A user interface and method of using said interface that uniquely applies a web browser navigation style to engineering analysis applications is disclosed herein. The user interface, which may be implemented at least in part by use of a computer system, may comprise a browser panel, a tabbed workspace, a graphics view, a search box, and a search and select bar.

Abstract: A method, a set-top box, and non-transitory computer readable medium are disclosed for detecting incompatible cables for devices. The method includes: setting, on an electronic device, a high speed data-transfer mode; sending, from the electronic device, data to a device at the high speed data-transfer mode over a cable under test; determining, on the electronic device, a number of authentication attempts by the device; and determining, by the electronic device, that the number of authentication attempts by the device is less a predetermined number that the cable under test is compatible with the high speed data-transfer mode.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.

Abstract: Disclosed embodiments relate, generally, to traffic shaping at a network segment having a shared bus. Some embodiments relate to performing aspects of the traffic shaping at a physical layer device. In some cases, transmit timeslot signaling may be tuned at a physical layer device to create transmit timeslots that are aligned with the traffic shaping profile.

Abstract: A host device is configured to communicate over a network with a storage system comprising a plurality of storage devices. The host device comprises a multi-path input-output (MPIO) driver configured to control delivery of input-output (IO) operations from the host device to the storage system over a plurality of paths through the network. The MPIO driver is further configured to identify whether given ones of a plurality of initiators associated with the paths comprise given ones of a plurality of virtual initiator instances, and to identify given ones of a plurality of virtual IO servers corresponding to the given ones of the virtual initiator instances. The MPIO driver is also configured to detect a failure of an IO operation over a first path, and to select a second path for retrying the IO operation based on the identification of the virtual IO servers corresponding to the virtual initiator instances.

Abstract: An optical port routing enclosure and programmable NIC card as well as cluster topologies leveraging same are provided.

Abstract: Described herein are techniques for managing failover in a data center environment interconnected using an internet small computer systems interface (iSCSI) communication protocol, the techniques including receiving, at a host and from a kernel driver, an asynchronous message comprising an indication of a failed path associated with a first node having a first port, a list of internet protocol (IP) addresses associated with a plurality of failover paths including a first failover path associated with a second node having a second port, and an expiration. The techniques further including performing, by the host and before the expiration, a first input/output (I/O) operation on the second port associated with the second node. The techniques further including performing, by the host and after the expiration, a second I/O operation on the first port of the first node.

Abstract: An apparatus and method for protecting content in a graphics processor. For example, one embodiment of an apparatus comprises: encode/decode circuitry to decode protected audio and/or video content to generate decoded audio and/or video content; a graphics cache of a graphics processing unit (GPU) to store the decoded audio and/or video content; first protection circuitry to set a protection attribute for each cache line containing the decoded audio and/or video data in the graphics cache; a cache coherency controller to generate a coherent read request to the graphics cache; second protection circuitry to read the protection attribute to determine whether the cache line identified in the read request is protected, wherein if it is protected, the second protection circuitry to refrain from including at least some of the data from the cache line in a response.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: A method for deploying a task includes deploying the task in the supercomputer; executing the task; at the end of the execution of the task, detecting at least one link which is not allocated to any task, and setting each detected link in an inactive state, wherein the link requires a power consumption less than the power consumption required by a link associated with at least one task.

Abstract: A semiconductor device includes a read/write control circuit, a core circuit, and a data conversion circuit. The read/write control circuit generates a read strobe signal and a read address from an internal address/command signal based on an internal read command during a self-write operation, generates a write strobe signal after the read strobe signal is generated, and generates a write address from the internal address/command signal. The core circuit is synchronized with the read strobe signal to output read data stored in a bank selected by the read address and is synchronized with the write strobe signal to store write data into the bank or another bank which is selected by the write address. The data conversion circuit changes a pattern of the read data to generate the write data.

Abstract: A cloud gaming system includes a cloud storage system and a cloud compute system connected together through a PCIe switch and PCIe fabric. The PCIe switch is configured to map resources within the cloud storage system to a memory map of the cloud compute system. The PCIe switch is configured to map resources within the cloud compute system to a memory map of the cloud storage system. The PCIe fabric enables transfer of a data input/output command buffer generated by the cloud compute system to the cloud storage system by either a direct write or a direct read between the cloud compute system and the cloud storage system. The PCIe fabric enables transfer of data between the cloud storage system and the cloud compute system, as indicated by the command buffer, by either a direct write or a direct read between the cloud compute system and the cloud storage system.

Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to control delivery of input-output (IO) operations from a host device to at least one storage system over selected ones of a plurality of paths through a network, wherein the paths are associated with respective initiator-target pairs, the initiators being implemented on the host device and the targets being implemented on the storage system. The processing device is further configured to identify one or more of the plurality of paths that each exhibits at least a threshold amount of mismatch between a negotiated rate of its initiator and a negotiated rate of its target, and to modify path selection in the host device to at least temporarily avoid selecting the one or more identified paths. The processing device illustratively comprises at least a portion of the host device.

Abstract: Embodiments described herein provide a system to configure distributed training of a neural network, the system comprising memory to store a library to facilitate data transmission during distributed training of the neural network; a network interface to enable transmission and receipt of configuration data associated with a set of worker nodes, the worker nodes configured to perform distributed training of the neural network; and a processor to execute instructions provided by the library, the instructions to cause the processor to create one or more groups of the worker nodes, the one or more groups of worker nodes to be created based on a communication pattern for messages to be transmitted between the worker nodes during distributed training of the neural network.

Abstract: Various implementations include devices and approaches for managing multimedia communications. In one aspect, a computer-implemented method of controlling a device connection includes: receiving audio data and video data from an input device connected with a peripheral bus input port; converting the audio data for transmission over an audio over internet protocol (IP) connection or a balun connection and converting the video data for transmission over a video over internet protocol (IP) connection or the balun connection; and transmitting the converted audio data and the converted video data for decoding and output to at least one output device via a multimedia audiovisual interface output port, where the peripheral bus input port is configured to support bidirectional audio and bidirectional video exchange with the input device and bidirectional exchange of IP-based control signals or balun-based control signals with the input device.

Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Abstract: A universal serial bus (USB) apparatus that has a USB hub, a first switching unit including first end coupled to a USB peripheral port of a first device, a second switching unit including a second end coupled to the USB hub and the first switching unit and a first end configured to be coupled to a first USB device, and control circuitry operable to provide control signals to the first and second switching units, in which the first control signals cause the first and second switching units to provide connectivity between the USB peripheral port of the first device and the first USB device when the first USB device is operating as a USB host and the second control signals to provide connectivity between the USB host port to the first USB device via the USB hub when the first USB device is operating as a USB peripheral.

Abstract: A power management method and device for a multi-operating system (OS) electronic apparatus can employ a host OS including first power attribute files, each including a power pack name and a power attribute name. A guest OS includes second power attribute files, each including a pack name code and an attribute name code corresponding respectively to a power pack name and a power attribute name in each first power attribute file. When any second power attribute file is called, a pack name code and an attribute name code corresponding thereto are decoded in the guest OS to obtain a called power pack name and a called power attribute name, which are then sent to the host OS. The host OS then provides the corresponding first power attribute file to the guest OS. The invalidity risk of any power attribute file in the multi-OS electronic apparatus can therefore be reduced.

Abstract: A computer vision system includes a camera that captures a plurality of image frames in a target field. A user interface is coupled to the camera. The user interface is configured to perform accelerated parallel computations in real-time on the plurality of image frames acquired by the camera. The system provides an accountability measurement of impact of architecture and design work.

Abstract: The present invention is directed to optimization and failure detection of a wireless base station network. Based on an RF link attenuation measurement, e.g., a Received Signal Strength Indication (RSSI) measurement, a server determines an optimal transmission sequence. For each base station of the optimal transmission sequence, a predecessor and a successor are designated. Each base station of the sequence generates a packet. The most distant base station (relative to the server) transmits its packet to its successor. Each base station of the sequence (in turn) receives the packet from its predecessor, combines the received packet with its own generated packet, transmits the combined packet to its successor, and so on until the combined packet is relayed to a super base station at the end of the sequence. The super base station transmits the packet to the server. Based on the packet size, the server can ascertain which base station (if any) failed.

Abstract: A method, an apparatus, and an electronic device for controlling memory access are disclosed. According to an embodiment, there is provided a method for controlling access to a memory including a plurality of memory modules configured in parallel. The method comprises: receiving an access instruction including an addressing field which comprise a parallel control field for controlling parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an addresses within a memory module; parsing the access instructions to determine the parallel control field, the module address field and the in-module address field; determining one or more memory modules to be accessed based on the parallel control field and the module address field; and accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field.

Abstract: A NUMA-aware storage system including a first processing subsystem coupled to a first memory subsystem, and a second processing subsystem coupled to a second memory subsystem. A first NTB subsystem connected to the first processing subsystem presents itself as a first storage device, identifies first data transfer operations directed to the first memory subsystem and, in response, claims those first data transfer operations and provides them directly to the first processing subsystem. A second NTB subsystem connected to the second processing subsystem presents itself as a second storage device, identifies second data transfer operations directed to the second memory subsystem and, in response, claims those second data transfer operations and provides them directly to the second processing subsystem. A storage controller system receives a command from either the first or second processing subsystem via the first or second NTB subsystem and, in response, transmits that command to a storage system.

Abstract: Methods and systems for collaborative learning and enabling skills among smart devices within a closed social network group are disclosed. A method includes: receiving, by a computing device from a first smart device, a request for steps to perform an activity; determining, by the computing device, the steps to perform the activity using a knowledge corpus; translating, by the computing device, the steps into a format that is compatible with the first smart device; and sending, by the computing device, the translated steps to the first smart device.

Abstract: A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.

Abstract: An arithmetic processing device includes arithmetic processing units configured to perform arithmetic processing; first routers connected to the plurality of arithmetic processing units, respectively; first buses connecting the plurality of first routers in a ring shape; and second buses connecting between one of the plurality of first routers and any one of the other first routers excluding the first routers directly connected through the first buses.

Abstract: An operation method of a transmitting apparatus in a wireless communication system includes transmitting, to a receiving apparatus, reverse mapping flag information indicating a direction of mapping data symbols to one or more subcarriers included in a resource block allocated to the receiving apparatus; mapping the data symbols to the one or more subcarriers of the resource block based on the reverse mapping flag information; and transmitting the resource block to the receiving apparatus. According to the embodiments of the present disclosure, the amount of subcarrier phase shift noises due to an SFO occurring in proportion to synchronization impairment and subcarrier index can be reduced in a multi-carrier communication system, thereby increasing data retransmission efficiency.

Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

Abstract: A method for managing traffic of a plurality of packets in a plurality of packet flows transmitted using a time-slotted interface. The packet flows traverse a plurality of switches of a transport network according to an assigned path from a source node to a destination node. The method comprises determining an end-to-end latency of a plurality of packets traversing a current switch in packet flows and assigning priority values to the packets traversing the current switch, wherein a priority value of a packet depends on the determined end-to-end latency of said packets. The method further comprises allocating a time slot in an output interface of the current switch to the packet having the highest priority value among the packets competing for said time slot.

Abstract: Described are programmable IO devices installed on a host device and configured to execute instructions that cause the programmable IO device to perform operations to establish a virtual link between another programmable IO device installed on the host device and provide a data plane using the virtual link. These operations comprise: establishing the virtual link with the other programmable IO device installed on the host device, wherein the virtual link provides a communication channel between the programmable IO devices; providing the data plane by establishing, with the other programmable IO device via the virtual link, a data path associated with the data plane; receiving a packet in the data plane destined for the other programmable IO device; and forwarding the packet to the other programmable IO device via the virtual link.

Abstract: The present disclosure provides a protection group superposition switching method, a control apparatus, and an optical communication device. Multiple protection state machines are implemented by using a field programmable gate array (FPGA). Each protection state machine independently performs an automatic protection switching (APS) protocol operation for at least one protection group that is pre-associated with the protection state machine. At least one protection status table for recording a status of each protection group is updated according to a result of the APS protocol operation, and a cross-connection table for traffic cross-connection between communication units is updated according to the protection status table; the updated cross-connection table is configured into a cross-connection chip, so that the cross-connection chip performs traffic cross-connection according to the updated cross-connection table.

Abstract: The invention relates to a software defined device interface system 10, a software defined device interface, gateway and a method of defining an interface for a device which uses a specific communication protocol for communication purposes. The system 10 includes a microprocessor/processing unit 12.1, 12.2 with a plurality of communication pins and software/firmware. The software/firmware is configured, based on a specific communication protocol which is used by a particular device 30.1-30.4 for communication purposes, to, in runtime, assign/select one or more of the communication pins to form a virtual port to which the particular device 30.1-30.4 can be connected, upon receiving a configuration instruction from a user to implement the specific communication protocol. The software/firmware is further configured to implement the specific communication protocol through the virtual port, to thereby allow for communication between the microprocessor/processing unit 12.1, 12.2 and the device 30.1-30.

Abstract: The present disclosure provides a Type-C interface controlling circuit, a controlling method, and a mobile terminal, wherein the Type-C interface controlling circuit includes: a Type-C interface, a first transmission module, a second transmission module, a switching module, and a detection module. The first end of the detection module is connected to the Type-C interface for detecting a connection state of the Type-C interface, and the second end of the detection module is connected to the switching module, and the detection module controls a connection relationship between the first end of the switching module and the second end of the switching module according to the connection state.

Abstract: A computer vision system includes a camera that captures a plurality of image frames in a target field. A user interface is coupled to the camera. The user interface is configured to perform accelerated parallel computations in real-time on the plurality of image frames acquired by the camera. The system detects and tracks animal wellness and habitat/intervention design.

Abstract: Technologies for error recovery in compressed data streams include a compute device configured to compress uncompressed data of an input stream to generate compressed data, perform a compression error check on the compressed data to verify integrity of the compressed data, and determine, as a result of the performed compression error check, whether the compressed data included a compression error. The compute device is further configured to transfer, in response to a determination that the performed compression error check indicated that the compressed data included the compression error, the uncompressed data into a destination buffer, and store an indication with the uncompressed data into the destination buffer, wherein the indication is usable to identify that the uncompressed data has been transferred into the destination buffer. Other embodiments are described herein.

Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.

Abstract: A method of facilitating communication to an embedded computer in a computational storage device via a host includes receiving a message for transmission to an embedded process running at the embedded computer, determining that a destination address of the message corresponds to the embedded computer within the computational storage device, in response to the determination, forwarding the message to a host relay process associated with the embedded computer, and encapsulating the message to generate a proprietary command for transmission to the computational storage device.

Abstract: The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of subarrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.

Abstract: A method and system for configuring a USB3 input/output port in a camera are disclosed. The method comprises responsive to an indication that a peripheral device is a non-USB3 device, remapping pins of the USB3 input/output port to a first predefined port configuration associated with an I2C protocol by remapping a RX1? pin to communicate a first I2C signal and remapping a RX1+ pin to communicate a second I2C signal, and responsive to successful authentication between the camera and the peripheral device via the I2C protocol, enabling communication with the peripheral device and remapping the pins of the USB3 input/output port to a second predefined port configuration compatible with operation of the authenticated peripheral device by remapping a TX2+ pin to communicate a first general purpose input/output signal and remapping a TX2? pin to communicate a second general purpose input/output signal.

Abstract: A system and method to balance computational loads across multiple computing systems, such as servers in a server cluster, is disclosed. The system includes a load balancer. Upon receiving a new computing request corresponding to an expected throughout, the load balancer identifies a computing system that is most likely to fail and sends the new computing request to a different computing system. The load balancer uses a mutational algorithm to identify potentially problematic throughputs for a given computing system in a given state. The mutational algorithm is used to determine latency-throughput curves that are fit to a data population that includes many diverse data points with relatively high slopes in a 2D latency-throughput space.

Abstract: A circuit includes a regulation circuit configured to intercept messages on a configuration channel of a universal serial bus (USB) cable between a USB source device and a USB sink device. The regulation circuit regulates a source capability message from the USB cable configuration channel based on a predetermined power capability of the USB cable.

Abstract: A control apparatus includes first and second regions that each store device information of a monitoring target device; an evacuating region; and a processor configured to execute a procedure including: controlling switching between first and second states at a predetermined timing, the first state including the first region being in updatable and unreferenceable states and the second region being in referenceable and unupdatable states, the second state including opposite states to the first state; evacuating, in a case where the second region is being referred at a timing when the first state is switched to the second state, unreferred information stored in the second region to the evacuating region; controlling, after completion of evacuation, switching the state of the second region from referenceable to updatable; and controlling, after completion of reference to the unreferred information in the evacuating region, switching the state of the first region from updatable to referenceable.

Abstract: The present invention is directed to optimization and failure detection of a wireless base station network. Based on Received Signal Strength Indication (RSSI) measurements, a cloud server determines an optimal transmission sequence. For each base station of the optimal transmission sequence, a predecessor and a successor are designated. Each base station of the sequence generates a packet. The most distant base station (relative to the cloud server) transmits its packet to its successor. Each base station of the sequence (in turn) receives the packet from its predecessor, combines the received packet with its own generated packet, transmits the combined packet to its successor, and so on until the combined packet is relayed to a super base station at the end of the sequence. The super base station transmits the packet to the cloud server. Based on the packet size, the cloud server can ascertain which base station (if any) failed.

Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.