Abstract: Embodiments of the present disclosure provide a method and apparatus of maintaining data consistency by receiving, when a first storage processor is in a Ready state, a request for configuration information of a storage object from a second storage processor; in response to receiving the request, setting the first storage processor to an Updating-Peer state, and sending the configuration information to the second storage processor to maintain consistency of the configuration information in the first and second storage processors; and in response to the configuration information being sent, setting the first storage processor back to the Ready state.

Abstract: A failover method, apparatus and system to implement fast failover between a primary processor and a secondary processor, where the method includes receiving, by a second device, a transaction processing packet, where the transaction processing packet includes processing information about access of a host to a peripheral component interconnect express (PCIe) device, the processing information is used to describe information required for resuming a transaction when the transaction is interrupted, the second device further stores topology information of the PCIe device, and a driver for the PCIe device is loaded to the second device, and when detecting that the first device fails, continuing to process, by the second device according to the topology information, the driver, and the processing information, the transaction that is about the access of the host to the PCIe device and is being processed when a first device fails.

Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.

Abstract: The disclosure describes a system including a first computer system including a first memory controller and a first inter-computer transfer interface to send information about write operations over an interconnect to a second computer system. A second computer system includes a second memory controller and a second inter-computer transfer interface to receive the information about the write operations over an interconnect, wherein the write operations are duplicated through the second memory controller. In other embodiments, a system includes a first computer system including a first memory controller and a first inter-computer transfer interface to send information about write operations of the first computer system during a lockstep operation. Still other embodiments are described.

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.

Abstract: An electronic assembly perform data storage operations on behalf of a set of storage processors (SPs). The electronic assembly includes an enclosure, and a set of peripheral component interconnect express (PCIe) switches which installs within the enclosure. The set of PCIe switches is constructed and arranged to connect to the set of SPs while the set of SPs is external to the enclosure. The electronic assembly further includes a set of data storage devices which installs within the enclosure. The set of data storage devices is constructed and arranged to persistently store data on behalf of the set of SPs via PCIe-based communications through the set of PCIe switches.

Abstract: A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer. The Input-Output (I/O) is uniformly viewed and treated as an individual First-In-First-Out (FIFO) device. Pluralities of memory areas are implemented for user stack, kernel stack, interrupt stack and procedure call stack. Only one I/O arbiter is necessary for a CPU model that arbitrates between a plurality of FIFOs substituting data caches for on-chip implementation, thus eliminating traditional data transfer techniques using Direct-Memory-Access (DMA), bus control and lock signals leaving just the interrupt signals and the new synchronous signals for an easy and streamlined system design and CPU model. Supporting an interrupt-driven, FIFO-based I/O and synchronous burst data transfer the CPU employs a simple linear large register sets without bank switching.

Abstract: A programmable system includes a programmable analog system that is reconfigurable to perform various analog operations, and includes a programmable digital system that is reconfigurable to perform various digital operations. The programmable system also includes a microcontroller capable of reconfiguring and controlling the programmable analog system and the programmable digital system. The programmable digital system is configured to control the programmable analog system autonomously of the microcontroller.

Abstract: A physical layer network interface module (PHY-NIM) adaptation system provides a PHY-NIM device and an attachable media access control (MAC) device. The PHY-NIM device interconnects with the attachable MAC device and the attachable MAC device interconnects to a network appliance to provide at least one of network switch capabilities and MAC device capabilities for use by the network appliance. The PHY-NIM device interconnects directly to the network appliance where the network appliance has at least one of an internal network switch and an internal MAC device in a southbridge input/output (I/O) interface chip of the network appliance.

Abstract: A serial peripheral interface is configurable to operate in a I2S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.

Abstract: An apparatus comprises a printed circuit board (PCB) having a first surface and a second surface, a plurality of blind press-fit vias penetrating the first surface and extending partially through the PCB toward the second surface, the blind press-fit vias configured to receive press-fit connectors of at least one component to be connected to the PCB, and a plurality of electrical connectors disposed in a region of the second surface opposite the blind press-fit vias and configured to interface with one or more signal processing components disposed on the second surface.

Abstract: Systems and methods are disclosed for effectuating control-plane changes at increased speeds to protect a network in which switching operations are performed. Operations to effectuate control-plane changes in the network can be divided between software and more-rapid, dedicated hardware within a line card. Examples of operations reserved to hardware implementation can include blocking and unblocking of ports, flushing of learned entries from switch tables, and coordination of control-plane changes through the generation of messages sent between nodes, and also between line cards of a node. Determinations about the need for hardware-driven, control-plane changes may be made based on events occurring in the network in accordance with any of a number of different network protection protocols. The protocol may be implemented in a state machine and the software may determine the state of the hardware through a master/slave relationship.

Abstract: A Universal Serial Bus (USB) dock is provided. The USB dock includes: a plurality of downstream ports; and a upstream port, connecting the USB dock to a portable device, wherein the upstream port includes an On-the-go (OTG) ID pin and a differential pair; and a microcontroller, configured to detect operating states of the portable device, wherein when it is detected that the portable device is in a USB OTG host mode and has entered a suspend state, the microcontroller controls the portable device to switch from the USB OTG host mode to a USB device mode by toggling a state of the USB OTG ID pin, thereby charging the portable device via the upstream port.

Abstract: A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified interconnect network. Data may be communicated between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network, wherein the communications comprise a protocol that is common to all resource pools, and wherein each resource pool comprises a plurality of resource modules each configured to perform a common function. Further, a network interface controller (NIC) module may be configured to receive data from a plurality of processor modules via a unified interconnect network, and provide core network connectivity to the processor modules.

Abstract: A processor is configured to determine non-core functions to be performed by an unmanaged device disposed on a packet based computer network. A control message generator is configured to (i) generate a point-to-point control message conforming to a point-to-point control protocol for controlling the unmanaged device over a point-to-point serial bus connection to perform the determined non-core functions, and (ii) encapsulate the point-to-point control message in a transport packet for transport over the packet based computer network. A packet transmitter is configured to transmit the transport packet including the encapsulated point-to-point control message via a port coupled to the packet based computer network, the packet based computer network configured to route the transport packet including the encapsulated point-to-point control message based on a header included in the transport packet so that the point-to-point control message is received at the unmanaged device via the packet based computer network.

Abstract: The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Abstract: A PCI-E signal transmission apparatus and an image forming apparatus using the same are provided. The PCI-E signal transmission apparatus includes a controller board, and at least one unit board which is connected to the controller board through a differential signal transmission cable, which uses a PCI-E protocol, to transceive data. Therefore, it is possible to transmit a signal using an inexpensive cable at a high speed.

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Abstract: A system and a method for assigning virtual functions, and a management host thereof are provided. The management host is connected with a computer host through a bridge and has at least one virtual function. A management processor of the management host updates a mapping table according to a virtual function establishing request to assign the at least one virtual function to the computer host according to the mapping table, wherein the management processor determines whether to establish the virtual function according to the mapping table. The management processor transmits a hot-plug event to the corresponding computer host via a switch according to an assignment result and connects the virtual function with the corresponding computer host to dynamically adjust an allocation of the virtual function.

Abstract: Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined, as by concatenation, and conveyed to the memory controller as information of the specified granularity.

Abstract: Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to receive a first TLP from a RC or an EP and forward the first TLP to a reliable TLP transmission RTT module for processing. A reliable TLP transmission module is configured to determine, according to the received first TLP, sending links connected to active and standby PCIE switching units, and send the first TLP to the active and standby PCIE switching units through the sending links at the same time. A destination PCIE interface controller of the first TLP selectively receives the first TLP forwarded by the active and standby PCIE switching units and sends the first TLP to a destination EP or a destination RC. Thereby, reliable transmission of a TLP is implemented in a case of a PCIE switching dual-plane networking connection.

Abstract: Embodiments of the present invention provide a system and a method for transmitting data based on Peripheral Component Interconnect Express 9PCIe). The system includes: a PCIe switching network, multiple switch terminal devices, a managing unit, multiple host processing units, multiple terminal processing units, multiple hosts, and multiple terminal devices. After a PCIe data packet sent by a host is processed by a host processing unit, a new PCIe data packet that can be transmitted in a PCIe switch is constructed, and is transferred, by using a switch terminal device and a terminal processing unit, to a terminal device. The embodiments can break through a limitation about a single root node of PCIe and implement sharing of a PCIe switching network by multiple hosts.

Abstract: Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described.

Abstract: An interface identification system includes an IHS enclosure including a plurality of IHS slots and a plurality of input/output (I/O) switching module slots. A connection plane provides interconnects between the plurality of IHS slots and the plurality of I/O switching module slots. An I/O switching module includes a plurality of interfaces. The I/O switching module may be coupled to a first I/O switching module slot and, in response, retrieve first I/O switching module slot information about the first I/O switching module slot, retrieve IHS information about IHSs located in the plurality of IHS slots that are interconnected with the first I/O switching module slot through the connection plane, and use the first I/O switching module slot information and the IHS information to identify each of the plurality of interfaces on the I/O switching module that is coupled to an IHS by that IHS and the first I/O switching module slot.

Abstract: A circuit has a wordline with an NVM element utilizing a first FET coupled to bitline true and a second FET coupled to bitline complement. A NFET coupled to the bitline complement is configured to pull bitline true toward ground in response to bitline complement reaching a first voltage. One or more wordline drivers are coupled to the NVM element such that a first path from a wordline driver is coupled to the first FET while a second path from a wordline driver is coupled to the second FET. The first path is current-limited in comparison to the second path, such that a first slew rate between a wordline driver and the first FET is slower than a second slew rate between a wordline driver and the second FET. The slew rate disparity allows the bitline complement to reach the first voltage.

Abstract: The disclosure provides a motherboard including a north bridge chipset, a basic input output system (BIOS), a first video graphics array (VGA) connector, and a controlling module. The north bridge chipset outputs a sleep signal to the controlling module, the controlling module obtains a switch signal from the first VGA connector, the controlling module outputs a first mode signal to the north bridge chipset according to the sleep signal and the switch signal, the north bridge chipset controls the computer host to be asleep according to the sleep mode. The disclosure also provides a computer control system including the motherboard. The motherboard and the computer control system control the computer to be asleep via a display.

Abstract: An automotive electronic control unit receives rewrite data wirelessly transmitted in units of a predetermined size from an external device and rewrites data stored in a nonvolatile memory based on the rewrite data. At this time, the rewrite data is communicated by switching between broadcast communication and unicast communication, or between multicast communication and unicast communication.

Abstract: Embodiments include a method and computer program product for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router routes requests received over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.

Abstract: Certain implementations of the disclosed technology may include systems and method for handling application notifications. According to an example implementation, a method is provided. The method can include receiving a plurality of audio feeds from a respective plurality of applications, and determining a priority status for one or more of the respective applications. Based on the determined priority status, the method may further include determining a first prioritized audio feed and a second prioritized audio feed from the plurality of applications. The method includes detecting, in a signal associated with the first prioritized audio feed, a signal gap having a gap start. The method includes modifying, based at least in part on the signal of the first prioritized audio feed, one or more parameters associated with at least the second prioritized audio feed, and outputting, to an output device, at least a portion of the first prioritized audio feed.

Abstract: A real-time reconfigurable input/output interface of a controller and a method of reconfiguring the same. The reconfigurable interface enables the controller to communicate with a plurality of peripheral digital subsystem blocks, and includes an input/output interface, a profile memory, and a state machine. The input/output interface includes a plurality of data lines including a shared portion that are shared among the plurality of peripheral digital subsystem blocks. The profile memory stores a plurality of interface profiles, each interface profile defining a configuration of the input/output interface to communicate with an associated one of the peripheral blocks. The state machine is coupled to the profile memory to receive interface profiles and to the input/output interface. In response to each request to communicate with a particular peripheral block, the state machine configures the input/output interface according to the interface profile associated with the particular peripheral block.

Abstract: Data objects can be migrated, while live, to virtualized clustered storage arrays in an efficient manner to allow for efficient transition from non-clustered storage to the virtualized clustered storage arrays. A data migration specification indicates data objects to be migrated and parameters for the migration. The parameters include a source of a data object, a destination of the data object in the virtualized clustered storage arrays, and a transfer space. A migration engine validates and parses the data migration specification. For each unique association of source, destination, and transfer space, the migration engine instantiates a migration process that drives and monitors migration of the corresponding data object. The migration processes operate in parallel for migration of the specified data objects into the virtualized clustered storage arrays.

Abstract: A method of automatically configuring a data network, the data network including a controller and a virtualization host with a hypervisor installed thereon, the method including creating a virtual switch in the hypervisor and communicatively coupling the virtual switch to a first physical network interface in the virtualization host. Further, the method includes receiving a request to boot an operating system image in a virtual machine in the hypervisor, the operating system image having network connectivity requirements. The method also includes creating a first virtual port in the virtual switch based upon the network connectivity requirements of the operating system image and creating a first virtual network adapter in the virtual machine in the hypervisor. Further, the method includes communicatively coupling the first virtual network adapter to the first virtual port in the virtual switch and configuring networking attributes of the first virtual network adapter in the virtual machine.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Abstract: An IT device includes a system board and a riser card socket electrically coupled to the system board and configured to receive a riser card. At least one expansion card slot is electrically coupled to the system board and configured to receive at least one expansion card. A controller assembly is electrically coupled to the system board and configured to energize the at least one expansion card slot while the riser card socket is empty.

Abstract: Data processing and an accelerator system therefore are described. An embodiment relates generally to a data processing system. In such an embodiment, a bus and an accelerator are coupled to one another. The accelerator has an application function block. The application function block is to process data to provide processed data to storage. A network interface is coupled to obtain the processed data from the storage for transmission.

Abstract: A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system.

Abstract: A circuit for realigning data received at a receiver is disclosed. The circuit comprises a plurality of memory arrays; a plurality of multiplexers, wherein each multiplexer is coupled to select an address for data to be output by a memory array of the plurality of memory arrays; an output multiplexer coupled to select the outputs of the plurality of memory arrays; and a memory control circuit coupled to the plurality of multiplexers and the output multiplexer, the memory control circuit coupling select signals to the plurality of multiplexers and the output multiplexer to enable generating realigned data. A method of realigning data received at a receiver is also disclosed.

Abstract: The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

Abstract: Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port and processed to reassemble link packets and to calculate a CRC over the data received on each lane. The link packets include a transmitted CRC that is compared to a received CRC to detect link packet errors. Upon detection of a link packet error, per-lane or per transfer group CRC values are stored, and a retry request is issued to retransmit the bad packet. In conjunction with receipt of the retransmitted packet, per-lane or per transfer group CRC values are recalculated over the received data and compared with the stored per-lane or per transfer group CRC values to detect the lane causing the link packet error.

Abstract: A method and system to support multiple chains of authentication modules. The method may include receiving a user login request, and identifying multiple chains of authentication modules to be performed prior to allowing a user to login, where each chain of authentication modules is associated with a chain manager. The method further includes determining dependencies between chain managers, invoking the chain managers in the order defined by the dependencies, and responding to the user login request based on execution results of the authentication modules.

Abstract: An electronic apparatus includes a first communication unit configured to perform I2C bidirectional communication with an external apparatus using two signal lines included in a transmission path as I2C communication lines, a second communication unit configured to perform bidirectional differential communication with the external apparatus using the two signal lines as high-speed data communication lines, a switching unit configured to select a first communication state in which the first communication unit is connected to the two signal lines or a second communication state in which the second communication unit is connected to the two signal lines, and a controller configured to control operation of the switching unit.

Abstract: The system includes a PCI switch connecting a plurality of computers via a PCI interface; and a management server which controls assignment of PCI devices and computers connected to the PCI switch. The PCI switch reports an addition or change of a PCI device to the management server. The management server obtains basic information for the PCI device upon receipt of the report, determines an assignment state of the PCI device to either occupation or sharing, and instructs the PCI switch to assign the PCI device to the management server in the determined assignment state. The management server reads a driver of the PCI device connected through the PCI switch, and obtains detailed information of the PCI device through the driver.

Abstract: An information processing apparatus that detects an input operation to a touch panel based on an output of the touch panel; creates an operation command to change content displayed on a display apparatus based on a detected input operation to the touch panel; and controls a wireless interface to transmit the operation command to the display apparatus controlling the display apparatus to change the content displayed on the display apparatus.

Abstract: A method and apparatus adapted to prevent Head-Of-Line blocking by forwarding dummy packets to queues which have not received data for a predetermined period of time. This prevention of HOL may be on an input where data is forwarded to each of a number of FIFOs or an output where data is de-queued from FIFOs. The dummy packets may be provided with a time stamp derived from a recently queued or de-queued packet.

Abstract: A reconfigurable, scalable and flexible island-based network flow processor integrated circuit architecture includes a plurality of rectangular islands of identical shape and size. The islands are disposed in rows, and a configurable mesh command/push/pull data bus extends through all the islands. The integrated circuit includes first SerDes I/O blocks, an ingress MAC island that converts incoming symbols into packets, an ingress NBI island that analyzes packets and generates ingress packet descriptors, a microengine (ME) island that receives ingress packet descriptors and headers from the ingress NBI and analyzes the headers, a memory unit (MU) island that receives payloads from the ingress NBI and performs lookup operations and stores payloads, an egress NBI island that receives the header portions and the payload portions and egress descriptors and performs egress scheduling, and an egress MAC island that outputs packets to second SerDes I/O blocks.

Abstract: A method is provided for a destination storage system to handle SCSI-3 reservations. The method includes discovering a volume on a source storage system when the source storage system exports the volume to the destination storage system, exporting the volume to host computer systems, locally registering keys for first paths to the destination storage system, and registering with the source storage system the keys for second paths to the source storage system. When one of the host computer systems requests to reserve the volume, the method includes locally reserving the volume for paths to the destination storage system with registered keys and performing reservation forwarding to request the source storage system to reserve the volume for paths to the source storage system with registered keys.

Abstract: A system and method can support multiple domains in an InfiniBand (IB) fabric. The IB fabric can include one or more subnets, wherein each said subnet contains one or more switch nodes. Additionally, at least one said subnet can be divided into one or more sub-subnets, wherein each said sub-subnet is managed by a separate sub-subnet manager that is associated with a unique management key, and wherein said one or more sub-subnets are connected by one or more sub-subnet gateway switch nodes, wherein each sub-subnet gateway switch node belongs to one sub-subnet.

Abstract: An output switch fabric is disclosed that comprises an interleaved plurality of multiplexers for switching channels between first and second busses. The busses run in tracks that form a grid pattern. The interleaving of the multiplexers is arranged according to the grid pattern for the busses.