Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

Abstract: A file allocation system for a hard disk drive includes a memory with driver logic and a processor configured with the driver logic to receive a request to allocate hard disk space of a defined size for a buffer file. In some embodiments, the processor is configured with the driver logic to allocate clusters for the buffer file from a plurality of clusters on the hard disk, wherein the clusters for the buffer file store media content instances. In some embodiments, the processor is configured with the driver logic to designate a portion of the clusters of the buffer file for at least one non-buffer file such that the non-buffer file is permitted to share the portion of the clusters of the buffer file with the buffer file.

Abstract: A bus bridge for coupling between a first bus and a second bus includes: multiple ticket registers; a ticket dispenser counter; and a ticket call counter. The ticket dispenser counter dispenses a ticket value to a request received at the bridge from the first bus for access to the second bus. This ticket value is held in one ticket register of the multiple ticket registers. The ticket call counter provides ticket call values, and the request is granted access to the second bus when a current ticket call value equals the ticket value dispensed to the request. While the request waits for access to the second bus, the bus bridge can perform work on the request. When request coherency is maintained employing snooping, ticket values assigned to a plurality of requests maintain a snoop response ordering of the requests for access to the second bus.

Abstract: A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to retrieve captured data events from the data event buffer and to display the retrieved data events substantially in real time with respect to the occurrence of the corresponding captured data events on the nondeterministic data bus.

Abstract: A control packet management device of a packet forwarding system has a packet queue having a plurality of queues to store a control packet as transmitted, a first processor to transmit said control packet stored in one queue of said plurality of queues to a host a by one-to-one interrupt, a second processor to divide said control packets stored in said one queue into groups of a predetermined size and transmit said control packets to said host in the group unit and by direct memory access (DMA), a third processor to discard a most common type of said control packets stored in said one queue, and a controller to control said first, second and third processors to selectively operate in accordance with an accumulation state of said control packets stored in said plurality of queues.

Abstract: A signal router routes N inputs to M outputs. All inputs signals are ultimately applied to a data buss by spreading across multiple buss lines and time multiplexing. The data are read from the buss and written in identical images to K random access memories. The memories are addressed and read according to a different schedule for each of K output signals that are ultimately demultiplexed to M outputs. As each RAM image is read, another RAM image is written and vice versa. Since each RAM image contains the same data, the generation of signals from each RAM to supply each of the respective K output signals can be done at a rate that is substantially more independent of the input, buss, or RAM write operations than prior art techniques permit.

Abstract: A data transferring apparatus has an ASIC (Application Specific Integrated Circuit), and the ASIC incorporates an interface unit, a head controlling unit, a receiving buffer unit and a DECU, which are coupled to be capable of transferring data. The DECU incorporates a development processing controller having a decode circuit for performing hardware development on compressed recording data, and a line buffer storing developed recording data. The DECU and the head controlling unit are coupled by an internal bus IB in order to perform data transfer.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: In one embodiment, a trace buffer circuit for use with a pipelined digital signal processor (DSP) may include a series of interconnected registers that operate as a first-in first-out (FIFO) register on a write operation and a last-in first-out (LIFO) register on a read operation. On the write operation, a branch target/source address pair may be written to a first pair of trace buffer registers and, the contents of each register may be shifted two registers downstream. On the read operation, one instruction address may be read from a top register, and the contents of each register may be shifted one register upstream. The trace buffer may also include structure to enable compression of hardware and software loops in the program flow. A valid bit may be assigned to each instruction address in the trace buffer and a valid bit buffer with a structure parallel to that of the trace buffer may be provided to track the valid bits.

Abstract: A service processor for a server system includes an event log that, once full, stores recent events by overwriting events of intermediate age so that the information required to diagnose both cascade errors and hangs are preserved. This contrasts with bottom-up buffers that discard recent events when full and with circular buffers that discard the oldest events when full. The event log can be reset by moving an exception region, that is, a region that is not overwritten by recent events. Alternatively, a partial reset can initialize an exception region (e.g., a bottom-up sublog), while a circular region or sublog continues to operate without being reset.

Abstract: In summary, one aspect of the present invention is directed to a method for a shared memory queue to support communicating between computer processes, such as an enqueuing process and a dequeuing process. A buffer may be allocated including at least one element having a data field and a reserve field, a head pointer and a tail pointer. The enqueuing process may enqueue a communication into the buffer using mutual exclusive access to the element identified by the head pointer. The dequeuing process may dequeue a communication from the buffer using mutual exclusive access to the element identified by the tail pointer. Mutual exclusive access to said head pointer and tail pointer is not required. A system and computer program for a shared memory queue are also disclosed.

Abstract: A separate-type music performance system has a master audio-visual station and a slave audio-visual station remote from the mater audio-visual station and connected through two communication channel independently of each other; MIDI music data codes and click time data codes are transmitted through one of the communication channels to the slave audio-visual station, and audio-visual data codes and a click signal are transmitted through the other communication channel; when the click signal and click time data code arrive the slave audio-visual station, the clock setter 21e sets an internal clock with the click time data code paired with the click signal, and the MIDI music data code are transferred to an automatic player piano in comparison with the time data and the internal clock, whereby the tones are produced synchronously with the visual images.

Abstract: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.

Abstract: Systems and methods for maintaining cache coherency between a first controller and a redundant peer controller while reducing communication overhead processing involved in the coherency message exchange. Header or meta-data information is accumulated in a buffer in a first controller along with updated cache data (if any) and forwarded to the peer controller. The accumulating information may be double buffered so that a buffer is filling as a previously filled buffer is transmitting to the peer controller. The peer controller processes the received information to update its mirror cache to maintain coherency with the first controller's cache memory with respect to dirty data. The method and systems avoid the need to update cache coherency in response to every flush operation performed within the first controller to thereby improve overall system performance.

Abstract: A method of controlling an industrial process by a programmable process control has the steps of taking data in form of resulting values which are decisive for the process, storing the data in a storage of a programmable process control, during starting a control program reading pre-defined configuration data which are stored in a storage in the control and connected with a control program, based on the configuration data selecting a subset of the resulting values adapted to a resulting value storage available in the control, and subsequently storing it in this storage.

Abstract: An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.

Abstract: According to some embodiments, a ping-pong buffer system has a buffer that stores a subset of data from a data source.

Abstract: A memory device is so adapted that data processing time is not prolonged even when there is little bus width. A DRAM is connected to first to third buffer circuits by buses, which have a bus width of 128 bits, via a selector. The first to third buffer circuits are connected to a circuit such as a signal processing circuit by buses having a bit width of 32 bits. Since part of the circuitry is connected by buses having a bit width of 32 bits, the wiring is simple. By executing various processing in parallel, it is possible to prevent prolongation of the time required to record image data on a memory card.

Abstract: To efficiently transfer data from a host computer to a printer, a part of data developed in the first memory is outputted on the basis of a draw command to the printer, the data remaining in the first memory is stored in the second memory after the data was outputted, and a part of the data stored in the second memory is outputted to the printer when the data is being developed in the first memory on the basis of the draw command.

Abstract: A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein the first read latch signal does not change the pointer location of the read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.

Abstract: A data handling device comprising a communication controller, having a data gate provided for receiving and transmitting data, said communication controller being connected to a processor having an n-bits addressing capacity and to a memory having a set of buffers comprising a first subset provided for storing data segments retrieved from said data and which buffers of said first subset are accessible under control of said processor by a buffer address indicating a buffer location in said memory and generated by using a buffer descriptor stored in a buffer descriptor list, said memory having a second subset of buffers which are not accessible by said addressing capacity. Said buffers of said second subset being addressable by using further buffer descriptors stored in said buffer descriptor list. Said processor comprising driving means for managing the transfer of data segments between the buffers of the first and second subset.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. In one embodiment a non-volatile synchronous memory device includes an array of memory cells arranged in a plurality of addressable banks. A bank buffer circuit is coupled to each of the banks. Each of the buffers can store data from a row of memory cells contained in a corresponding bank. A method of operating a synchronous flash memory includes storing instruction code in each array block and copying the instruction code from a first array block to a buffer circuit, during a write operation, so that the instruction code can be read from the buffer circuit during the write operation.

Abstract: A system and method for distributing a portion of the processing of a received packet among a plurality of service threads. When an ISR or similar process retrieves a packet from a communication interface via a receive descriptor ring, it places the packet on one of a plurality of service queues. Each queue has an associated service thread or process that initiates upper layer protocol processing for queued packets. The ISR may select a particular service queue based on the packet's communication flow or connection. Alternatively, the ISR may use a processor identifier provided by the communication interface to select a queue (e.g., in a multi-processor computer system). Or, other information provided by the interface may be used.

Abstract: Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and the number of occupied pipelines.

Abstract: An inverse-modified discrete cosine transform and overlap-add method, and hardware structure for MPEG Layer3 audio signal decoding. In order to have the MPEG Layer3 audio signal decoder have more competitive power in the consumer market, the present invention provides a low cost fast algorithm of the inverse-modified discrete cosine transform and overlap-add, so that the quantity of the operation needed in the decoding process can be significantly reduced to enhance the system performance. Afterwards, according to the fast algorithm, the present invention provides a hardware structure that is suitable for the inverse-modified discrete cosine transform and overlap-add in the MPEG Layer3 decoder. Since the hardware structure of the present invention makes the MPEG Layer3 decoder able to be implemented by the application specific integrated circuit (ASIC), the entire system can fulfill the low cost and high performance requirements.

Abstract: A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. Also provided is a data packet format for transferring data, which comprises of an Endpoint Transfer Descriptor (“ETD”) that includes an EndPoint Descriptor and a Transfer Descriptor, wherein the host system programs the parameters of a communication channel for a particular Endpoint. Also included is a technique for partitioning a memory storage device into a first memory buffer and a second memory buffer; wherein the size of the first and second memory buffer may be programmed by the host system and the first and/or second memory buffer may contain more than one USB packet.

Abstract: Provided are a computer implemented method, system, and program for accessing information on a device. A first and second buffers are generated in a computer readable medium. The first buffer is indicated as a read buffer. Property values are returned from the buffer indicated as the read buffer in response to requests for property values for the device. The second buffer is indicated as a refresh buffer. Updates to the property values accessed from the device are written to the buffer indicated as the refresh buffer.

Abstract: An LCD controller (10) has a DMA unit (18) and a FIFO memory (20) for storing display data. The LCD controller also has a display data generator (26) that generates display information using a line of the display data stored in the FIFO memory in accordance with a predefined algorithm. A holding register (28) is connected to the display data generator and stores the generated display information. A multiplexer (34) selects for display either the data stored in the FIFO memory or the generated display information. The generated display information is selected when there is a bus overload indicating that the data stored in the FIFO may be erroneous.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.

Abstract: A refetch logic propagates data from a first source to a link controller by default. The link controller prefetches data from the refetch logic to generate a first packet prior to receiving control of the transmission medium on which the data is to be transmitted. The refetch logic changes sources and propagates to the link controller data from a second source if necessary. At the same time, the refetch logic also causes the link controller to discard the first packet and generate a second packet from data provided by the second source.

Abstract: A disk input/output (I/O) system includes a controller, a cache, a disk I/O subsystem, and a command queue. The load on the queue is monitored and when it reaches a threshold, commands are designated cache only. Cache only commands are added to the queue only if they can be completed without accessing the disk I/O subsystem. If the disk I/O subsystem would be accessed in order to complete a cache only command, the command is returned to the operating system with an error. The operating system can then add the command to an operating system or back-up queue.

Abstract: A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.

Abstract: The present invention focuses on the aggregation of flows belonging to different classes of non-guaranteed-delay traffic into a single FIFO queue in a downstream stage of the multi-stage switch. These include the guaranteed flows requiring bandwidth reservation, the best-effort flows that require a fair share of the excess bandwidth, and the flows that require both types of guarantee. We disclose a credit-based backpressure scheme which selectively controls the traffic originating from the previous stage of the system while achieving the goal of meeting the requirements of the individual flows. The credit function is maintained for each controlled traffic component in the aggregate session, and its objective is to balance the actual arrival rate of the component with the service rate dynamically granted by the downstream scheduler. The number of flows that can be aggregated is related to the complexity of maintaining the credit functions for the different traffic components.

Abstract: A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packet sizes and another portion is for larger packet sizes, although other portions may be created. As packets are received at the network device, they are stored into the appropriate memory portion based on their size. The number of available buffers in each portion is monitored so that, when it falls below a threshold, buffers are reallocated to the other thereby increasing the overall memory efficiency.

Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.

Abstract: The present invention provides method, data transfer controller and system for asynchronously transferring data. The method allows to provide a buffer device. The method further allows to define in the buffer device a plurality of buffer segments. Respective ones of the buffer segments are filled with data from at least one data source device operating in a respective clock domain. Upon any respective buffer segment being filled up, the method allows to generate an indication of availability of the contents of the respective buffer segment to at least one data destination device operating in a respective clock domain. The clock domain of the at least one source device is distinct than the clock domain of the at least one destination device.

Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.

Abstract: A method and apparatus optimizes the speed and efficiency of data transfer between two devices having different data input/output rates. In one embodiment, the present invention is directed to a computer software driver or hardware apparatus that may work with any port and/or network. The driver has a calibrator portion for optimizing data transfer between a CPU and a peripheral. The calibrator portion includes a data input/output rate profiler. The profiler preferably sends run-time data samples to the peripheral, builds a table that relates each data sample to an aggregate data transfer rate, and selects the optimum result as a model for further data transfer. A preferred method for performing the present invention is also included.

Abstract: The present invention provides a method of transferring incoming multithreaded concurrent sets of data from a sending transport system to a requesting transport system which includes retrieving the sets of data from the sending transport system. A receiving queue is queried for a number of available data storage locations, and the sets of data being transferred to the receiving queue. The method further includes queuing the sets of data in the receiving queue, where each the set of data are divided into blocks of data. Then, determining a number of the data storage locations for storing the blocks of data. Next, the blocks of data are loaded into available data storage locations, and location indexes are provided for each of the blocks of data where the location indexes associate the block of data with a corresponding the storage location.

Abstract: The data storage system 1 comprises tape drives 21 to 23 operable to read and write data transmitted via the SCSI bus 112 from and on a tape in parallel and a host PC 4 for controlling data transmission to the SCSI bus. The host PC 4 includes a data access control unit 41 operable to calculate a bus reconnect timing that makes it possible to avoid stopping tape writing or reading even when any one of the respective drive drives 21 to 23 waits for the time when the other tape drives finish data transmitting after it reaches a bus reconnect timing based on the tape drive information “(the number of drive units, a data transmission speed of the bus, either a data reading speeds of the respective drive units or a data writing speeds of the respective drive units)=(m, S and R)”.

Abstract: The method and apparatus presented are targeted to improve the performance of moving data between memory portions connected by a system bus where writes have higher performance than reads, such as the PCI bus. Due to the PCI bus design, read requests from memories connected across the PCI bus take a significantly longer time to complete than performing a write operation under the same circumstances. The present invention uses the faster write operations across the PCI bus, and queue management techniques, to take advantage of the relative speed of writes in a PCI system. The overall result is significant performance enhancement, which is especially useful in service aware networks (SAN) where operation at wired-speed is of paramount importance.

Abstract: System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Abstract: A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of “1” is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of “0” (zero) is shifted from a second end of the shift register, indicating that one more space is available.

Abstract: A system and method for compensating for differences between a recovered receive clock and an internal transmit clock in an elastic buffer and thereby preventing corruption of data. In one embodiment, the system comprises a circularly accessed buffer coupled to read and write logic. The read and write logic read and write to locations within the circular buffer as indicated by respective read and write pointers. The system further comprises control logic which compares the pointers to determine whether the buffer is approaching an underflow or overflow condition and adds or deletes fill words between frames of data to compensate for the underflow or overflow condition. In one embodiment, the system includes fill word logic which is configured to add a fill word bit to each received word and to set or clear the fill word bit to indicate whether or not the corresponding word is a fill word.

Abstract: A method for providing efficient use of a transmit engine in transmitting packet directing information. In one embodiment, two linked lists are used to submit packets and packet directing information to a transmit engine. When there is no packet to send, both lists are marked as free. When software desires to send a packet to hardware, the packet is placed on the first linked list. Software marks the first linked list as busy. If the transmit engine is not busy with the second linked list, software will start the transmit engine utilizing the first linked list. While the first linked list is marked as busy, all additional packets are directed to the second linked list. When the packets of the first linked list have been sent, software marks the first linked list as free.

Abstract: A system and method is disclosed for providing a pre-fetch memory controller in a computer system that comprises a plurality of master agents. The memory controller comprises a bus interface, a memory interface and a plurality of pre-fetch queues. In one embodiment each pre-fetch queue is assigned to a master agent. In an alternate embodiment the pre-fetch queues are dynamically assigned to master agents. The bus interface services memory read requests, memory write requests, and pre-fetch requests. Data may be pre-fetched from main memory and stored in the pre-fetch queues. This reduces the latency for memory read requests and improves the efficiency of the memory interface with the main memory.

Abstract: The invention relates to a method and apparatus for transmitting data packets over a channel wherein the data packets have compressed headers. After compressing a header using a context, a number of consecutive update packets are transmitted, each containing data indicating the context. According to the invention, the channel quality is determined and the number of update packets is set accordingly. The channel quality may be determined by measuring the block error rate or the signal-to-noise ratio. Alternatively, the channel quality may be estimated by evaluating whether a NACK message has been received. The total number of update and non-update packets transmitted during a context update phase may be set according to the Round Trip Time. The number of non-update packets may further be determined based on codec properties. The invention may advantageously be used over unreliable, e.g. wireless, channels.

Abstract: Subject matter to regulate real-time data capture rates to match processor-bounded data consumption operations is described. In one aspect, a first transition time for a data source to transition from a first mode to a second mode is determined. A second transition time for the data source to change from the second mode to the first mode is also identified. Based on the first and second transition times, the data source is directed to transition into respective ones of the first and second modes such that real-time capture of data from the data source is regulated by a computing device to match processor-bound data consumption rates of an application consuming the data.

Abstract: A system and method autonomically reallocate memory among buffer pools to permit quick access to data. A simulated buffer pool extension (SBPX) is created for each buffer pool in a set of buffer pools. Data victimized from a buffer pool is represented in the associated SBPX. Requests for data that is not resident in a buffer pool but is represented in the associated SBPX are tallied. Periodically, an expected efficiency benefit of increasing the capacity of each buffer pool is determined from the tallies. Memory is reallocated from the buffer pool with the lowest expected efficiency benefit having remaining reallocatable memory to the buffer pool with the highest expected efficiency benefit having remaining reallocatable memory, until either one or both of the buffer pools exhausts its reallocatable memory.

Abstract: Embodiments are provided in which a method is described for transferring data in a digital system including a first bus, a second bus, a PCI-X bridge coupling the first and second buses, and a first device and a second device residing on the first and second buses, respectively. The first bus has the same or higher bandwidth than that of the second bus. According to the method, the PCI-X bridge immediately starts or resumes forwarding split completion data from the first device to the second device if the first device starts or resumes split completion data transfer to the PCI-X bridge at the beginning of a block (i.e., the start or resume byte address has the form of 128N). If the first device starts transfer to the PCI-X bridge not at the beginning of a block, the PCI-X bridge refrains from forwarding split completion data until (a) the first device sends the data byte at the beginning of the next block to the PCI-X bridge or (b) the byte transfer count is exhausted, whichever occurs first.