Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank and writing a second plurality of data words and associated memory addresses into an error buffer. The method also comprises monitoring a first counter value which tracks a number of write 1 errors and a second counter value which tracks a number of write 0 errors in the memory bank. Further, the method comprises determining if the first counter value and the second counter value have exceeded a predetermined threshold. Responsive to a determination that the first counter value has exceeded the predetermined threshold increasing a write 1 voltage of the memory bank, and, further, responsive to a determination that the second counter value has exceeded the predetermined threshold increasing a write 0 voltage of the memory bank.

Abstract: A system comprising a memory component including blocks, and a processing device, operatively coupled with the memory component. The processing device determines endurance values for the memory component. For each selected block of the plurality of blocks, the processing device determines an endurance estimation of the selected block based on at least one of a time to erase the selected block or an error statistic for the selected block, and updates an endurance value associated with the selected block based on the endurance estimation for the selected block. The processing device receives a write instruction to the memory component and distributes the write instruction to one or more of the blocks based on the endurance values. Other embodiments are described.

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.

Abstract: One example method includes receiving a write request that includes a data structure version to be written, wherein the data structure version is associated with a unique identifier, storing the data structure version in association with the unique identifier, receiving a read request for a most recent version of the data structure and, when the stored data structure version is not the most recent version of the data structure, examining respective unique identifiers of each of a group of other stored data structure versions to determine which stored data structure version is the most recent. Finally, the example method includes returning the most recent data structure version, notwithstanding that one or more other data structure versions existed at the time that the read request was received.

Abstract: An in-line (or foreground) approach to obtaining contiguous ranges of free space in a file system of a data storage system that can select windows having blocks suitable for relocation at a time when one or more blocks within the respective windows are freed or de-allocated. By providing the in-line or foreground approach to obtaining contiguous ranges of free space in a file system, a more efficient determination of windows having blocks suitable for relocation can be achieved, thereby conserving processing resources of the data storage system.

Abstract: In general, embodiments of the technology relate to a method and system for storing and reading data from persistent storage. More specifically, embodiments of the technology relate to a method and system for storing data in persistent storage, where the data written to the persistent storage is not immediately accessible in the persistent storage (i.e., during the inaccessibility period). In such instances, embodiments of the technology provide a method and system to enable the storage system to service read requests for the data using a primary cache entry table (PCET) and an overflow table.

Abstract: A computer comprises a controller and a storage apparatus which is configured to provide a storage area for storing data. The controller and the storage apparatus have a function of achieving encryption and decryption of data through use of an encryption key. The computer is configured to: execute encryption key setting processing for setting the encryption key in the controller and the storage apparatus so that the controller holds the same encryption key as the encryption key of the storage apparatus; and determine whether to enable the function of any one of the controller and the storage apparatus, based on load states of the controller and the storage apparatus when an I/O request is received.

Abstract: The present invention is a system and method of making setpoint adjustments to a vehicle control computer in a real time manner in order to enable the one performing the programming to observe the changes in vehicle characteristics in real time. The system and method is an improvement over known methods in that it does not require the programmer to repeatedly stop and start the operation of the vehicle in order to verify that any changes have the desired result.

Abstract: In some examples, a fluidic die includes a plurality of fluid actuators, and a controller to determine, based on input control information relating to controlling actuation of the plurality of fluid actuators, whether a first fluid actuator of the plurality of fluid actuators is to be actuated, and in response to determining that the first fluid actuator is to be actuated, activate a delay element associated with the first fluid actuator, the delay element to delay an activation signal propagated to selected fluid actuators of the plurality of fluid actuators in response to an actuation event.

Abstract: Systems and methods for deleting backup pieces associated with an application such as a database application. Backup pieces are identified and deleted from the database records and from the backup application.

Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: Apparatuses and methods related to generating memory characteristic based access commands generating the access commands can include providing a first access command to a memory system of a plurality of memory systems, receiving, at a host coupled to the memory system, data corresponding to characteristics of a memory device of the memory system from a controller of the memory system, where the characteristics are based at least in part on processing of the first access command. Generating access commands can also include generating, at the host, a second access command based on the data and transmitting the second access command to at least the memory system.

Abstract: The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: A method for implementing pulse-amplitude modulation on a memory device includes configuring a first resistor of a first memory die to a first resistance value. The method also includes configuring a second resistor of a second memory die to a second resistance value. The method also includes receiving, during performance of a read operation, in parallel: two voltage values from the first memory die; and two voltage values from the second memory die. The method also includes determining a first data bit value using the two voltage values from the first memory die. The method also includes determining a second data bit value using the two voltage values from the second memory die.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if an access request (e.g., a read or write request) to a memory location would result in an integrity failure and, if so determined, read previous data from the memory location, set an indicator to indicate the integrity failure, and store the previous data together with the indicator and previous authentication information. Other embodiments are disclosed and claimed.

Abstract: A method for identifying a boot stage of a BIOS of a computer device is provided. A control terminal receives screen information data indicative of a current BIOS screen image of the computer device, acquires current screen information based on the screen information data, acquires feature vector based on the current screen information, uses an image classification model to classify the current information into a screen category, and generates boot stage information indicative of a boot stage corresponding to the screen category.

Abstract: Apparatus and method for hashing a message, comprises using an array of individually selectable memristor cells. The memristor cells are subject to write disturb that affects cells neighboring a selected cell so that a write operation into one cell has a knock-on effect on the neighbors. The array is initiated into a known stable state so that these changes to neighboring cells are predictable according to proximity to the currently selected cell. An inserter sequentially mixes bits with the hash so far to insert bits into successively selected cells of the memristor array and forms a succession of memristor array states including the knock on effects on the neighboring cells. A final resulting memristor array state following input of the bits forms the hash of the message.

Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.

Abstract: A computer-implemented method according to one embodiment includes identifying code word interleaved (CWI)-4 entries to be re-written to a data storage cartridge, selecting a subset of the CWI-4 entries to be included within a first CWI-4 set, where a plurality of the CWI-4 entries within the subset are associated with a single sub data set (SDS), and re-writing the first CWI-4 set to the data storage cartridge.

Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.

Abstract: According to one embodiment, a non-volatile first memory includes a plurality of first storage areas. A second memory stores a plurality of first addresses each is address information of a second storage area. The second storage area is a first storage area in a first state. A third memory stores a counted value for the second storage area. A determiner circuit reads, at a time of a read access to the first memory, at least one of the first addresses and compares the read second address with a third address to determine whether a third storage area is in the first state. The third address indicates a location of the third storage area. The third storage area is a first storage area to be read. An update circuit increments, for the third storage area, the counted value, when the third storage area is in the first state.

Abstract: One or more write operations are performed on a memory component. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds a threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

Abstract: A system for a nonvolatile memory for broad temperature range applications. The system includes a memory organized into an addressable memory range and comprising a plurality of memory arrays comprising memory cells wherein each memory array is configured for operation over a different temperature range, and a buffer for receiving a data word and an associated address for writing into the memory. A temperature sensor is used for sensing a current temperature of operation of the memory. A write controller is coupled to the buffer, the temperature sensor and the memory. The write controller is operable to perform a write operation that includes accessing a temperature value from the temperature sensor, selecting a selected memory array of the plurality of memory arrays that is configured for operation at the temperature value, and writing the data word, at the associated address, to the selected memory array.

Abstract: Common microcontroller unit (MCU) self-identification information is disclosed. In one embodiment, an MCU is contained in a package. The MCU includes a central processing unit (CPU) and a non-volatile memory. This non-volatile memory stores information specific to the MCU and/or the package. The non-volatile memory also stores a common main program that, when executed by the CPU, accesses the information. The information enables the common main program to adapt itself to resources of the MCU and/or package that are identified in the information.

Abstract: A computer implemented method comprises detecting a failure of a primary volume at a first location, the primary volume having data stored on a first plurality of media according to a first heat map; in response to detecting the failure of the primary volume, overwriting a second heat map of a secondary volume at a second location with a copy of the first heat map, the secondary volume having data stored on a second plurality of media according to the second heat map; migrating extents of data on the second plurality of media at the second location according to the copy of the first heat map prior to a next heat map cycle update after detection of the failure; and processing data access requests from the secondary location using the extents of data on the secondary plurality of media migrated according to the copy of the first heat map.

Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.

Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.

Abstract: A computer implemented method includes receiving multiple requests to update a data structure stored in non-volatile memory (NVM) and applying an atomic multiword update to the data structure to arbitrate access to the NVM. In a further embodiment, a computer implemented method includes allocating a descriptor for a persistent multi-word compare-and-swap operation (PMwCAS), specifying targeted addresses of words to be modified, returning an error if one of the targeted addresses contains a value not equal to a corresponding compare value, executing the operation atomically if the targeted addresses contain values that match the corresponding compare values, and aborting the operation responsive to the returned error.

Abstract: Augmenting data files in a repository of an append-only file system includes maintaining a companion metadata file for each corresponding data file in a map-reduce system using the append-only file system. Each companion metadata file tracks a logical end-of-file (EOF) for each data file. Global versioning of each companion metadata is maintained. A map-reduce append job is performed for a set of data files using a current global version number for the companion metadata file. The map-reduce job including multiple append tasks. For each successful append job, a logical EOF for each appended file is incremented to a new physical EOF. For each failed append task of the append job, a logical EOF is maintained for each failed append task by not incrementing the logical EOF for each failed append task.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory, and a controller. The controller associates a first number of consecutive logical addresses with the first number of physical addresses which are included in a second number of consecutive physical addresses of the first memory. The controller executes a first updating and a second updating. The first updating includes associating a first physical address among the second number of physical addresses with a first logical address. The second updating includes obtaining a second logical address which is away from the first logical address by a value corresponding to distance information on the basis of origin information and the distance information and associating, with the second logical address, a second physical address which had been associated with the first logical address before the first updating is executed.

Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.

Abstract: A method for reducing power consumption of a memory of a computer device is presented. The memory includes at least two channels, each channel includes at least two storage units, a dirty data storage area is set in the memory, and the dirty data storage area includes at least one storage unit in each channel. After the computer device encounters a power failure, a backup power supply is turned on to supply power to the memory, then the storage unit included in the dirty data storage area is kept in a normal operating state, and a storage unit outside the dirty data storage area in the memory is caused to enter a self-refreshing state. Data in the dirty data storage area is then written to a non-volatile storage area of the computer device.

Abstract: Examples may include techniques to monitor processing of I/O requests of an application being executed by a computing platform by collecting a trace of the I/O requests, the trace including an I/O class of each I/O request; replay the trace and automatically analyze possible cache configuration policies for using a cache during execution of the application by the computing platform; and determine an optimal cache configuration policy for the cache from the possible cache configuration policies. The optimal cache configuration policy may then be applied to use of the cache during subsequent execution of the application by the computing platform.

Abstract: A data storage device coupled to a host device via a predetermined interface includes a memory device, an SRAM, and a controller. The controller is coupled to the memory device and the SRAM. The controller receives a first power mode change request packet requesting to change the data transfer speed of the predetermined interface from a first speed to a second speed via the predetermined interface from the host device, and in response to the first power mode change request packet, the controller determines whether the operation status of the data storage device is busy. When the operation status of the data storage device is busy, the controller determines to reject the request to change the data transfer speed and keeps the data transfer speed at the first speed and does not change the data transfer speed to the second speed.

Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.

Abstract: An example method and an example apparatus for writing data into a cache are described herein. The example method includes receiving an IO request write command, where the IO request write command includes metadata of to-be-written data. A first buddy group is obtained from a global buddy queue, and a determination as to whether all metadata of the to-be-written data can be written into the first buddy group is made. If the determination is yes, all the metadata of the to-be-written data is written into the first buddy group, and all the metadata of the to-be-written data is written into a metadata block corresponding to a metadata group to which the first buddy group belongs.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device maintain memory ranking information for a set of storage units (SUs) and receives a read data request. The computing device selects a decode threshold number and/or a read threshold number of SUs to service the read data request based on the memory ranking information. The computing device recovers the data segment and transmits a read data response that is based on the processing the read data request.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a prognostic agent embodied in a program of executable instructions and configured to, when executed, maintain a prognostic data structure setting forth a plurality of parameters regarding a non-volatile memory of the information handling system, and a memory controller configured. The memory controller may be configured to calculate a severity index based on the parameters set forth in the prognostic data structure, the severity index indicative of a likelihood of successfully completing a save operation to the non-volatile memory from a volatile memory in response to a power event of the information handling system and based on the severity index, determine whether or not to perform a save operating in response to a power event of the information handling system.

Abstract: A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the M3 and M4 metal layers of the memory device.

Abstract: Various examples of the present invention relate to an electronic device data recording method and an electronic device thereof, and an electronic device operating method can comprise the steps of: determining a data recording possibility of a specific area of a nonvolatile memory in which data is to be recorded; and determining whether to record data based on the data recording possibility. In addition, the various examples of the present invention also include the aforementioned example and other examples.

Abstract: Performance tuning in a storage system that includes one or more storage devices, including: storing, by a primary controller of the storage system, data corresponding to one or more computer processes into one or more of the one or more storage devices, determining, by a secondary controller that is configured similarly to the primary controller, one or more utilization patterns of the data, and initiating, in dependence upon the one or more utilization patterns of the data, a modification to a manner in which the one or more computer processes access the data stored in the one or more storage devices.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: A computer-implemented method executed on one or more processors is provided for processing a query for a NoSQL (non-structured query language) database. The computer-implemented method includes periodically monitoring active transactions that started and are committing dirty versions before a specific time, sending a query to fetch a state of the active transactions, and receiving a query result. The computer-implemented method further includes, if the query result includes active transactions, performing a normal query that scans dirty and committed versions. The computer-implemented method further includes, if the query result includes no active transactions, due to a time window indicating a specified staleness, sending a simplified query that scans only committed versions.

Abstract: A system management controller with a consolidated memory is disclosed. The example computing device includes a processor to host an operating system and a system memory to be used by the processor to execute instructions. The computing device also includes a management controller to enable out-of-band management of the computing device. The management controller includes a consolidated memory device. A first memory block of the consolidated memory device is used by the management controller as a working memory and a second memory block of the consolidated memory device is used for long-term storage of programming instructions.

Abstract: Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.

Abstract: Example implementations relate to backup power supply support. For example, a backup power supply support system can include a shared backup power supply controlled by a backup power control module and a support switch coupled to the shared backup power supply. The support switch enables a transition from a primary power supply to the shared backup power supply and the support switch includes system firmware. The system firmware detects a primary power supply compromise, isolates a hardware switch from the shared backup power supply, enables the hardware switch, and transitions to the shared backup power supply.

Abstract: A linked-list-based method for application caching management is disclosed, the method including: when receiving application cached data, creating a node in a linked list for the cached data and obtaining a memory size of the cached data; obtaining a maximum memory size and a currently occupied memory size of the linked list; adding the memory size of the received cached data to the currently occupied memory size of the linked list to obtain a first memory size; and adding the node to the linked list if the first memory size is smaller than or equal to the maximum memory size. A linked-list-based device for application caching management is also provided.

Abstract: A management device according to an embodiment manages reading and writing of data, by a processing circuit, from and into a first memory unit and a non-volatile memory unit containing a plurality of pages, and includes a setting storage unit, an access processing circuit, and a management circuit. The setting storage unit stores an access method indicating whether first access processing of writing and reading data into and from data transferred to the first memory unit from the non-volatile memory unit or second access processing of directly writing and reading data into and from data stored in the non-volatile memory unit is executed for each of the pages. The management circuit changes the access method for a third page on which the second access processing is set to be performed to the first access processing when quality of the third page is equal to or lower than a reference value.