Abstract: Preventing out of legacy option ROM space errors in a computing system, including: iteratively for each option ROM in the computing system: loading, into an option ROM memory, the option ROM; executing, from the option ROM memory, the option ROM; and removing, from the option ROM memory, the option ROM.

Abstract: Disclosed herein are a buffer cache apparatus, a journaling file system, and a journaling method capable of incorporating journaling features based on nonvolatile memory. The buffer cache apparatus provides a data buffering function between a central processing unit (CPU) and storage. The buffer cache apparatus includes a plurality of cache blocks and a journal management unit. The plurality of cache blocks are configured as volatile or nonvolatile memory devices. The journal management unit maintains states of freezing for write-protecting dirty up-to-date cache blocks among the plurality of cache blocks.

Abstract: According to an embodiment, a multi-core processor is capable of executing a plurality of tasks. The multi-core processor includes at least a first core and a second core. The first core and the second core are capable of accessing a shared memory area. The first core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the first core. The second core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the second core. The local memory for the first core and the local memory for the second core include memories with different unit cell configurations in at least one identical memory layer.

Abstract: A system and method are described for intelligently flushing data from a processor cache. For example, a system according to one embodiment of the invention comprises: a processor having a cache from which data is flushed, the data associated with a particular system address range; and a PCM memory controller for managing access to data stored in a PCM memory device corresponding to the particular system address range; the processor determining whether memory flush hints are enabled for the specified system address range, wherein if memory flush hints are enabled for the specified system address range then the processor sending a memory flush hint to a PCM memory controller of the PCM memory device and wherein the PCM memory controller uses the memory flush hint to determine whether to save the flushed data to the PCM memory device.

Abstract: Preventing out of legacy option ROM space errors in a computing system, including: iteratively for each option ROM in the computing system: loading, into an option ROM memory, the option ROM; executing, from the option ROM memory, the option ROM; and removing, from the option ROM memory, the option ROM.

Abstract: A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data from the hard disk drive, the control circuit first determines if the requested read data are stored in the non-volatile memory. If so, the requested read data are provided from the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. The volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.

Abstract: A machine and method to manage BIOS images.

Abstract: According to one embodiment, a memory system includes a memory and a controller configured to control the memory. The memory includes a semiconductor memory region in which data rewrite is executed by an instruction of the controller, a timing determination module configured to derive a command input timing to the memory, based on the instruction and a clock which are received from the controller, and a status register configured to store the command input timing to the memory, which is derived by the timing determination module.

Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Abstract: A system is provided that includes a remote device and bus controller coupled to the remote device via a digital network bus. The remote device includes one or more data channels for respective one or more peripherals, and includes volatile channel-based memory for each data channel and non-volatile device-based memory for the remote device. The bus controller is and configured to send a command across the network bus to the remote device, and in response thereto, the remote device is configured to acquire data from a designated data channel or command the designated data channel to perform a conversion. The command is from a communication protocol with which the remote device is compatible, and includes a set of channel commands for accessing the channel-based memory, and a different, distinct set of device-memory commands for accessing the device-based memory. The channel commands and device-memory commands have different timing requirements.

Abstract: An apparatus, system, and method are disclosed for managing configuration parameters of a non-volatile storage device. The method includes storing a first set of configuration parameters for a non-volatile recording device. The first set of configuration parameters are configured for a storage operation on a storage element of the non-volatile recording device. The method also includes storing a second set of configuration parameters for the non-volatile recording device during execution of the storage operation on the storage element. The second set of configuration parameters are configured for a second storage operation on the storage element of the non-volatile recording device.

Abstract: A technique includes performing an update to a location of a non-volatile memory. The update is created by execution of at least one machine executable instruction of a plurality of machine executable instructions. The technique includes using a processor-based machine to selectively track the update to allow recovery of the execution to a given consistency point based at least in part on whether the machine executable instruction(s) creating the update are located within a synchronized section of the plurality of machine executable instructions.

Abstract: Solid state drive (SSD) packages are provided including a controller package and at least one non-volatile memory package. The controller package and the at least one non-volatile memory package are connected to each other using a package-on-package (PoP) technique. A data input/output of the at least one non-volatile memory package is controlled by using the controller package.

Abstract: A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.

Abstract: Methods and systems are disclosed for symmetrical replication of data within multiple data subsystems for failure management in non-volatile memory (NVM) systems. Disclosed embodiments perform symmetrical write operations to multiple different data block subsystems so that duplicate subsystems are created. As the subsystems are operated symmetrically, address locations and pointers are the same for each subsystem. If an error is detected in data within one subsystem, the duplicated data at the same symmetrical location within a duplicate subsystem can be used. As such, the endurance and lifetime of NVM systems is greatly enhanced. These extended lifetime NVM systems can then be used, for example, to emulate EEPROM (erasable programmable read only memory) systems.

Abstract: An apparatus having a nonvolatile memory and a controller. The memory stores information in multiple pages. The information includes data units and headers. Each data unit is associated with a respective identifier in an address space of the apparatus and a respective location in the memory, has a respective header having the respective identifier, and is associated with a respective time stamp. Multiple headers include ones of the time stamps. The controller is configured to (i) read information stored in the pages, (ii) determine an order in which the data units were written based on the time stamps, (iii) locate based on the order (a) each last-written occurrence of the respective identifiers and (b) the respective locations of the data units associated with the last-written occurrences, and (iv) rebuild a map of the controller according to the respective locations of each last-written occurrence of each respective identifier.

Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Abstract: A method can include injecting key information from memory of a memory device into non-volatile memory of a hardware device via a data port of the hardware device; receiving via the data port identification information from the hardware device that identifies the hardware device; and associating the key information and the identification information in the memory of the memory device. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: Apparatuses, systems, and methods are disclosed for managing contents of a cache. A method includes receiving a read request for data stored in a non-volatile cache. A method includes determining whether a read request satisfies a frequent read threshold for a cache. A method includes writing data of a read request forward on a sequential log-based writing structure of a cache in response to determining that the read request satisfies a frequent read threshold.

Abstract: Quality of service indicators are provided from a host via a host interface. The quality of service indicators relate to data stored in a non-volatile data storage via the host. Workload indicators related to the quality of service indicators are measured, and a weighting is assigned to the host in response to a correlation between the quality of service indicators and the measured workload indicators. The weighting is applied to the quality of service indicators when responding to data access requests from the host.

Abstract: According to an embodiment, the program memory stores application software in a ROM area. An address range of the application software targeted for restriction on use in the program memory is described in the application information memory. Yes-or-no information on the use of the application software targeted for restriction on use is written in the yes-or-no information memory. The switch switches between whether or not to apply an input signal to the processor core. The judgment unit judges whether or not a program counter value of the processor core is within the address range described in the application information memory and, when the program counter value is within the address range, the judgment unit controls the switching of the switch based on the yes-or-no information written in the yes-or-no information memory.

Abstract: A data capture system includes a processor instructed by configuration data that indicates a trigger event and data identifiers, a volatile memory that stores data based upon the data identifiers, and a non-volatile memory that stores contents of the volatile memory based upon detection of the trigger event by the processor. The data identifiers indicate data elements to be stored.

Abstract: A system includes a device, a BIOS, and a processor. The BIOS includes a storage operable to store predefined identifier/user defined name pairs. The processor is operable to, detect the device, determine a predefined identifier for the device, and access the storage to locate a predefined identifier/user defined name pair corresponding to the predefined identifier. The processor is further operable to provide a user defined name of the predefined identifier/user defined name pair when the predefined identifier/user defined name pair is present, and provide the predefined identifier of the predefined identifier/user defined name pair when the predefined identifier/user defined name pair is not present.

Abstract: A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N?1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N?1 memory location swap operations, and resets every (N2?N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.

Abstract: A virtual storage layer (VSL) for a non-volatile storage device presents a logical address space of a non-volatile storage device to storage clients. Storage metadata assigns logical identifiers in the logical address space to physical storage locations on the non-volatile storage device. Data is stored on the non-volatile storage device in a sequential log-based format. Data on the non-volatile storage device comprises an event log of the storage operations performed on the non-volatile storage device. The VSL presents an interface for requesting atomic storage operations. Previous versions of data overwritten by the atomic storage device are maintained until the atomic storage operation is successfully completed. Data pertaining to a failed atomic storage operation may be identified using a persistent metadata flag stored with the data on the non-volatile storage device. Data pertaining to failed or incomplete atomic storage requests may be invalidated and removed from the non-volatile storage device.

Abstract: A method of controlling a memory including a first storage area and a second storage area. The method includes determining, in response to a request for writing a write data string, whether the write data string changes a logical value stored in the memory from a first logical value to a second logical value, writing, to the first storage area, a logical value that is located in a position of the write data string and does not change an existing logical value of the memory from the first logical value to the second logical value, and writing the second logical value that is located in a position of the write data string and changes an existing logical value of the memory from the first logical value to the second logical value to the second storage area which is different from the first storage area.

Abstract: A data merging method for merging data belonging to a first logical block in a rewritable non-volatile memory module is provided. The method includes getting a second physical block from a free area of the rewritable non-volatile memory module and determining whether a valid logical page number is smaller than a predetermined number. The method also includes, when the valid logical page number is smaller than the predetermined number, storing a corresponding page mapping table in a start physical page of the second physical block and writing at least one valid page data belonging to the first logical block into at least one physical page of the second physical block. Accordingly, the method can effectively shorten the time for merging data.

Abstract: A method is provided to manage access to a memory array. The method includes encoding a bit string with a rank metric encoder to generate an encoded binary array, modifying the encoded binary array so each row has at most half of the row with a bit value and each column has at most half of the column with the bit value, and storing the modified binary array into corresponding memory devices of the memory array.

Abstract: A computer-based system, method and computer program product for generating chronologically based globally unique identifiers.

Abstract: For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to utilize a Solid State Drive (SSD) portion of the tiered levels of storage, while sparsely hot ones of the groups of data segments are migrated to utilize the lower-speed cache.

Abstract: The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.

Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count.

Abstract: Embodiments of systems, apparatuses, and methods for determining if an instruction of a virtual machine is allowed to modify a protected memory region are described. In some embodiments, a system detects an indication of an attempt by the instruction to write to the protected memory region. In addition, the system determines if the instruction is allowed to write to the protected memory region based on a starting address and data length of the instruction. Furthermore, if the instruction is allowed to write to the protected memory region, the system updates the protected memory region with the instruction results.

Abstract: A technique of managing data placement involves constructing an active extent list which identifies active extents stored in a storage pool based on a history of extent activity. The technique further involves based on the active extent list, generating preferred extent-tier pairings for extents of a particular LUN slice that are initially stored on a first tier of the pool, the preferred extent-tier pairings matching (i) a first extent of that LUN slice to the first tier and (ii) a second extent of that LUN slice to a second tier of the pool. The technique further involves, based on the preferred extent-tier pairings, maintaining the first extent on the first tier and relocating the second extent from the first tier to the second tier to distribute the first and second extents of that LUN slice across multiple tiers of the pool in accordance with the extent activity history.

Abstract: A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.

Abstract: A method for providing for write once read many (WORM) times from at least some addresses of a storage drive that is otherwise manufactured for multiple writes to individual addresses. In at least one embodiment, a WORM area(s) is defined by a START_LBA and an END_LBA and the method uses a HWM_LBA to determine whether a LBA in the WORM area has been written to previously and to prevent previously written to LBA(s) in the WORM area from being rewritten. In at least one embodiment where there are multiple WORM areas, each WORM area has its own respective START_LBA, END_LBA and HWM_LBA.

Abstract: The present invention relates to a method, system, and computer program product for determining storage device weight values to use to select one of the storage devices to use as a target storage to which data from a source storage is migrated. A determination is made, for each of the storage devices, of static parameter values for static parameters comprising attributes of the storage device and dynamic parameter values for dynamic parameters providing device health information determined by accessing the storage device to determine operational conditions at the storage device. Storage device weight values are determined as a function of the static parameter values and the dynamic parameter values of the device. The determined storage device weight values are used to select one of the storage devices as the target storage to which data from the source storage is migrated.

Abstract: Memory units and computer systems are provided. The computer systems include a memory unit. The memory unit includes a stable storage unit, an unstable storage unit, and a controller. The unstable storage unit stores pending write operations for the stable storage unit. The controller is configured to determine the locations in the unstable storage that store the pending write information and to selectively write the pending write operations to the stable storage unit when power to the memory unit is interrupted.

Abstract: The present disclosure relates to an electronic device for storing data on PRAM and a memory control method thereof The electronic device of the present disclosure comprises: a nonvolatile memory in which data is stored; a volatile memory in which an address conversion table of a nonvolatile memory is stored; and a controller that stores data on a nonvolatile memory by referencing an address conversion table of a nonvolatile memory stored on a volatile memory. Due to this, a nonvolatile memory having limitative number of write and read such as PRAM can be operated more effectively.

Abstract: A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width (“MFW”) instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests.

Abstract: A manufacturing testing system includes an information handling system, a RAM memory device including a reserved physical RAM address space, non-volatile bootable disk, and a header for the reserved physical RAM address space. The head may include a non-volatile bootable disk signature, a start physical address, a length of reserved space, and a processor.

Abstract: A method includes reading a representation of tracking data from at least a portion of a non-volatile memory. The method further includes adjusting a read voltage based on a comparison between a number of bits in tracking data as compared to a count of bits in the representation of the tracking data.

Abstract: A storage device with a health status check feature is disclosed. In one embodiment, the storage device keeps track of the number of erase cycles performed on the memory of the storage device. The storage device also stores a value of the predicted limit on the number of times that erase cycles can be performed on the memory. In response to a request from a host device for the health status of the memory, the storage device can provide the host device with information about how many erase cycles have been performed on the memory as compared to the predicted limit.

Abstract: Embodiments are disclosed for presenting a digital content item comprising a plurality of content portions. One example embodiment includes a computing device comprising a primary content storage machine, where the primary content storage machine is configured to selectively store one or more content portions of a digital content item. The computing device is configured to determine a dynamically changing content access window including one or more content portions useable to provide an above-threshold user experience based on a current access position of the digital content item. The computing device is configured to dynamically load the primary content storage machine with the content portions of the digital content item corresponding to the content access window and dynamically unload the content portions of the digital content item outside of the content access window from the primary content storage machine.

Abstract: The invention discloses a method for storing data and a device of implementing the same. The method comprises receiving a request for storing data sent by a user and storing the data to an SSD according to the received request. The device comprises a request receiving module used to receive the request storing data and an SSD storage module used to store the data to an SSD according to the received request. The invention ensures consistency of data storage by storing data to an SSD according to the received request, thereby reducing data redundancy caused by using a cache layer to cache the data in the prior art. Additionally, the use of a single layer of an SSD to store data avoids the need of reloading data in the cache layer once a machine is power-down, thereby reducing the complexity of system design and the cost of operation and maintenance.

Abstract: A method of storing data in a storage media can include determining whether a size of data to be stored in the storage media satisfies a reference condition and compressing the data to provide compressed data for storage in the storage media upon determining that the size satisfies a reference condition.

Abstract: The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time.

Abstract: A memory control apparatus includes a temperature obtaining unit, a priority determination unit, and a write processing unit. The temperature obtaining unit is configured to obtain, in a memory having a plurality of measurement areas each including a plurality of unit areas, temperatures measured in the plurality of measurement areas. The priority determination unit is configured to determine a priority for each unit area in accordance with a degree of consumption and the temperature of the measurement area including the unit areas, the degree of consumption being a degree of consumption of the unit area which is caused by a write process performed. The write processing unit is configured to preferentially perform the write process with respect to the unit area having a higher priority as a data write destination.

Abstract: A block storage system includes a host and comprises a block storage module that is coupled to the host. The block storage module includes a MRAM array and a bridge controller buffer coupled to communicate with the MRAM array. The MRAM array includes a buffer widow that is moveable within the MRAM array to allow contents of the MRAM array to be read by the host through the bridge controller buffer even when the capacity of the bridge controller buffer is less than the size of the data being read from the MRAM array.

Abstract: A read/write ratio for each of a plurality of data segments classified in a hot category as hot data segments is determined. Each of the plurality of hot data segments is ordered by the read/write ratio in a descending order. Each of a plurality of available SSD devices is ordered by a remaining life expectancy in an ascending order. Those of the plurality of hot data segments are matched with those of the plurality of hot data segments with those of the plurality of available SSD devices such that a hot data segment having a higher read/write ratio is provided to an SSD device having a smaller remaining life expectancy than another hot data segment having a lower read/write ratio.