Abstract: Examples disclosed herein relate to dual in-line memory module (DIMM) battery backup. Some examples disclosed herein describe systems that include a backup power source pluggable into a DIMM slot. The backup power source may include a plurality of battery cells electrically connected to a DIMM to provide backup power to the DIMM. Each of the plurality of battery cells supporting the DIMM may be electrically connected to a DC-to-DC converter in series and to each other in parallel.

Abstract: Aspects of the subject matter described herein relate to storage systems and aliased memory. In aspects, a file system driver or other component may send a request to a memory controller to create an alias between two blocks of memory. One of the blocks of memory may be used for main memory while the other of the blocks of memory may be used for a storage system. In response, the memory controller may create an alias between the blocks of memory. Until the alias is severed, when the memory controller receives a request for data from the block in main memory, the memory controller may respond with data from the memory block used for the storage system. The memory controller may also implement other actions as described herein.

Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.

Abstract: A method includes detecting a storage device at a protected node and determining whether the storage device has been checked-in for use with at least the protected node. The method also includes granting access to the storage device in response to determining that the storage device has been checked-in for use with at least the protected node. The method further includes blocking access to the storage device in response to determining that the storage device has not been checked-in for use with at least the protected node. The method may also include determining whether a file on the storage device has been checked-in for use with at least the protected node. Meaningful access to the file is granted or blocked in response to determining that the file has or has not been checked-in for use with at least the protected node.

Abstract: Technologies for managing an operational characteristic of a solid state drive include monitoring the operational characteristic to determine whether the operational characteristic satisfies a low threshold and a high threshold. If the operational characteristic does satisfy the low threshold, the solid state drive throttles high power memory accesses requests while not throttle low power memory access requests. If the operational characteristic satisfies a high threshold, the solid state drive is configured to throttle all memory accesses. The operational characteristic may be embodied as, for example, a temperature of the solid state drive.

Abstract: A semiconductor storage device includes m (m?2) memory chips, a buffer, and a controller. The controller arranges, in the buffer, a first plurality of data units to be transferred to N (1?N?m) of the m memory chips, in an order in which each of the first plurality of data units has been received from a host, for each one of the N memory chips, and arranges a second plurality of data units, if any, in an order in which each of the second plurality of data units has been received from the host, for each one of the next N memory chips. Upon the arranged data units, the controller collectively transfers the certain number of arranged data units to the memory. The value of N is changed based on an amount of data accumulated in the buffer.

Abstract: Common microcontroller unit (MCU) self-identification information is disclosed. In one embodiment, an MCU is contained in a package. The MCU includes a central processing unit (CPU) and a non-volatile memory. This non-volatile memory stores information specific to the MCU and/or the package. The non-volatile memory also stores a common main program that, when executed by the CPU, accesses the information. The information enables the common main program to adapt itself to resources of the MCU and/or package that are identified in the information.

Abstract: Systems and methods for destroying sensitive enterprise data on portable devices are provided. Such systems and methods may include providing a portable device that includes a security agent for deleting sensitive enterprise data. The security agent on the portable device can be required to regularly be authenticated by a user through an authentication server. The authentication server provides a pre-determined timeframe for which the user would need to re-authenticate. Failure by the user to re-authenticate within the pre-determined timeframe can result in the security agent proceeding with deleting the sensitive enterprise data on the portable device.

Abstract: Aspects extend to methods, systems, and computer program products for predicting solid state drive reliability. Aspects of the invention can be used to predict and/or to configure a data center to minimize one or more of: SSD capacity degradation (how much storage an SSD has left), SSD performance degradation (reduced read/write latency/throughput), and SSD failure. Models and data center considerations can be based on device level SSD related operations, such as, for example, read, write, erase. Operations decisions can be made for a data center based on SSD specific features, such as, for example, remaining capacity, write amplification factor, etc. Dependence and/or causality of various different data center factors can be leveraged. The impact of the various data center factors on different SSD failure modes and capacity/performance degradation can be quantified to drive SSD design, SSD provisioning, and SSD operations.

Abstract: Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.

Abstract: A BIOS delivery installation package includes a basic input/output system (BIOS) update payload including a BIOS image. The BIOS delivery installation package also includes a first hash corresponding to a portion of the BIOS image.

Abstract: An aggregation module combines a plurality of logical address spaces to form a conglomerated address space. The logical address spaces comprising the conglomerated address space may correspond to different respective storage modules and/or storage devices. An atomic aggregation module coordinates atomic storage operations within the conglomerated address space, and which span multiple storage modules. The aggregation module may identify the storage modules used to implement the atomic storage request, assign a sequence indicator to the atomic storage request, and issue atomic storage requests (sub-requests) to the storage modules. The storage modules may be configured to store a completion tag comprising the sequence indicator upon completing the sub-requests issued thereto. The aggregation module may identify incomplete atomic storage requests based on the completion information stored on the storage modules.

Abstract: Performance tuning in a storage system that includes one or more storage devices, including: storing, by a primary controller of the storage system, data corresponding to one or more computer processes into one or more of the one or more storage devices, determining, by a secondary controller that is configured similarly to the primary controller, one or more utilization patterns of the data, and initiating, in dependence upon the one or more utilization patterns of the data, a modification to a manner in which the one or more computer processes access the data stored in the one or more storage devices.

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.

Abstract: A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.

Abstract: A data access control apparatus of an embodiment includes an update region management apparatus including an update region management unit configured to record, in response to a writing request for data from an input apparatus, management information of a first address region in which the data is stored, a reading request management unit configured to record a second address specified in a reading request from a storage apparatus and a control unit configured to receive the writing request and the reading request, and control processing of the reading request and updating of the update region management unit and the reading request management unit.

Abstract: Provided are systems and methods for a location-aware, self-configuring peripheral device. In some implementations, the peripheral device may include two or more personalities. In these implementations, a personality enables the peripheral device to provide a service. In some implementations, the peripheral device may be configured to receive a configuration cycle. In some implementations, the peripheral device may further select a personality from among two or more personalities. The peripheral device may use information derived from the configuration cycle to make this selection. Selecting a personality may further include configuring the peripheral device according to the selected personality.

Abstract: A mass data storage system includes a number of communicatively coupled storage drives powered by one or more power supplies. Shared control electronics selectively connect power and a data signal to a select storage drive via instructions within a control signal received by the common controller. Instructions for selectively powering and connecting the data signal are transmitted over a first signal path to a first controller of the shared electronics. Responsive to successful execution of the instructions, a drive access command is sent over a second different signal path to a second controller of the shared electronics.

Abstract: A memory system includes a memory device including a plurality of blocks each comprising first and second regions of pages; and a controller suitable for storing a plurality of data in the first region and hot/cold information respectively corresponding to the plurality of data in the second region.

Abstract: A method for allowing an operating system (OS), to access an encrypted data storage system of a computer, wherein: the data storage system comprises: a partition; and first encrypted data units that comprise partition table data of said data storage system; and said computer is connectable to an external device comprising: a boot loader for an external OS that is not installed on the computer; and partitioning information capturing an expected location of said partition in the data storage system; and wherein second encrypted data units that comprise reference partition table data for said data storage system are available from said computer or said external device, the method comprising: upon connection of said external device to the computer, instructing to boot the computer from said boot loader; and during or after booting of the computer: comparing the first and second encrypted data units; and if the first and second encrypted data units match, allow the external OS to access, based on the partitioning

Abstract: The present invention is notably directed to a method for allowing an operating system, or OS, to access an encrypted data storage system of a computer (10), wherein: the data storage system (11) comprises: a partition (122); and first encrypted data units (120) that comprise partition table data of said data storage system; and said computer (10) is connectable to an external device (20) comprising: a boot loader (24) for an external OS (112) that is not installed on the computer; and partitioning information (22) capturing an expected location of said partition (122) in the data storage system; and wherein second encrypted data units (220) that comprise reference partition table data for said data storage system are available from said computer (10) or said external device, the method comprising: upon connection (S21) of said external device (20) to the computer, instructing to boot (S23) the computer (10) from said boot loader (24); and during or after booting of the computer: comparing (S25) the first (12

Abstract: A packet processor or packet processing pipeline may implement forwarding table updates during live packet stream processing. Updates may be updates to add or remove entries from group of entries in a forwarding table or may be updates to defragment the available entries in a chain of entries maintained in a forwarding table. Reserved entries may be allocated for moving entries as part of updates so that migrations of the entries from one location to another may be performed atomically.

Abstract: Error reduction in memristor programming includes programming an n-th switched memristor of a switched memristor array with an error-corrected target resistance. The error-corrected target resistance is a function of a resistance error of the switched memristor array and a target resistance of the n-th switched memristor. The n-th switched memristor programming is to reduce a total resistance error of the switched memristor array.

Abstract: The present disclosure is directed to firmware block dispatch based on fusing. A device may determine firmware blocks to load during initialization of the device based on fuses set in a processing module in the device. A firmware module may comprise at least a nonvolatile (NV) memory including boot code and a firmware information table (FIT). During initialization the boot code may cause the processing module to read fuse information from a fuse module and to determine at least one firmware block to load based on the fuse information. For example, the fuse information may comprise a fuse string and the processing module may compare the fuse string to the FIT table, determine at least one pointer in the FIT table associated with the fuse string and load at least one firmware block based on a location (e.g., offset) in the NV memory identified by the at least one pointer.

Abstract: An image forming system capable of properly managing maintenance information on a punch die mounted on a puncher. The puncher punches holes in a sheet using a removably mounted punch die. A punch die memory mounted on the punch die stores maintenance information concerning the punch die. A CPU of the image forming system detects mounting of a punch die. A RAM of the same stores maintenance information concerning each of punch dies mounted on the puncher. When a punch die is mounted on the puncher, the CPU performs comparison between maintenance information is stored in the RAM, and maintenance information stored in the punch die memory, and when the maintenance information stored in the RAM is older, the CPU updates the information in the RAM to the information in the punch die memory.

Abstract: A controller determines whether system boot code stored in a first non-volatile memory is compromised and non-recoverable. In response to determining that the system boot code is compromised and non-recoverable, switch logic is activated to connect a second non-volatile memory to the shared bus and to disconnect the first non-volatile memory from the shared bus.

Abstract: A recording device operates in accordance with an instruction from an access device. The recording device comprising a nonvolatile memory that stores data, a communication unit that receives an instruction issued by the access device, and a memory controller that controls the nonvolatile memory. When a recording instruction for recording data into the nonvolatile memory is received from the access device, the memory controller starts recording of data into the nonvolatile memory. When the memory controller receives from the access device a suspension instruction for suspending the recording of data, the memory controller stores suspension information into the nonvolatile memory, the suspension information indicating a suspended position as a position in a recording area of the nonvolatile memory at which the data is being recorded upon reception of the suspension instruction.

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Abstract: An adaptive compression data storing method for non-volatile memories and a system using the method are disclosed. The system includes a host interface unit, a data compressor, a padding unit, a buffer, a combining unit, and a mapping table unit. By combining some compressed data in one page, the present invention can settle the problem that space for storing a compressed data that can not be utilized. Further, lifetime of non-volatile memories can be extended.

Abstract: An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.

Abstract: An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.

Abstract: The present disclosure relates to a method for controlling a plug-in by a router and the router thereof. The method includes: receiving a plug-in state request querying an operational state of a plug-in sent from a terminal device; obtaining the operational state of the plug-in according to the plug-in state request; and sending the operational state of the plug-in to the terminal device.

Abstract: Aspects of the subject matter described herein relate to storage systems and aliased memory. In aspects, a file system driver or other component may send a request to a memory controller to create an alias between two blocks of memory. One of the blocks of memory may be used for main memory while the other of the blocks of memory may be used for a storage system. In response, the memory controller may create an alias between the blocks of memory. Until the alias is severed, when the memory controller receives a request for data from the block in main memory, the memory controller may respond with data from the memory block used for the storage system. The memory controller may also implement other actions as described herein.

Abstract: A computer system, having a non-volatile storage unit (152), a main storage unit (151), and a data processor (102) including a memory management unit (102A) for managing a program stored in the non-volatile storage unit and the main storage unit to transfer a program stored in the non-volatile storage unit to the main storage unit, wherein the memory management unit (102A) includes a program storage control function of storing a program subjected to predetermined data conversion and a program yet to be subjected to predetermined data conversion in the non-volatile storage unit, and a function of combining programs subjected to predetermined data conversion so as not to bridge over a boundary between blocks at the execution of the program storage control function, as well as, at a first access to a certain block, expanding all the data included in the block to a corresponding block of the main storage unit.

Abstract: A system includes a baseboard management controller (BMC) and a remote computing device communicatively connected to the BMC via a network. The BMC includes a processor, a volatile memory, and a non-volatile memory storing a firmware. The remote computing device includes first and second computer executable code. The firmware, when executed at the processor, is configured to: in response to a debug command, request, receive, and execute the first computer executable code. The first computer executable code, when executed at the processor, is configured to mount a remote file system to the BMC corresponding to the second computer executable code, such that the second computer executable code is accessible to the BMC, retrieve the second computer executable code, and execute the second computer executable code at the BMC to perform an on-site debug process without interrupting operation of the firmware.

Abstract: A method including creating a transaction object for a transaction identified by a TOI and associated with an object identified by an OID, storing a TE and a MD frag for the transaction object, receiving a write request to write data to the transaction object, storing second TE including a TOI and offset and a data frag including the data, storing an entry including a hash value and a physical address of the data frag, and receiving a commit request to commit the transaction. In response to the commit request storing a third TE and a second MD frag for the transaction object, where the second MD frag identifies the object and specifies that the transaction is committed and updating a second entry including a second hash value and a second physical address for a second data frag to replace the second physical address with the physical address.

Abstract: Encrypted storage often introduces unwanted latency in access. This delay can result in a processor having to wait for critical data thus slowing performance. Generally speaking, the latency is at most an issue when reading from encrypted storage, since the processor may need the information read from encrypted storage to proceed. During a write operation, there typically is not an issue because the processor does not need to wait for the end of the write operation to proceed. A variant of counter (CTR) mode for a block cipher can be used to perform the majority of the decryption operation without knowledge of the ciphertext, therefore the majority of the decryption operation can be performed concurrently with the retrieval of the ciphertext from memory. In order to further secure the encrypted storage, a light encryption can be performed to further obfuscate the ciphertext.

Abstract: Aspects include computing devices, systems, and methods for implementing executing decompression of a compressed page. A computing device may determine a decompression block of a compressed page that contains a code instruction requested in a memory access request. Decompression blocks, other than the decompression block containing the requested code instruction, may be selected for decompression based on being situated between an end of the compressed page and the decompression block containing the requested code instruction. Decompression blocks not identified for decompression may be substituted for a fault or exception code. The computing device may decompress decompression blocks identified for decompression, starting at the end of the compressed page and terminating the decompression of the compressed page upon filling all blocks with decompressed blocks, faults, or exception code.

Abstract: Example embodiments disclosed herein relate to security parameter zeroization. Example embodiments include security parameter zeroization based on a remote security monitor.

Abstract: A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move back and forth within the cache hierarchy. The cache line may be evicted from the cache hierarchy after the lock property is removed.

Abstract: A method includes booting an information handling system, starting a BIOS on the information handling system, storing configuration information for the information handling system, retrieving, by an operating system (OS) loader, the configuration information, determining, by the OS boot manager, that a configuration of the information handling system indicated by the configuration information is incompatible with an OS loaded on the information handling system by the OS boot manager, determining, by the OS boot manager, that the incompatibility can be mitigated by changing a setting of the information handling system, changing, by the OS boot manager, the setting in response to determining that the incompatibility can be mitigated, and launching, by the OS boot manager, the OS in response to changing the setting.

Abstract: The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

Abstract: Various embodiments allow for flexible and secure updates of drivers for numerous types of external memory devices by utilizing an address-selection mechanism within a simple and secure ROM code to enable the loading of a dynamic routine from an external source into a dynamic memory. In certain embodiments, the routine enables a simple and trusted framework to access and modify the content of any number of complex memory devices via simple commands without affecting existing security measures. This increases the usable lifetime of secure ROM code, simplifies device validation, and shortens the overall development cycle by extending the functionality of secure ROM code while keeping the ROM code and any programming thereof simple.

Abstract: Patching a read-only memory, including a program executable by a processor is performed with a MRAM-based CAM device connected to the address bus and comparing in the background the addresses requested by the processor with the elements of a vector of addresses. The match-in-place operation is done in parallel on all the elements of the vector and typically is performed in less than a clock cycle. If a match is found, the CAM device outputs a diversion address that's used to retrieve a substitution machine code element from a flash memory that is presented to the processor in lieu of the one addressed in the ROM. This patching scheme is totally transparent, has little overhead, and extreme granularity.

Abstract: There is provided a control device which includes a cache memory configured to temporarily store data, a nonvolatile memory configured to store a copy of the data stored in the cache memory, a battery configured to supply power to the cache memory in a case of a power failure, a data save processing unit configured to save data stored in a backup target region of the cache memory to the nonvolatile memory in the case of the power failure, and a charge control unit configured to charge the battery up to a target amount of charge which is determined on the basis of a size of the backup target region.

Abstract: A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.

Abstract: A method of operation of a data programming control system includes: providing a secure data management host server coupled to a network; encrypting a contract manufacturer job by the secure data management host server, including: providing a memory image file, creating a programmer encrypted file from the memory image file, and encrypting permissions and the programmer encrypted file to form the contract manufacturer job; decrypting the contract manufacturer job transmitted through the network by a secure data management local server; transmitting the programmer encrypted file by the secure data management local server to a device programmer; and programming a device with the memory image file decrypted by the device programmer.

Abstract: Enable a read command of a first flash memory. After the read command of the first flash memory is enabled, a ready/busy signal of the first flash memory enters a busy waiting time, and a read command of a second flash memory starts to be enabled. Start to read data of the first flash memory when the busy waiting time is over. Enable the read command of the first flash memory again upon completion of reading the data of the first flash memory. Start to read data of the second flash memory after the read command of the first flash memory is enabled again. And enable the read command of the second flash memory again upon completion of reading the data of the second flash.

Abstract: A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.

Abstract: An apparatus comprising one or more processors configured to implement a plurality of operations for an operating system (OS) platform including a kernel and a user application, one or more shared resource blocks by the kernel and the user application, and one or more shared locks by the kernel and the user application corresponding to the shared resource blocks, wherein the user application is configured to synchronize accesses to the shared resource blocks between a user thread and a kernel thread by directly accessing the locks without using a system call to the kernel.