Abstract: Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

Abstract: The technique introduced here involves using a block address and a corresponding generation number as a “fingerprint” to uniquely identify a sequence of data within a given storage domain. Each block address has an associated generation number which indicates the number of times that data at that block address has been modified. This technique can be employed, for example, to determine whether a given storage server already has the data, and to avoid sending the data to that storage server over a network if it already has the data. It can also be employed to maintain cache coherency among multiple storage nodes.

Abstract: Circuits and methods for performing search operations in a content addressable memory (CAM) array are provided. A system for searching a CAM includes a circuit that selectively activates a main-search of a two stage CAM search while a pre-search of the two stage CAM search is still active.

Abstract: A computer system includes a central processing unit (CPU), a main memory including a non-volatile memory, and a memory reset controller controlling the main memory. If a memory reset command is input from outside, while the computer system is powered on/off, the memory reset controller deletes data stored in the main memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, controller, memory, wireless communication function section, and extension register. The controller controls the nonvolatile semiconductor memory device. The memory is serving as a work area of the controller. The wireless communication module has a wireless communication function. The extension register is provided in the memory. The controller processes a first command to read data from the extension register, and a second command to write data to the extension register. The extension register records, an information specifying the type of the wireless communication function in a specific page, and an address information indicating a region on the extension register to which the wireless communication function is assigned.

Abstract: According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.

Abstract: Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM.

Abstract: A method and apparatus for accessing a storage media employed to store data from a host includes identifying a module as a block storage device. The block storage device is coupled to a host and includes a bridge controller and magnetic random access memory (MRAM). The MRAM has a buffer window for storing data from a host, the buffer window is movable throughout the MRAM. The bridge controller has a bridge controller buffer and controller registers. A request to access the block storage device is intercepted and a command to the block storage device is issued. If the command is a write command, at least a portion of the data to be saved into the MRAM is saved. The size of the at least a portion of the data is based on the capacity of the bridge controller buffer. Further, at least a portion of the data to the buffer window is transferred and upon having additional data to be saved into the MRAM, the buffer window is moved within the MRAM.

Abstract: In a particular embodiment, a storage device with a memory, a controller, and a host interface has a write-once read-many device configuration. The memory contains a database having entries, each entry for a logical memory address. The memory further contains information for converting each logical memory address to a redirected logical memory address that corresponds to a physical memory location. The controller receives a command specifying a logical memory address and interprets the command based on information extracted from the database. The controller executes the command according to the information.

Abstract: A memory managing device and method and an electronic apparatus are provided. The memory managing device is applied to a memory having a plurality of storage regions capable of being separated physically, comprising: a storage detecting unit for detecting the current storage status of the memory; a block computing unit for computing the current active block in the memory; a discreteness deciding unit for deciding whether the discreteness of a segment in the memory is larger than a predetermined threshold; a segment arranging unit for arranging the segment when the discreteness is larger than the predetermined threshold to move the active block to a set of storage regions whose number of the storage regions is less than that before the movement; and a power consumption setting unit for setting the storage regions other than the set of the storage regions in the memory to a low power consumption status.

Abstract: A firmware cleanup device includes a solid state disk (SSD) and an operation member. The SSD includes two pads and a connection portion, the connection portion defines two contacting pins respectively and electronically connected to the two pads. The operation member is detachably connected to the connection portion, the operation member includes two interconnected connection lines, and the two connection lines are respectively and electronically connected to the two contacting pins.

Abstract: The present disclosure relates to a data storage system and method that includes at least two solid state devices that can be classified in at least two different efficiency levels, wherein data progression is used to allocate data to the most cost-appropriate device according to the nature of the data.

Abstract: The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event.

Abstract: A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: The present invention provides a method of establishing a hard disk physical partition. First of all, it selects a sector in which the head of the hard disk physical partition is located, and establishes a user available partition of the hard disk within the range of the hard disk physical volume from the sector, the other portion of the hard disk becomes a protected partition of the hard disk, finally constitutes one hard disk physical partition. After entering into the hard disk physical partition, only the user available partition can be accessed, the protected partition is invisible to the user. It can establish the different hard disk physical partition in the different position of the hard disk through selecting the sector where the head of the hard disk is located.

Abstract: An operating method of a nonvolatile memory device controller includes generating a code word through polar encoding of information bits, reading a mapping pattern, generating a repeated mapping pattern through iteration of the mapping pattern, and mapping each bit of the code word onto a specific bit of multi-bit data of the nonvolatile memory device, based upon the repeated mapping pattern.

Abstract: A method for selectively placing cache data, comprising the steps of (A) determining a line temperature for a plurality of devices, (B) determining a device temperature for the plurality of devices, (C) calculating an entry temperature for the plurality of devices in response to the cache line temperature and the device temperature and (D) distributing a plurality of write operations across the plurality of devices such that thermal energy is distributed evenly over the plurality of devices.

Abstract: A storage system includes a storage that stores a file; and a plurality of access control devices that control access to the storage and include a cache memory in which the file is stored in blocks, wherein when receiving an update request of a prescribed block and latest data of the prescribed block is not stored in the cache memory of a first access control device, the first access control device among the plurality of access control devices obtains a version number added to the latest data from a second access control device, in which the latest data is stored, among the plurality of access control devices, and wherein the first access control device stores update data that updates the prescribed block in the cache memory of the first access control device and adds a new version number to the update data based on the version number.

Abstract: Disclosed are systems, methods and computer program products for secure rebooting and debugging a peripheral subsystem of a system on a chip (SoC) device. According to one aspect of the method, when an application processor of the SoC device detects crash of the peripheral subsystem, the application processor loads a secure boot agent into SoC memory. The secure boot agent is configured to access a secure memory region of the peripheral subsystem containing memory dump data associated with the peripheral subsystem. The secure memory region is inaccessible to the application processor. The Secure boot agent encrypts the memory dump data in the secure memory region and opens the secure memory region for access to the application processor. The application processor accesses the secure memory region and collects the encrypted memory dump data. The application processor then forwards the encrypted memory dump data to a third party for debugging purposes.

Abstract: A storage layer is configured to store data at respective offsets within storage units of a storage device. Physical addresses of the data may be segmented into a first portion identifying the storage unit in which the data is stored, and a second portion that indicates the offset of the data within the identified storage unit. An index of the data offsets (e.g., second portions of the physical addresses) may be persisted on the storage device. The first portion of the address may be associated with logical addresses of the data in a forward index. The forward index may omit the second portion of the physical addresses, which may reduce the memory overhead of the index and/or allow the forward index to reference larger storage devices. Data of a particular logical address may be accessed using the first portion of the physical address maintained in the forward index, and the second portion of the media address stored on the storage device.

Abstract: According to the embodiments, a first management table, which is included in a nonvolatile second semiconductor memory and manages data included in a second storage area by a first management unit, is stored in the second semiconductor memory and a second management table for managing data in the second storage area by a second management unit larger than the first management unit is stored in a first semiconductor memory capable of random access.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM). A read frequency of a first logical block address (LBA) is maintained, and when the read frequency of the first LBA exceeds a threshold and a corresponding PBA is assigned to a data sector of the disk, first data stored in the data sector is copied to a memory segment of the NVSM. When the read frequency of the first LBA exceeds a threshold and the PBA is assigned to a memory segment of the NVSM, first data stored in the memory segment is copied to a data sector of the disk. When a read command is received to read the first LBA, a decision is made to read the first data from one of the NVSM and the disk.

Abstract: Host input/output (I/O) operations are performed via a file stored in a non-volatile storage coupled to a storage controller while data structures are being generated in the storage controller to copy data from source logical volumes to target logical volumes. The source logical volumes and the target logical volumes are logical representations of physical storage maintained in a plurality of direct access storage devices. The contents of the file are transferred from the non-volatile storage to one or more of the plurality of direct access storage devices, after the data structures have been generated, wherein the host I/O operations are performed via the file while the contents of the file are being transferred to the one or more of the plurality of direct access storage devices. The host I/O operations to the plurality of direct access storage devices are resumed, in response to transferring entire contents of the file to the one or more of the plurality of direct access storage devices.

Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.

Abstract: A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.

Abstract: A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.

Abstract: Disclosed is a semiconductor memory device which includes a normal memory cell array; a redundancy memory cell array; and a multi-row selection circuit configured to activate a defective normal memory cell or a defective normal word line of the normal memory cell array while activating a redundancy memory cell or a redundancy word line of the redundancy memory cell array.

Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.

Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.

Abstract: A solid state drive (SSD) interface controller includes a host interface, first and second command interfaces, and an interface storage unit. The host interface is configured to communicate data with a host device. The first command interface is configured to communicate data between the host interface and an SSD, and the second command interface is configured to communicate data between the host interface and the SSD independently of the first command interface. The interface information storage unit is configured to store information for determining activation or deactivation of each of the first and second command interfaces, and a capacity allocated to each of the first and second command interfaces.

Abstract: A higher-level system of a nonvolatile semiconductor storage device (hereinafter, semiconductor device) displays a GUI (Graphical User Interface), which receives a parameter group (one or more parameters) for controlling the processing of the semiconductor device. The higher-level system stores at least one of the parameters of the parameter group inputted to the GUI, and sends a command comprising the parameter group to the semiconductor device. The semiconductor device stores at least one of the parameters of the parameter group included in this command. The higher-level system and the semiconductor device each execute processing in accordance with the stored parameter. The semiconductor device sends, to the higher-level system, information of a log related to the processing executed in accordance with the stored parameter. The higher-level system displays feedback information on the basis of multiple times of logs. A user can change a desired parameter on the basis of this feedback information.

Abstract: Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium. A data stream is received and the data stream is portioned into a plurality of allocation units (AUs), where each AU in the plurality of AUs has a pre-determined byte length. A first portion of a selected AU from the plurality of AUs is written to a first page of the plurality of pages and a second portion of the selected AU is written to a second page of the plurality of pages by consecutively writing bytes of the selected AU from a starting byte on the first page to an ending byte on the second page.

Abstract: Disclosed are methods, systems and products, including a method that includes establishing in a computing environment, implemented using at least one processor-based device, a non-immutable object as being a read-only object, the computing environment not allowing performance of operations that cause modification of the read-only non-immutable object. The method also includes preventing by the at least one processor-based device performance of an operation on the read-only non-immutable object that would cause the read-only non-immutable object to be modified.

Abstract: A storage module is configured to determine a health metric of a storage division of a solid-state storage medium. The health metric may comprise a combination of factors, including, but not limited to: wear level, performance (e.g., program time, erase time, and the like), error rate, and the like. A wear level module may configure storage operations to reduce the wear rate of storage divisions having poor health metrics and/or heath metrics that are degrading more quickly than other storage divisions. Reducing wear rate may include deferring grooming operations, delaying use for storage operations, temporarily retiring the storage division, or the like. Storage divisions may be brought back into service at normal use rates in response determining that other portions of the storage media have been worn to the point that they exhibit similar health and/or reliability characteristics.

Abstract: A storage drive includes a non-volatile semiconductor memory, and interface, a compression module, a sector module, and a control module. The interface is configured to receive first data sectors transmitted from a host to the storage drive. The compression module is configured to compress the first data sectors to generate second data sectors. Lengths of the second data sectors vary. The first sector module is configured to generate third data sectors by adding nuisance data to (i) the second data sectors, or (ii) an encrypted version of the second data sectors, wherein lengths of the third data sectors do not vary. The control module is configured to store the third data sectors in the non-volatile semiconductor memory.

Abstract: A data protection device includes a basic input output system chip and a main control chip. The basic input output system chip stores basic input output system program and includes a write protection pin and a plurality of status registers. The main control chip includes a plurality of general purpose input output pins. One general purpose input output pin is electrically connected to the write protection pin of the basic input output system chip, the voltage level of the general purpose input output pin is controlled by performing different command programs of the basic input output system program, and the status registers and the basic input output system chip are selectable to be in a write protection mode or a writable mode under the control of the voltage level of the write protection pin of the basic input output system chip.

Abstract: Systems and methods are provided that may be implemented for out-of-band backup and/or restore of information handling system components. Such out-of-band backup and restore operations may be performed, in one embodiment, to backup and/or restore hardware profile information such as firmware images and corresponding system configuration information.

Abstract: A solid-state mass storage device for use with host computer systems, and methods of increasing the endurance of non-volatile memory components thereof that define a first non-volatile memory space. The mass storage device further has a second non-volatile memory space containing at least one non-volatile memory component having a higher write endurance than the memory components of the first non-volatile memory space. The second non-volatile memory space functions as a low-pass filter for host writes to the first non-volatile memory space to minimize read accesses to the first non-volatile memory space. Contents of the second non-volatile memory space are managed using a change counter.

Abstract: Disclosed is an information storing device which includes a first interface for connection with a host; a second interface for connection with the host; a first memory unit including a first controller controlling a first nonvolatile memory, the first controller communicating with the host via the first interface; and a second memory unit including a second controller controlling a second nonvolatile memory, the second controller communicating with the host via the second interface.

Abstract: A read only memory (ROM) data patch circuit replaces ROM data stored in N modified ROM data blocks with patch data stored in N random access memory (RAM) patch blocks based on patch information. The ROM data patch circuit includes a data patch detecting unit, a RAM address generating unit, and an address selecting unit. The data patch detecting unit generates N offset select signals and an address select signal. The N offset select signals indicate which block a read ROM address belongs to, and the address select signal represents whether the read ROM address belongs to any of the N modified ROM data blocks. The RAM address generating unit generates a read RAM address corresponding to the read ROM address based on the offset select signals. The address selecting unit outputs one of the read ROM address and the read RAM address based on the address select signal.

Abstract: A power loss condition is detected that affects volatile data that is cached in preparation for storage in a non-volatile, solid-state memory device. The volatile cached data is stored in an over-provisioned portion of the non-volatile, solid-state memory device in response to the power loss condition.

Abstract: Systems and methods of securely updating BIOS are disclosed. One such system comprises a reprogrammable memory, a first and a second register, and comparison logic. The reprogrammable memory comprises a first portion and a protect input. The protect input is configured to disallow writes to at least the first portion when the memory protect input is at a first level, and to allow writes to at least the first portion when the protect input is at a second level; The comparison logic is configured to drive a comparison output to a third level responsive to the first and second registers having equal values, and to drive the comparison output to a fourth level responsive to the first and second registers having different values. The comparison output is electrically coupled to the memory protect input.

Abstract: A cache module leverages a logical address space and storage metadata of a storage module (e.g., virtual storage module) to cache data of a backing store. The cache module maintains access metadata to track access characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not currently in the cache. The access metadata may be separate from the storage metadata maintained by the storage module. The cache module may calculate a performance metric of the cache based on profiling metadata, which may include portions of the access metadata. The cache module may determine predictive performance metrics of different cache configurations. An optimal cache configuration may be identified based on the predictive performance metrics.

Abstract: A method is disclosed of configuring a data storage device. A manufacturing procedure is executed to generate a configuration data record. The configuration data record is compared to configuration execution records of an executable file, wherein the configuration execution records are for configuring at least one configuration file of the data storage device. When the configuration data record interlocks with the configuration execution records, the configuration file is modified.

Abstract: A memory controller has a digital signal processor. The digital signal processor is configured to output a digital data signal of M+N bits of program data intended for programming a memory cell of a memory device. The digital signal processor is configured to receive a digital data signal of M+L bits read from the memory cell of the memory device and to retrieve from the received digital data signal M bits of data that were stored in the memory cell.

Abstract: Apparatuses, systems, and methods are disclosed for managing contents of a cache. A method includes receiving a read request for data stored in a non-volatile cache. A method includes determining whether a read request satisfies a frequent read threshold for a cache. A method includes writing data of a read request forward on a sequential log-based writing structure of a cache in response to determining that the read request satisfies a frequent read threshold.

Abstract: The inventive concept herein relates to data storage devices, and more particularly, to a hybrid storage device including a plurality of storage media. The hybrid storage device may include first and second storage media storing a plurality of data blocks according to a data type and a hybrid controller configured to copy a data block having a change type to the first storage medium if a data type of the data block stored in the second storage medium is changed.

Abstract: A method of pattern and image recognition and identification includes building a data store of known patterns or images having known attributes and comparing those patterns to unknown patterns. The data store and comparison processing may be distributed across processors. A digital pattern recognition engine on each of the processors has the ability to compare a known pattern from the data store and an unknown pattern and compare the two patterns to determine whether the patterns constitute a match based on match criteria. If the comparison indicates a match, the match may be communicated to the data store and added as a known pattern with detected attributes to the data store. If the comparison does not indicate a match, the pattern may be flagged, transmitted to manual recognition, or further processed using character thresholding or cutting or slicing the pattern.

Abstract: Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.