Abstract: Methods, systems, apparatuses and program products are disclosed for protecting computers and similar equipment from undesirable occurrences, especially attacks by malware. Invariant information, such as pure code and some data tables may be enrolled for later revalidation by code operating outside the normal context. For example, a periodic interrupt may invoked a system management mode interrupt service routine to discover whether code regions accessible to Protected Mode programs have become corrupted or otherwise changed, such as by tampering from untrusted or untrustworthy programs that have easy access only to protected mode operation.

Abstract: A high-performance-computer system includes a statistics accumulation apparatus configured to efficiently accumulate system performance data from a variety of system components, and periodically write such data to processor local memory for efficient subsequent software processing of the thus acquired data, thereby reducing the system hardware and software overhead needed for collection of such data as compared to prior art systems.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.

Abstract: An electronic apparatus includes a volatile memory, a swap device, and a control unit. The control unit is configured to divide data loaded in the volatile memory between an activation start and a specific time point after the activation start into data used to create a snapshot image and data stored in the swap device.

Abstract: A data processing system 3 employing a coherent memory system comprises multiple main cache memories 8. An inclusive snoop directory memory 14 stores directory lines 22. Each directory line includes a directory tag and multiple snoop vectors. Each snoop vector relates to a span of memory addresses corresponding to the cache line size within the main cache memories 8.

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

Abstract: A hybrid cache includes a static random access memory (SRAM) portion and a resistive random access memory portion. Cache lines of the hybrid cache are configured to include both SRAM macros and resistive random access memory macros. The hybrid cache is configured so that the SRAM macros are accessed before the resistive random memory macros in each cache access cycle. While SRAM macros are accessed, the slower resistive random access memory reach a data access ready state.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.

Abstract: According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2n basic units (n is an integer) among the basic units in the first mode, the read/write of the one bit executed in 2m basic units (m is an integer, m?n) among the basic units in the second mode, and a control circuit which controls the switching between the first and second modes.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data blocks of write data received in the random access memory of the data storage. A storage controller is communicatively coupled to the random access memory and the data storage and being configured to write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses. A method and processor-implemented process provide for sorting data blocks of write data received in random access memory of data storage. The method and processor-implemented process write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses.

Abstract: A method of updating mapping information for a memory system comprises generating write transaction information based on multiple write requests issued by a host, performing program operations in the memory system based on the write transaction information, and following completion of the program operations, updating mapping information based on an order in which the write requests were issued by the host.

Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.

Abstract: A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.

Abstract: Systems and methods may be implemented in a power device subsystem topology to provide an arbitration and communication scheme between a single consolidated non-volatile random access (NVRAM) memory device and multiple discrete digital power controller devices in a manner that provides data protection and the ability to update the full NVRAM content when needed.

Abstract: Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

Abstract: A block storage system includes a host and comprises a block storage module that is coupled to the host. The block storage module includes a MRAM array and a bridge controller buffer coupled to communicate with the MRAM array. The MRAM array includes a buffer widow that is moveable within the MRAM array to allow contents of the MRAM array to be read by the host through the bridge controller buffer even when the capacity of the bridge controller buffer is less than the size of the data being read from the MRAM array.

Abstract: A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item.

Abstract: According to one embodiment, a memory controller includes a mode selection part that selects one of a MLC-mode and a SLC-mode, after a write command is decoded by a command decode part, and a write part that executes a data writing to a storage memory by using one of the MLC-mode and the SLC-mode selected by the mode selection part. The mode selection part is configured to check whether a first data wrote from a host to a buffer memory is a time-continuous data that is wrote continuously during a predetermined period, execute the data writing of a second data from the buffer memory to the storage memory in the MLC-mode, when the first data is the time-continuous data, and execute the data writing of the second data from the buffer memory to the storage memory in the SLC-mode, when the first data is not the time-continuous data.

Abstract: Techniques for escalating a real time agent's request that has an address conflict with a best effort agent's request. A best effort request can be allocated in a memory controller cache but can progress slowly in the memory system due to its low priority. Therefore, when a real time request has an address conflict with an older best effort request, the best effort request can be escalated if it is still pending when the real time request is received at the memory controller cache. Escalating the best effort request can include setting the push attribute of the best effort request or sending another request with a push attribute to bypass or push the best effort request.

Abstract: A First-in First-out (FIFO) memory comprising a latch array and a RAM array and operable to buffer data for multiple threads. Each array is partitioned into multiple sections, and each array comprises a section designated to buffer data for a respective thread. A respective latch array section is assigned higher priority to receive data for a respective thread than the corresponding RAM array section. Incoming data for the respective thread are pushed into the corresponding latch array section while it has vacancies. Upon the latch array section becoming empty, incoming data are pushed into the corresponding RAM array section during a spill-over period. The RAM array section may comprise two spill regions with only one active to receive data at a spill-over period. The allocation of data among the latch array and the spill regions of the RAM array can be transparent to external logic.

Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.

Abstract: A system and method for clients, a control module, and storage modules to participate in a unifed address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from the client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address.

Abstract: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

Abstract: A method and a processing device are provided for sequentially aggregating data to a write log included in a volume of a random-access medium. When data of a received write request is determined to be suitable for sequentially aggregating to a write log, the data may be written to the write log and a remapping tree, for mapping originally intended destinations on the random-access medium to one or more corresponding entries in the write log, may be maintained and updated. At time periods, a checkpoint may be written to the write log. The checkpoint may include information describing entries of the write log. One or more of the checkpoints may be used to recover the write log, at least partially, after a dirty shutdown. Entries of the write log may be drained to respective originally intended destinations upon an occurrence of one of a number of conditions.

Abstract: A system and associated method of using may generally have at least a mobile data storage device with a controller directing data to first and second tiers of memory. The first tier of memory can have at least boot data pre-fetched from the second tier of memory with the boot data including at least metadata and personalized user data.

Abstract: In one embodiment, a parallel (e.g., tiered) logging technique is provided to deliver low latency acknowledgements of input/output (I/O) requests, such as write requests, while avoiding loss of data. Write data may be stored (copied) as a log in a portion of a dynamic random access memory and a non-volatile random access memory (NVRAM). The NVRAM may be configured as, e.g., a persistent write-back cache of the node, while parameters of the request may be stored in another portion of the NVRAM configured as the log (NVLog). The write data may be organized into separate variable length blocks or extents and “written back” out-of-order from the write-back cache to storage devices, such as SSDs, e.g., organized into a data container (intended destination of the write request). The write data may be preserved in the NVlog until each extent is safely stored on SSD.

Abstract: An electronic apparatus that includes a controlled device with a plurality of control registers. A data bus is coupled between the controlled device and a processor, and an interface is configured to receive a plurality of portions of data read from or to be written to the plurality of control registers. The electronic apparatus also includes a correlation circuit configured to associate at least some of the plurality of portions of data with respective physical addresses of the plurality of control registers based on respective positions of the respective portions of data within the plurality.

Abstract: Described herein is a system and method for high speed non-volatile random access memory (NVRAM) emulation. The system and method may utilize a primary storage device and a volatile random access memory (RAM) device to emulate NVRAM functionality. The system and method may allocate a range of the primary storage device. The storage capacity or size of the allocated range may correspond or be at least partially based on a storage capacity or size of the volatile RAM device. Data, such as write requests, may be migrated from the primary storage device to the volatile RAM device. In the event of the unavailability, loss of power, or other such circumstances of the volatile RAM device, data from the volatile RAM device may be migrated back to the previously allocated range of the primary storage device.

Abstract: A computer-based system, method and computer program product for generating chronologically based globally unique identifiers.

Abstract: An apparatus and a method capable of selectively extending a memory in a terminal are provided. The apparatus includes a socket unit into which an external memory having a built-in Random Access Memory (RAM) is inserted, and a controller that performs a control operation for moving data stored in a RAM of the terminal to the RAM of the external memory and for securing available space of the RAM of the terminal, when the external memory having the built-in RAM is inserted into the socket unit.

Abstract: Disk-backed array techniques can, in some implementations, help ensure that the arrays contain consistent data. An alert can be provided if it is determined that the data in the array is, or may be, corrupted.

Abstract: Persistent files are copied from persistent memory to volatile memory to yield volatile files. At least some requests to open for writing or to close to writing persistent files are redirected to the corresponding volatile files. Openings to writing and closings to writing of volatile files are tracked to yield a synchronization record. Persistent files are synchronized to volatile files based on the synchronization record.

Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Abstract: Data caching methods and systems are provided. The data cache method loads data into an installation cache and a cache (simultaneously or serially) and returns data from the installation cache when the data has not completely loaded into the cache. The data cache system includes a processor, a memory coupled to the processor, a cache coupled to the processor and the memory and an installation cache coupled to the processor and the memory. The system is configured to load data from the memory into the installation cache and the cache (simultaneously or serially) and return data from the installation cache to the processor when the data has not completely loaded into the cache.

Abstract: A system, method and computer program product to store tag blocks in a tag buffer in order to provide early row-buffer miss detection, early page closing, and reductions in tag block transfers. A system comprises a tag buffer, a request buffer, and a memory controller. The request buffer stores a memory request having an associated tag. The memory controller compares the associated tag to a plurality of tags stored in the tag buffer and issues the memory request stored in the request buffer to either a memory cache or a main memory based on the comparison.

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract: A SOC system includes a central processing unit; a memory management unit receiving a virtual address from the central processing unit and converting the virtual address into a physical address; a main memory implemented by a volatile memory and directly accessed through the physical address converted by the memory management unit; and a storage implemented by a nonvolatile memory separate from the main memory and including a first area directly accessed through the physical address converted by the memory management unit.

Abstract: A deleted cache determining part determines a cache data which is to be deleted from a data storing part in a case where a sum of a data amount of a data which is recorded to the data storing part and a data amount of a cache data which is stored to the data storing part and a data amount of a buffer data which is stored to the storing part is equal to or more than a predetermined threshold, and an accumulated data control part deletes the cache data which is determined by the deleted cache determining part from the data storing part.

Abstract: An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard.

Abstract: A setting control apparatus includes a setting control part, a special register, and a read-out control part. The setting control part makes stored in a temporary storage part a control value used in a processing circuit, in response to an input of the control value. The special register is electrically connected to the processing circuit and serving as a storage element capable of storing the control value. The read-out control part controls a read-out operation for reading out the control value from the temporary storage part into the special register. The read-out control part performs the read-out operation at a predetermined timing after storing of the control value in the temporary storage part is completed.

Abstract: An information processing apparatus has a task area unit as an area that executes a predetermined process, a power control unit that reads a task area to execute the process from the process and supplies power from a power source to the read task area, and a control unit that executes the process in the task area unit to which the power is supplied by the power control unit.

Abstract: A method for optimizing performance of programs has steps for scanning storage mechanisms of the computing appliance by executing a configuration utility by a Central Processing Unit (CPU) of the computing appliance to find and identify installed programs, comparing the determined installed programs to a database (dB) of information and files prepared to optimize performance of specific programs through caching, and determining matches between the installed programs and specific programs having information and files in the dB, selecting installed programs to optimize for performance, partitioning a portion of system RAM of the computing appliance as cache, and loading information and files from local storage mechanisms for each program selected to the cache partitioned in system RAM, enabling the programs selected to at least read data in operation from the cache portion partitioned in system RAM.

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.

Abstract: A static read-only memory (SRAM) includes one or more bit cell rows that each includes a collection of bit cells. Each bit cell row is coupled to two or more different wordlines, where each wordline associated with a given bit cell row provides memory access to a different subset of bit cells within that bit cell row.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Methods and systems are provided that may include a memory device having a physical nonvolatile memory, a memory space, and a controller. At least a portion of a physical nonvolatile memory may permit a direct read operation of the physical nonvolatile memory and prohibit a direct write operation of the physical nonvolatile memory. A memory space may comprise at least open one write overlay window available after a reset operation. Such a memory space may be adapted to permit at least one read overlay window to be opened that is logically separate from at least one open write overlay window. A controller may be included to open at least one read overlay window.

Abstract: Systems and methods are used to manage the contents of NVRAM in a wagering game machine. NVRAM may be pre-allocated for various purposes prior to loading a first wagering game on a the wagering game machine. A second wagering may be loaded on the wagering game machine. The second wagering game reuses the pre-allocated NVRAM portions for the same purposes as the first wagering game.

Abstract: Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance.

Abstract: A computer system has a random access memory (RAM) that stores currently used memory pages and SWAP storage for storing memory page that is not in use. If the process requires memory page stored on the SWAP storage, a corresponding page is loaded to RAM. If the page in RAM is not currently in use, it is moved to the SWAP storage. The computer system has a number of Virtual Environments (i.e., Containers) that run their own processes, a VE/Container RAM and a virtual SWAP storage. The Container processes have access to a VE/Container RAM. When the Container process request OS for memory, the memory manager allocates memory pages in the RAM and also allocates memory pages for the Container process in the VE/Container RAM. If no free virtual RAM is available, the process data is moved to the virtual SWAP storage.

Abstract: Methods and systems for mass storage of data over two or more tiers of mass storage media that include nonvolatile solid-state memory devices, hard disk devices, and optionally volatile memory devices or nonvolatile MRAM in an SDRAM configuration. The mass storage media interface with a host through one or more PCIe lanes on a single printed circuit board.