Parallel Caches Patents (Class 711/120)
  • Patent number: 10528275
    Abstract: A storage system includes a first storage control device including a first memory being a volatile memory and a first processor, and a second storage control device including a second memory being a non-volatile memory and a second processor, wherein the second processor is configured to receive a first write request to write first data into a first storage device, store the first data into the second memory, and transmit the first data to the first storage control device, the first processor is configured to store the first data into the first memory, and transmit a first notification to the second storage control device, and the second processor is configured to receive the first notification, transmit a first completion notification in response to the first write request, and execute processing to write the first data, stored in the second memory, into the first storage device.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 7, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiko Suzuki
  • Patent number: 10521357
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: December 31, 2019
    Assignee: Mellanox Technologies Ltd.
    Inventors: Carl G. Ramey, Patrick Robert Griffin
  • Patent number: 10503645
    Abstract: A method for providing fast access, the method may include obtaining, by a first storage controller of a storage system, retrieval information for retrieving, from a permanent storage space, a subset of cached data units, the subset of the cached data units forms a part of a set of cached data units that are cached in a first cache memory and were destaged to the permanent storage space; and retrieving, using the retrieval information, at least some of the cached data units of the subset from the permanent storage space to a second cache memory, wherein the retrieving occurs in response to an occurrence of a failure to access the first cache memory; wherein the second cache memory differs from the first cache memory.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 10, 2019
    Assignee: INFINIDAT LTD.
    Inventors: Kariel Sandler, Jacob Broido
  • Patent number: 10503640
    Abstract: A processor includes multiple processing units (e.g., processor cores), with each processing unit associated with at least one private, dedicated cache. The processor is also associated with a system memory that stores all data that can be accessed by the multiple processing units. A coherency manager (e.g., a coherence directory) of the processor enforces a specified coherency scheme to ensure data coherency between the different caches and between the caches and the system memory. In response to a memory access request to a given cache resulting in a cache miss, the coherency manager identifies the current access latency to the system memory as well as the current access latencies to other caches of the processor. The coherency manager transfers the targeted data to the given cache from the cache or system memory having the lower access latency.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: December 10, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Yasuko Eckert
  • Patent number: 10503641
    Abstract: A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 10, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael W. Boyer, Nuwan Jayasena
  • Patent number: 10453501
    Abstract: An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 22, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang, Yu Meng, Yunxiang Wu
  • Patent number: 10445102
    Abstract: Systems, apparatuses, and methods for efficient program flow prediction. After receiving a current fetch address, a first predictor performs a lookup of a first table. When the lookup results in a miss and the first table has no available entries, the first predictor overwrites a given entry of the first table with the received fetch address, in response to detecting a strength value for the given entry is below a threshold. Otherwise, in response to detecting no entries of the first table have a strength value below the threshold, the first predictor allocates an entry in the second table for the received fetch address. When an indication of a target address for the received fetch address is a return address for a function call, a third predictor allocates an entry of a third table with the received fetch address.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: October 15, 2019
    Assignee: Apple Inc.
    Inventors: Constantin Pistol, Ian D. Kountanis
  • Patent number: 10387314
    Abstract: A directory structure that may allow concurrent processing of write-back and clean victimization requests is disclosed. The directory structure may include a memory configured to store a plurality of entries, where each entry may include information indicative of a status of a respective entry in a cache memory. Update requests for the entries in the memory may be received and stored. A subset of previously stored update requests may be selected. Each update request of the subset of the previously stored update requests may then be processed concurrently.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: August 20, 2019
    Assignee: Oracle International Corporation
    Inventors: Thomas Wicki, Jurgen Schulz, Paul Loewenstein
  • Patent number: 10372602
    Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 6, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Sanketh Nalli, Haris Volos, Kimberly Keeton
  • Patent number: 10346387
    Abstract: A method includes a primary storage unit receiving a first write request including a first key and a first value; persisting the first value in a first non-volatile memory in association with the first key; broadcasting the first write request and a first set of globally-durable keys to secondary storage units; receiving, from the secondary storage units, an acknowledgement of the first write request and a first set of locally-durable keys, each of the first sets of locally-durable keys including the first key; the primary storage unit receiving a second write request including a second key and a second value; persisting the second value in the first non-volatile memory in association with the second key; and broadcasting the second write request and a second set of globally-durable keys to the secondary storage units, the second set of locally-durable keys including the first key. A system is also disclosed.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 9, 2019
    Assignee: SAP SE
    Inventors: Peter Bumbulis, Jeffrey Pound, Nathan Auch, Anil Kumar Goel, Matthias Ringwald, Thomas Bodner, Scott MacLean
  • Patent number: 10338813
    Abstract: The present invention provides a storage controller and a using method therefor. The method comprises: processors send a storage instruction; a processor controller receives the storage instructions sent by the processors, and sends the storage instructions to an exchanger; the exchanger sends the storage instructions to a hard disk controller one by one; and the hard disk controller sends the storage instructions to a hard disk according to storage address spaces indicated in the storage instructions, the indicated address spaces being address spaces allocated to the processors sending the storage instructions. By using the technical scheme of the present invention, multiplexing of the same physical storage space for the storage instructions of multiple processors can be ensured in a time-sharing mechanism, and accordingly, a purpose that the multiple processors share the same physical storage space by means of hardware is achieved.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: July 2, 2019
    Assignees: Dawning Cloud Computing Group Co., Ltd, Dawning Information Industry (Beijing) Co., Ltd
    Inventors: Hua Nie, Xiaojun Yang, Yalu Ni
  • Patent number: 10318428
    Abstract: A multi-core processing chip where the last-level cache functionality is implemented by multiple last-level caches (a.k.a. cache slices) that are physically and logically distributed. The hash function used by the processors on the chip is changed according to which of last-level caches are active (e.g., ‘on’) and which are in a lower power consumption mode (e.g., ‘off’.) Thus, a first hash function is used to distribute accesses (i.e., reads and writes of data blocks) to all of the last-level caches when, for example, all of the last-level caches are ‘on.’ A second hash function is used to distribute accesses to the appropriate subset of the last-level caches when, for example, some of the last-level caches are ‘off.’ The chip controls the power consumption by turning on and off cache slices based on power states, and consequently dynamically switches among at least two hash functions.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 11, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Patrick P. Lai, Robert Allen Shearer
  • Patent number: 10275280
    Abstract: A plurality of cores are maintained in a processor complex. A core of the plurality of cores is reserved for execution of critical tasks, wherein it is preferable to prioritize execution of critical tasks over non-critical tasks. A scheduler receives a task for scheduling in the plurality of cores. In response to determining that the task is a critical task, the task is scheduled for execution in the reserved core.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Clint A. Hardy, Trung N. Nguyen
  • Patent number: 10216651
    Abstract: The invention is directed to a primary data storage system for use in a computer network in which a network allows user computers to transfer data to/from the primary data storage system. In one embodiment, the primary data storage system implements a tiering strategy to move data between stores with different characteristics so as to match the characteristics of the data to the characteristics of one of the stores.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: February 26, 2019
    Assignee: NexGen Storage, Inc.
    Inventors: Paul A. Ashmore, Kelly E. Long, Sebastian Piotr Sobolewski
  • Patent number: 10198356
    Abstract: A separate distributed buffer cache system may be implemented for a storage client of a distributed storage system. Storage I/O requests may be sent from a storage client to one or more buffer cache nodes in a distributed buffer cache system that maintain portions of an in-memory buffer cache to which the requests pertain. The distributed buffer cache system may send the write requests on to the distributed storage system to be completed, and in response to receiving acknowledgements from the storage system, sending a completion acknowledgement back to the storage client. Buffer cache nodes may update buffer cache entries for received requests such that they are not available for reads until complete at the distributed storage system. For read requests where the buffer cache entries at the buffer cache node are invalid, valid data may be obtained from the distributed storage system and sent to the storage client.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: February 5, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Anurag Windlass Gupta, Matthew David Allen
  • Patent number: 10188815
    Abstract: A laryngeal mask including a rigid hollow tube essentially in the form of a “J”, and which has a lengthwise opening along its entire length, and a flexible tube, also essentially in the form of a “J”, configured to be housed in the lengthwise opening of the rigid hollow tube, and which can be separated from it. This provides a configuration for a laryngeal mask that can change from having rigid properties to flexible ones at the doctor's will, without the need to interrupt the patient's supply of oxygen at any time.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 29, 2019
    Assignee: Medcom Flow S.A.
    Inventors: Juan Sagalés Mañas, Alejandro Roca De Viñals Delgado, Alberto Calaf Alcalde
  • Patent number: 10180906
    Abstract: A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tyler Stocksdale, Mu-Tien Chang, Hongzhong Zheng
  • Patent number: 10170170
    Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 1, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
  • Patent number: 10152412
    Abstract: Techniques herein are for chaining nonvolatile storage devices to achieve high availability. A method involves a storage server receiving a write request to store data blocks in a first nonvolatile memory device. The storage server comprises a plurality of nonvolatile memory devices that cache data blocks stored on primary storage. The plurality of nonvolatile memory devices comprises the first nonvolatile memory device. The storage server maintains a cache index of data blocks that reside in the plurality of nonvolatile memory devices. Based on one or more criteria, the storage server reroutes the write request to a second nonvolatile memory device of the plurality of nonvolatile memory devices and stores an identifier of the second nonvolatile memory device in the cache index.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: December 11, 2018
    Assignee: Oracle International Corporation
    Inventors: Selcuk Aya, Jia Shi, Kothanda Umamageswaran, Juan Loaiza
  • Patent number: 10140157
    Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: November 27, 2018
    Assignee: Apple Inc.
    Inventors: Russell A. Blaine, Daniel A. Chimene, Shantonu Sen, James M. Magee
  • Patent number: 10120804
    Abstract: Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are maintained for a transaction. The indication(s) are stored in cache. In addition, a queue(s) of at least one address corresponding to a speculatively executed instruction is maintained. For a received request from a processor, a transaction resolution process takes place, and a resolution is performed if an address match in the queue is detected. The resolution includes to hold a response to the receive request until the speculative instruction is committed or flushed.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 10067872
    Abstract: A plurality of memory modules, which may be used to form a heterogeneous memory system, are connected to a plurality of prefetchers. Each prefetcher is independently configured to prefetch information from a corresponding one of the plurality of memory modules in response to feedback from the corresponding one of the plurality of memory modules.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: September 4, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David A. Roberts
  • Patent number: 10049055
    Abstract: Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 14, 2018
    Assignee: VIRIDIENT SYSTEMS, INC
    Inventors: Shibabrata Mondal, Vijay Karamcheti, Ankur Arora, Ajit Yagaty
  • Patent number: 10025711
    Abstract: Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Peter G. Sassone, Christopher Edward Koob, Dana M. Vantrease, Suresh K. Venkumahanti, Lucian Codrescu
  • Patent number: 10019362
    Abstract: An example method for using a plurality of SSDs as a caching medium in a data storage system can include splitting the SSDs into a plurality of cache regions, maintaining a first cache region of the SSDs as a read cache and maintaining a second cache region of the SSDs as a write cache. Additionally, read data can be stored by striping the read data across the SSDs in the first cache region, and dirty write data can be stored by mirroring the dirty write data across the SSDs in the second cache region. The computer-implemented method can also include dynamically adjusting a size of at least one of the first and second cache regions of the SSDs based on an input/output (“I/O”) load of the data storage system.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: July 10, 2018
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Srikumar Subramanian, Sankarji Gopalakrishnan, Senthilkumar Ramasamy
  • Patent number: 9952974
    Abstract: A dual-server based storage system maintains a first cache and a first non-volatile storage (NVS) in a first server, and a second cache and a second NVS in a second server, where data in the first cache is also written in the second NVS and data in the second cache is also written in the first NVS. In response to a failure of the first server, a determination is made as to whether space exists in the second NVS to accommodate the data stored in the second cache. In response to determining that space exists in the second NVS to accommodate the data stored in the second cache, the data is transferred from the second cache to the second NVS.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 9916241
    Abstract: Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: March 13, 2018
    Assignee: NetApp, Inc.
    Inventors: Brian McKean, Gregory Friebus, Sandeep Kumar R. Ummadi, Pradeep Ganesan
  • Patent number: 9904552
    Abstract: An out of order processor. The processor includes a distributed load queue and a distributed store queue that maintain single program sequential semantics while allowing an out of order dispatch of loads and stores across a plurality of cores and memory fragments; wherein the processor allocates other instructions besides loads and stores beyond the actual physical size limitation of the load/store queue; and wherein the other instructions can be dispatched and executed even though intervening loads or stores do not have spaces in the load store queue.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 9888062
    Abstract: A distributed storage system including a plurality of proxy server and a method for managing objects. The distributed storage system may include a plurality of data nodes, a plurality of proxy server, and a global load balancer. Each one of the plurality of data nodes may be configured to perform at least one management operation and output an operation result. Each one of the plurality of proxy servers may be configured to perform operations for controlling the plurality of data nodes to perform the at least one management operation in response to an operation request from a respective client. The global load balancer may be configured to select one proxy server from the plurality of proxy servers and allocate the selected proxy server to the respective client as the responsible proxy server. The respective client may perform the management operation through the allocated responsible proxy server.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: February 6, 2018
    Assignee: KT CORPORATION
    Inventors: Mi-Jeom Kim, Hyo-Min Kim, Chang-Sik Park, Jin-Kyung Hwang
  • Patent number: 9852074
    Abstract: Various exemplary embodiments relate to a system for hashing a value into a cache, the system including a processor for performing a series of instructions; a memory; and the cache including a plurality of slots, each slot including two locations to store values, each location comprising a tag value and an index, the cache in communication with the memory and the processor, the cache configured to calculate a target slot in the cache for an object, determine if a location is available, store a characteristic of the object in the index of the location, and update the tag value of the location.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: December 26, 2017
    Assignee: Alcatel Lucent
    Inventor: Jeroen van Bemmel
  • Patent number: 9846648
    Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Daniel Greenspan, Anant V. Nori, Supratik Majumder, Yoav Lossin, Asaf Rubinstein
  • Patent number: 9830162
    Abstract: Technologies for indirect branch target security include a computing device having a processor to execute an indirect branch instruction. The processor may determine an indirect branch target of the indirect branch instruction, load a memory tag associated with the indirect branch target, and determine whether the memory tag is set. The processor may generate a security fault if the memory tag is not set. The processor may load an encrypted indirect branch target, decrypt the encrypted branch target using an activation record key stored in an activation key register, and perform a jump to the indirect branch target. The processor may generate a next activation record coordinate as a function of the activation record key and a return address of a call instruction and generate the next activation record key as a function of the next activation record coordinate. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventor: Michael LeMay
  • Patent number: 9824030
    Abstract: Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Will A. Wright
  • Patent number: 9824012
    Abstract: Providing coherent merging of committed store queue entries in unordered store queues of block-based computer processors is disclosed. In one aspect, a block-based computer processor provides a merging logic circuit communicatively coupled to an unordered store queue and cache memory. The merging logic circuit is configured to select a first store queue entry in the unordered store queue, and read its memory address, an age indicator, and a data value. The age indicator and the data value are stored in merged data bytes within a merged data buffer. The merging logic circuit then locates a remaining store queue entry having a memory address identical to the first selected store queue entry, and reads its age indicator and data value. Based on the age indicator and one or more age indicators of the merged data bytes within the merged data buffer, the data value is merged into the merged data buffer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Gregory Michael Wright
  • Patent number: 9823730
    Abstract: A method and apparatus for power management of cache duplicate tags is disclosed. An IC includes a cache, a coherence circuit, and a duplicate tags memory that may store duplicates of the tags stored in the cache. The cache includes a number of ways that are separately and independently power controllable. The duplicate tags memory may be similarly organized, with portions that are power controllable separately and independently of others. The coherence circuit is also power controllable, and may be placed into a sleep mode when idle. The IC also includes a power management circuit. During operation, the cache may change power states and provide a corresponding indication to the power management circuit. Responsive to the indication, the power management circuit may awaken the coherence circuit if in a sleep state. The coherence circuit may then power manage the duplicate tags in accordance with the change in power state.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: November 21, 2017
    Assignee: Apple Inc.
    Inventors: Muditha Kanchana, Erik P. Machnicki
  • Patent number: 9811474
    Abstract: Provided are a computer program product, system, and method for determining cache performance using a ghost cache list. Tracks in the cache are indicated in a cache list. A track demoted from the cache is indicated in a ghost cache list in response to demoting the track in the cache. The demoted track is not indicated in the cache list. During caching operations, information is gathered on a number of cache hits comprising accesses to tracks indicated in the cache list and a number of ghost cache hits comprising accesses to tracks indicated in the ghost cache list. The gathered information on the cache hits and the ghost cache hits is used to generate information on cache performance improvements that would occur if the cache was increased in size to cache tracks in the ghost cache list.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Juan A. Yanes
  • Patent number: 9792050
    Abstract: Example distributed caching systems and methods are described. In one implementation, a system has multiple host systems, each of which includes a cache resource that is accessed by one or more consumers. A management server is coupled to the multiple host systems and presents available cache resources and resources associated with available host systems to a user. The management server receives a user selection of at least one available cache resource and at least one host system. The selected host system is then configured to share the selected cache resource.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: October 17, 2017
    Assignee: PernixData, Inc.
    Inventors: Michal Ostrowski, Akhilesh Joshi, Deepak Muley, Satyam Vaghani, Bryan Jeffrey Crowe, Shyan-Ming Perng
  • Patent number: 9792211
    Abstract: Providing coherent merging of committed store queue entries in unordered store queues of block-based computer processors is disclosed. In one aspect, a block-based computer processor provides a merging logic circuit communicatively coupled to an unordered store queue and cache memory. The merging logic circuit is configured to select a first store queue entry in the unordered store queue, and read its memory address, an age indicator, and a data value. The age indicator and the data value are stored in merged data bytes within a merged data buffer. The merging logic circuit then locates a remaining store queue entry having a memory address identical to the first selected store queue entry, and reads its age indicator and data value. Based on the age indicator and one or more age indicators of the merged data bytes within the merged data buffer, the data value is merged into the merged data buffer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 17, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Gregory Michael Wright
  • Patent number: 9684593
    Abstract: Techniques are described for storing data. A command is issued from a client to a data storage system. The data storage system includes a plurality of storage tiers comprising a first storage tier of physical storage devices and a second storage tier of physical storage devices, wherein data stored on any physical storage device of the first storage tier is stored in an encrypted form and data stored on any physical storage device of the second storage tier is not stored in an encrypted form. The command includes a hint indicating whether data stored at a first logical address range of a first logical device is stored in an encrypted form. The command is received at the data storage system. First data written to the first logical device at the first logical address range is stored on one or more physical storage devices of any of said first storage tier and said second storage tier in accordance with the hint.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 20, 2017
    Inventors: Xiangping Chen, Xuan Tang, Qin Tao
  • Patent number: 9588898
    Abstract: A data storage system incorporating a write-caching subsystem that implements a steady-state media-based cache is described. The steady-state of the media-based cache can be obtained by directing non-sequential write commands and data received from the host device to multiple independent cache locations and, thereafter, selectively copying or moving such data between the caches so that none of the caches are either too full or too empty. In this manner, a non-sequential write command can be cached in a power-safe manner until it is efficient and/or convenient to write such data to the mainstore portion of the physical media.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: March 7, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Wayne H. Vinson, Robert Brummet
  • Patent number: 9588896
    Abstract: A computer includes a first memory, a second memory having an I/O speed lower than an I/O speed of the first memory, a storage device, and a processor. The first memory has a work area and a first cache area where data input to and output from the storage device is temporarily stored and the second memory has a second cache area where the data input to and output from the storage device is temporarily stored and a swap area to be a saving destination of data stored in the work area. The processor reduces the work area and expands the first cache area, when an input/output amount to be an amount of data input to and output from the storage device is larger than a predetermined input/output amount.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 7, 2017
    Assignee: HITACHI, LTD.
    Inventor: Aritoki Takada
  • Patent number: 9582425
    Abstract: A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state signal including a different number of states. A set status of a set-associative storage container in a computer system is determined. The set status identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Adam B. Collura
  • Patent number: 9584617
    Abstract: Various embodiments of the present disclosure provide improved systems and techniques for intelligently allocating cache requests to caches based upon the nature of the cache objects associated with the cache requests, and/or the condition of the caches in the distributed cache system, to facilitate cache system utilization and performance. In some embodiments, an allocation of cache requests may be performed in response to detection of a problem at one of a group of cache servers. For example, in some embodiments, a particular cache server may be entered into a safe mode of operations when the cache's ability to service cache requests is impaired. In other embodiments, an allocation of cache requests may be performed based on an cache object data type associated with the cache requests.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 28, 2017
    Assignee: SUCCESSFACTORS, INC.
    Inventors: Xiao Han, Kun Liu, Peter Zhao, Edward Lu, Jessica Yang, Tim Ke
  • Patent number: 9575692
    Abstract: The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: February 21, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Ho Han, Young Su Kwon
  • Patent number: 9547552
    Abstract: A system and method for maintaining operation of a storage array with one or more failed storage devices and for quickly recovering when failing devices are replaced are provided. In some embodiments, the method includes receiving a data transaction directed to a volume and determining that a storage device associated with the volume is inoperable. In response to determining that the storage device is inoperable, a data extent is recorded in a change log in a storage controller cache. The data extent is associated with the data transaction and allocated to the storage device that is inoperable. The data transaction is performed using at least one other storage device associated with the volume, and data allocated to the storage device is subsequently reconstructed using the recorded data extent.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: January 17, 2017
    Assignee: NetApp, Inc.
    Inventors: Theresa L. Segura, Wei Sun, Martin Parrish, Donald R. Humlicek
  • Patent number: 9544755
    Abstract: In an example embodiment, a method includes determining, by an apparatus, whether the apparatus provides data for other wireless devices to request from the apparatus in response to wireless device discovery messages transmitted by the apparatus; and transmitting, by the apparatus, wireless device discovery messages including an indication that additional information should not be requested from the apparatus in response to the wireless device discovery messages, without establishing a connection with the apparatus, the indication being in response to the determination that the apparatus does not provide data for other wireless devices to request from the apparatus in response to the wireless device discovery messages.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 10, 2017
    Assignee: Nokia Technologies Oy
    Inventors: Arto Palin, Jukka Reunamaki, Tapani Mikola, Juha Salokannel
  • Patent number: 9529759
    Abstract: Multipath I/O in a computer system includes: receiving asynchronously, for a single I/O operation by a memory controller from a plurality of I/O adapters, a request to access a memory page, where each request to access the memory page includes an adapter-specific tag; and for each request received by the memory controller: determining, by the memory controller, whether an adapter-specific tag has been assigned to the memory page; if an adapter-specific tag has not been assigned to the memory page: assigning, by the memory controller, the received adapter-specific tag to the memory page; and allowing, by the memory controller, access to the memory page; and if an adapter-specific tag has been assigned to the memory page, granting access to the memory page only when the received adapter-specific tag is the adapter-specific tag assigned to the memory page.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Hart, Anil Kalavakolanu, James A. Pafumi, Vani D. Ramagiri, Evelyn T. Yeung
  • Patent number: 9524171
    Abstract: A split level history buffer in a central processing unit is provided. A history buffer is split into a first portion and a second portion. An instruction fetch unit fetches and tags instructions with unique tags. A register file stores tagged instructions. An execution unit generates results for tagged instructions. A first instruction is fetched, tagged, and stored in an entry of the register file. A second instruction is fetched and tagged, and then evicts the first instruction from the register file, such that the second instruction is stored in the entry of the register file. Subsequently, the first instruction is stored in an entry in the first portion of the history buffer. After a result for the first instruction is generated, the first instruction is moved from the first portion of the history buffer to the second portion of the history buffer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: December 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 9495300
    Abstract: A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state signal including a different number of states. A set status of a set-associative storage container in a computer system is determined. The set status identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Adam B. Collura
  • Patent number: 9491099
    Abstract: A method and a system embodying the method for information lookup request processing at a look-aside processor unit entailing storing a received lookup transaction request in a first buffer; rebuilding the lookup transaction request into a request packet; transmitting the request packet; receiving a packet; determining whether the received packet is a response packet or an exception packet; and processing the received packet in accordance with the determining is disclosed. Furthermore, a method and a system embodying the method for exception packet processing at a look-aside processor unit entailing storing at least one received lookup transaction request in a first buffer; receiving a packet; determining that the received packet is an exception packet; and associating the exception packet with one of the at least one stored lookup transaction request in accordance with an identifier of the first buffer is disclosed.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 8, 2016
    Assignee: Cavium, Inc.
    Inventors: Wilson Parkhurst Snyder, II, Steven Craig Barner, Richard Eugene Kessler