Hierarchical Caches Patents (Class 711/122)
  • Patent number: 11893423
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 6, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Sonata Gale Wen, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Patent number: 11886345
    Abstract: Configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system is disclosed. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. In response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventor: Burkhard Steinmacher-Burow
  • Patent number: 11868260
    Abstract: A method of caching large data objects of greater than 1 GB, comprising: populating a sharded cache with large data objects backfilled from a data store; servicing large data object requests from a plurality of worker nodes via the sharded cache, comprising deterministically addressing objects within the sharded cache; and if a number of requests for an object within a time exceeds a threshold: after receiving a request from a worker node for the object, sending the worker node a redirect message directed to a hot cache, wherein the hot cache is to backfill from a hot cache backfill, and wherein the hot cache backfill is to backfill from the sharded cache.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 9, 2024
    Assignee: GM CRUISE HOLDINGS LLC
    Inventors: Hui Dai, Seth Alexander Bunce
  • Patent number: 11868263
    Abstract: A microprocessor includes a virtually-indexed L1 data cache that has an allocation policy that permits multiple synonyms to be co-resident. Each L2 entry is uniquely identified by a set index and a way number. A store unit, during a store instruction execution, receives a store physical address proxy (PAP) for a store physical memory line address (PMLA) from an L1 entry hit upon by a store virtual address, and writes the store PAP to a store queue entry. The store PAP comprises the set index and the way number of an L2 entry that holds a line specified by the store PMLA. The store unit, during the store commit, reads the store PAP from the store queue, looks up the store PAP in the L1 to detect synonyms, writes the store data to one or more of the detected synonyms, and evicts the non-written detected synonyms.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 9, 2024
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, Srivatsan Srinivasan, Robert Haskell Utley
  • Patent number: 11868644
    Abstract: In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: January 9, 2024
    Assignee: VMWARE, INC.
    Inventors: Andreas Georg Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Adarsh Seethanadi Nayak, Nishchay Dua
  • Patent number: 11847008
    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: David Hunt, Niall Power, Kevin Devey, Changzheng Wei, Bruce Richardson, Eliezer Tamir, Andrew Cunningham, Chris MacNamara, Nemanja Marjanovic, Rory Sexton, John Browne
  • Patent number: 11797206
    Abstract: Embodiments for migrating hash values for backup data blocks in a network of data protection targets (DPTs) and a common data protection target implementing a Gold image library management system in which backups of Gold images used as templates for physical machines and virtual machines are stored on the CDPT. The CDPT and each DPT stores backup data split into chunks that are uniquely identified by a respective hash of its contents, and maintains data structures comprising the hash, chunk size, chunk data, and a list of DPT and CDPT identifiers. The hashes are partitioned into a set of buckets in the CDPT. A Bloom filter is generated for each bucket of hashes, and stored in each DPT so that each DPT stores Bloom filters for all CDPTs in the network. Each DPT checks its list of hashes against the Bloom filters in each of the DPTs to determine whether to keep or free chunks of data.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 24, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Arun Murti, Mark Malamut, Stephen Smaldone
  • Patent number: 11768777
    Abstract: Methods, apparatus, and processor-readable storage media for application aware cache management are provided herein. An example computer-implemented method includes maintaining a data structure comprising at least one entry indicative of an importance of at least one of a plurality of applications associated with a storage system; and controlling whether or not a particular data item requested by one of the plurality of applications is cached in a cache memory of the storage system based at least in part on the at least one entry of the data structure.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: September 26, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Jai P. Gahlot, Shiv S. Kumar
  • Patent number: 11748262
    Abstract: Techniques for implementing an apparatus, which includes a memory system that provides data storage via multiple hierarchical memory levels, are provided. The memory system includes a cache that implements a first memory level and a memory array that implements a second memory level higher than the first memory level. Additionally, the memory system includes one or more memory controllers that determine a predicted data access pattern expected to occur during an upcoming control horizon, based at least in part on first context of first data to be stored in the memory sub-system, second context of second data previously stored in the memory system, or both, and control what one or more memory levels of the multiple hierarchical memory levels implemented in the memory system in which to store the first data, the second data, or both based at least in part on the predicted data access pattern.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Anton Korzh
  • Patent number: 11748263
    Abstract: Improvements to internet cache protocols are disclosed. In certain embodiments, a client-facing proxy server can query peer servers to determine whether they have a copy of an object that the proxy server needs. The peer servers can respond based on object information that the peer servers stored about objects they have in cache, where the peers recorded such object information previously when ingesting the objects into their cache and stored it separately from the objects for fast access (e.g. in RAM vs. on disk). This information can be expressed in a compact way using just a few object flags, and enables the peer server to quickly respond and with detail about the status of objects they hold. The proxy server can make an intelligent decision about which peer to use, and indeed whether to use a peer at all.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: September 5, 2023
    Assignee: Akamai Technologies, Inc.
    Inventors: Dmitry Sotnikov, Denis Emelyanov, Dvir Tuberg, Arnon Shoshany, Michael Hakimi, Kfir Zigdon
  • Patent number: 11724714
    Abstract: Systems and methods for autonomous vehicle state management are provided. An offboard state service can obtain a vehicle command associated with changing an onboard-defined state of an autonomous vehicle. Data indicative of the command can be provided to a computing system onboard the autonomous vehicle. The onboard computing system can initiate a vehicle action in accordance with the command and provide a command response indicative of an updated vehicle status for the onboard-defined state to the state service. In response, the state service can update a current status for the onboard-defined state as represented by a vehicle profile corresponding to the autonomous vehicle. The state service can generate an update event indicative of the vehicle state and the updated current status and publish the update event to a distributed event stream such that a number of devices subscribed to the event stream can receive data indicative of the update event.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 15, 2023
    Assignee: Uber Technologies, Inc.
    Inventor: Zelin Liu
  • Patent number: 11698893
    Abstract: In accordance with an embodiment, described herein is a system and method for use of lock-less data structures and processes with a multidimensional database computing environment. Lock-less algorithms or processes can be implemented with specific hardware-level instructions so as to provide atomicity. A memory stores an index cache retaining a plurality of index pages of the multidimensional database. A hash table indexes index pages in the index cache, wherein the hash table is accessible by a plurality of threads in parallel through application of the lock-less process.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: July 11, 2023
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Young Joon Kim, Vilas Ketkar, Shubhagam Gupta, Haritha Gongalore
  • Patent number: 11687497
    Abstract: An overlay network is augmented to provide more efficient data storage by processing a dataset of high dimension into an equivalent dataset of lower dimension, wherein the data reduction reduces the amount of actual physical data but not necessarily its informational value. Data to be processed (dimensionally-reduced) is received by an ingestion layer and supplied to a learning-based storage reduction application that implements the data reduction technique. The application applies a data reduction algorithm and stores the resulting dimensionally-reduced data sets in the native data storage or third party cloud. To recover the original higher-dimensional data, an associated reverse algorithm is implemented. In general, the application coverts an N dimensional data set to a K dimensional data set, where K<<N. The N dimensional dataset has a high dimension, and the K dimensional dataset has a low dimension.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: June 27, 2023
    Assignee: Akamai Technologies Inc.
    Inventor: Indrajit Banerjee
  • Patent number: 11687378
    Abstract: Embodiments include a multi-tenant cloud system that receives a request for an authenticate action for a user. Embodiments create an authenticate target action and register a cache listener for a cache that includes a filter to listen for a target action response that is responsive to the authenticate target action, the filter listing a plurality of bridges assigned to an on-premise active directory. Embodiments randomly select one of the plurality of bridges and sends the authenticate target action to the active directory via the selected bridge. Embodiments wait for a cache callback and, at the cache callback, receive a target action response that includes a result of the authenticate action.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: June 27, 2023
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Ashish Bhargava, Gary Cole, Gregg Wilson
  • Patent number: 11688122
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Devan Burke, Adam T. Lake, Jeffery S. Boles, John H. Feit, Karthik Vaidyanathan, Abhishek R. Appu, Joydeep Ray, Subramaniam Maiyuran, Altug Koker, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Eric J. Hoekstra, Gabor Liktor, Jonathan Kennedy, Slawomir Grajewski, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 11653035
    Abstract: Systems, methods, and devices of the various embodiments disclosed herein may provide a protocol and architecture for decentralization of content delivery. Various embodiments may provide a client based method for content delivery from content delivery networks (CDNs) via tiered caches of content hosted by Internet Service Providers (ISPs). In various embodiments, content delivery protocol (CDP) messages may enable clients to discover local cache network topologies and request content from a CDN based on a discovered local cache network topology. In various embodiments, security may be provided for the content delivery by the use of key encryption and/or file hashing.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: May 16, 2023
    Assignee: Charter Communications Operating, LLC
    Inventor: Jody Lee Beck
  • Patent number: 11641337
    Abstract: This document relates to a CDN balancing mitigation system. An implementing CDN can deploy systems and techniques to monitor the domains of content provider customers with an active DNS scanner and detect which are using other CDNs on the same domain. This information can be used as an input signal for identifying and implementing adjustments to CDN configuration. Both automated and semi-automated adjustments are possible. The system can issue configuration adjustments or recommendations to the implementing CDN's servers or to its personnel. These might include “above-SLA” treatments intended to divert traffic to the implementing CDN. The effectiveness can be measured with the multi-CDN balance subsequently observed. The scanning and adjustment workflow can be permanent, temporary, or cycled. Treatments may include a variety of things, such as more cache storage, routing to less loaded servers, and so forth.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: May 2, 2023
    Assignee: Akamai Technologies, Inc.
    Inventors: Martin T. Flack, Utkarsh Goel
  • Patent number: 11636115
    Abstract: A system comprises a data source storing data, a data processing unit (DPU) comprising an integrated circuit having programmable processor cores and a hardware-based regular expression (RegEx) engine, and a control node configured to generate a data flow graph for configuring the DPUs to execute the analytical operation to be performed on the data. The analytical operation specifies a query having at least one query predicate. A controller is configured to receive the data flow graph and, in response, configures the DPU to input the data as one or more data streams, and configure the RegEx engine to operate according to one or more deterministic finite automata (DFAs) or non-deterministic finite automata (NFAs) to evaluate the query predicate against the data by applying one or more regular expressions to the one or more data streams.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 25, 2023
    Assignee: FUNGIBLE, INC.
    Inventor: Satyanarayana Lakshmipathi Billa
  • Patent number: 11625333
    Abstract: Methods, systems, and devices for configurable flush operation speed are described. Before executing a flush operation at a first portion of a cache including single-level cells (SLCs), a memory system may communicate parameters associated with data stored in the first portion of the cache to a host system. The host system may then identify another portion of the cache (e.g., including either SLCs or multi-level cells (MLCs)) for the flush operation based on the parameters and a speed of a flush operation associated with the other portions of the cache. The host system may indicate the identified portion of the cache to the memory system and the memory system may execute a flush operation at the first portion of the cache. For example, the memory system may write a subset of the data stored at the first portion of the cache to a second portion of the cache.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 11, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11620060
    Abstract: Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein an access latency for a near memory device is less than an access latency for a far memory device. The near memory devices store data in data units having addresses in a near memory virtual address space, while the far memory devices store data in data units having addresses in a far memory address space, with a portion of the data being stored on both near and far memory devices. In response to memory read access requests, a determination is made to where data corresponding to the request is located on a near memory device, and if so the data is read from the near memory device; otherwise, the data is read from a far memory device. Memory access patterns are observed, and portions of far memory that are frequently accessed are copied to near memory to reduce access latency for subsequent accesses.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 11615024
    Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric coupled to the system memory and the multiple vertical cache hierarchies. Based on a request of a requesting processor core among the plurality of processor cores, a master in the multiprocessor data processing system issues, via the interconnect fabric, a read-type memory access request. The master receives via the interconnect fabric at least one beat of conditional data issued speculatively on the interconnect fabric by a controller of the system memory prior to receipt by the controller of a systemwide coherence response for the read-type memory access request. The master forwards the at least one beat of conditional data to the requesting processor core.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 28, 2023
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Michael S. Siegel, Guy L. Guthrie, Bernard C. Drerup
  • Patent number: 11593276
    Abstract: A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: February 28, 2023
    Assignee: SK hynix Inc.
    Inventors: Seung Gyu Jeong, Dong Gun Kim
  • Patent number: 11586539
    Abstract: A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: February 21, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Weon Taek Na, Jagadish B. Kotra, Yasuko Eckert, Steven Raasch, Sergey Blagodurov
  • Patent number: 11567971
    Abstract: A method of processing data in a system having a host and a storage node may include performing a shuffle operation on data stored at the storage node, wherein the shuffle operation may include performing a shuffle write operation, and performing a shuffle read operation, wherein at least a portion of the shuffle operation is performed by an accelerator at the storage node. A method for partitioning data may include sampling, at a device, data from one or more partitions based on a number of samples, transferring the sampled data from the device to a host, determining, at the host, one or more splitters based on the sampled data, communicating the one or more splitters from the host to the device, and partitioning, at the device, data for the one or more partitions based on the one or more splitters.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: January 31, 2023
    Inventors: Hui Zhang, Joo Hwan Lee, Yiqun Zhang, Armin Haj Aboutalebi, Xiaodong Zhao, Praveen Krishnamoorthy, Andrew Chang, Yang Seok Ki
  • Patent number: 11550723
    Abstract: An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 10, 2023
    Assignee: Qualcomm Incorporated
    Inventors: Niket Choudhary, David Scott Ray, Thomas Philip Speier, Eric Robinson, Harold Wade Cain, III, Nikhil Narendradev Sharma, Joseph Gerald McDonald, Brian Michael Stempel, Garrett Michael Drapala
  • Patent number: 11507420
    Abstract: Systems and methods for scheduling tasks using sliding time windows are provided. In certain embodiments, a system for scheduling the execution of tasks includes at least one processing unit configured to execute multiple tasks, wherein each task in the multiple tasks is scheduled to execute within a scheduler instance in multiple scheduler instances, each scheduler instance in the multiple scheduler instances being associated with a set of time windows in multiple time windows and with a set of processing units in the at least one processing unit in each time window, time windows in the plurality of time windows having a start time and an allotted duration and the scheduler instance associated with the time windows begins executing associated tasks no earlier than the start time and executes for no longer than the allotted duration, and wherein the start time is slidable to earlier moments in time.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: November 22, 2022
    Assignee: Honeywell International Inc.
    Inventors: Srivatsan Varadarajan, Larry James Miller, Arthur Kirk McCready, Aaron R. Larson, Richard Frost, Ryan Lawrence Roffelsen
  • Patent number: 11507441
    Abstract: A method of performing a remotely-initiated procedure on a computing device is provided. The method includes (a) receiving, by memory of the computing device, a request from a remote device via remote direct memory access (RDMA); (b) in response to receiving the request, assigning processing of the request to one core of a plurality of processing cores of the computing device, wherein assigning includes the one core receiving a completion signal from a shared completion queue (Shared CQ) of the computing device, the Shared CQ being shared between the plurality of cores; and (c) in response to assigning, performing, by the one core, a procedure described by the request. An apparatus, system, and computer program product for performing a similar method are also provided.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Leonid Ravich, Yuri Chernyavsky
  • Patent number: 11481598
    Abstract: A computer-implemented method for creating an auto-scaled predictive analytics model includes determining, via a processor, whether a queue size of a service master queue is greater than zero. Responsive to determining that the queue size is greater than zero, the processor fetches a count of requests in a plurality of requests in the service master queue and a type for each of the requests. The processor derives a value for time required for each of the requests and retrieves a number of available processing nodes based on the time required for each of the requests. The processor then auto-scales a processing node number responsive to determining that a total execution time for all of the requests in the plurality of requests exceeds a predetermined time value and outputs an auto-scaled predictive analytics model based on the processing node number and queue size.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 25, 2022
    Assignee: International Business Machines Corporation
    Inventors: Mahadev Khapali, Shashank V. Vagarali
  • Patent number: 11467908
    Abstract: A distributed storage places data units and parity units constituting a stripe formed by divided data into storage nodes in a distributed manner. In reference to determination formulas, either a full-stripe parity calculation method or an RPM parity calculation method is selected so as to minimize an amount of network traffic.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 11, 2022
    Assignee: HITACHI, LTD.
    Inventors: Kazushi Nakagawa, Mitsuo Hayasaka, Yuto Kamo
  • Patent number: 11442869
    Abstract: A cache memory includes a first cache area corresponding to even addresses, and a second cache area corresponding to odd addresses, wherein each of the first and second cache areas includes a plurality of cache sets, and each cache set includes a data set field suitable for storing data corresponding to an address among the even and odd addresses, and a pair field suitable for storing information on a location where data corresponding to an adjacent address which is adjacent to an address corresponding to the stored data is stored.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Seung-Gyu Jeong
  • Patent number: 11442868
    Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 13, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Hippleheuser
  • Patent number: 11431790
    Abstract: The present description is directed towards systems and methods for directing a user request for content over a network to a given content server on the basis of one or more rules. Methods and systems implemented in accordance with the present description comprise receiving a request for content form a user, the request for content including a profile of the user identifying one or more characteristics associated with the user. One or more rules are retrieved for identifying a content server to which a request for content is to be delivered, the one or more rules including at least one of business rules, network rules, and user profile rules. The one or more retrieved rules are applied to the request for content to identify a content server to which the request for content is to be delivered and the request for content is delivered to the identified content server.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 30, 2022
    Assignee: R2 Solutions, LLC
    Inventors: Selvaraj Rameshwara Prathaban, Dorai Ashok S.A., Mahadevaswamy G. Kakoor, Bhargavaram B. Gade, Matthew Nicholas Petach
  • Patent number: 11422891
    Abstract: Example apparatus and methods control a data storage system to store data in a self-describing logical data storage capsule using a logical cylindrical recording format. Example apparatus and methods assign a searchable, globally unique identifier to the capsule and associate the globally unique identifier with a user. The logical data storage capsule is migrated from a first data storage medium to a second data storage medium without translating or reformatting the data storage capsule. The data storage capsule contains information describing to a data storage device how to migrate the capsule without translating or reformatting the data storage capsule. Example apparatus and methods dynamically select an error correction approach for storing data in the data storage capsule, de-duplicate, and encrypt the data storage capsule. The data storage capsule may be local, or may be part of a cloud-based storage system.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: August 23, 2022
    Assignee: QUANTUM CORPORATION
    Inventor: George Saliba
  • Patent number: 11422938
    Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 23, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew David Pierson, Kai Chirca, Timothy David Anderson
  • Patent number: 11416405
    Abstract: A circuit and corresponding method map memory addresses onto cache locations within set-associative (SA) caches of various cache sizes. The circuit comprises a modulo-arithmetic circuit that performs a plurality of modulo operations on an input memory address and produces a plurality of modulus results based on the plurality of modulo operations performed. The plurality of modulo operations performed are based on a cache size associated with an SA cache. The circuit further comprises a multiplexer circuit and an output circuit. The multiplexer circuit outputs selected modulus results by selecting modulus results from among the plurality of modulus results produced. The selecting is based on the cache size. The output circuit outputs a cache location within the SA cache based on the selected modulus results and the cache size. Such mapping of the input memory address onto the cache location is performed at a lower cost relative to a general-purpose divider.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: August 16, 2022
    Assignee: MARVELL ASIA PTE LTD
    Inventor: Albert Ma
  • Patent number: 11397680
    Abstract: A technique is provided for controlling eviction from a storage structure. An apparatus has a storage structure with a plurality of entries to store data. The apparatus also has eviction control circuitry configured to maintain eviction control information in accordance with an eviction policy, the eviction policy specifying how the eviction control information is to be updated in response to accesses to the entries of the storage structure. The eviction control circuitry is responsive to a victim selection event to employ the eviction policy to select, with reference to the eviction control information, one of the entries to be a victim entry whose data is to be discarded from the storage structure. The eviction control circuitry is further configured to maintain, for each of one or more groups of entries in the storage structure, an indication of a most-recent entry. The most-recent entry is an entry in that group that was most recently subjected to at least a given type of access.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: July 26, 2022
    Assignee: Arm Limited
    Inventor: Joseph Michael Pusdesris
  • Patent number: 11392498
    Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 19, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
  • Patent number: 11379370
    Abstract: In a multi-node system, each node includes tiles. Each tile includes a cache controller, a local cache, and a snoop filter cache (SFC). The cache controller responsive to a memory access request by the tile checks the local cache to determine whether the data associated with the request has been cached by the local cache of the tile. The cached data from the local cache is returned responsive to a cache-hit. The SFC is checked to determine whether any other tile of a remote node has cached the data associated with the memory access request. If it is determined that the data has been cached by another tile of a remote node and if there is a cache-miss by the local cache, then the memory access request is transmitted to the global coherency unit (GCU) and the snoop filter to fetch the cached data. Otherwise an interconnected memory is accessed.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 5, 2022
    Assignee: Marvell Asia Pte Ltd
    Inventors: Pranith Kumar Denthumdas, Rabin Sugumar, Isam Wadih Akkawi
  • Patent number: 11360891
    Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: June 14, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh
  • Patent number: 11354307
    Abstract: There is provided a database management system, comprising: a multicore processor, a shared memory, a partitioned memory, and a database engine adapted to execute at least one transaction worker thread managing transaction states and database indexes in the shared memory using a cache coherency mechanism, and execute at least one partition manager thread for handling database access actions submitted by the at least one transaction worker thread to access a database in the partitioned memory, the cache coherency mechanism being disabled in the partitioned memory; wherein the at least one transaction worker thread and the at least one partition manager thread are executed simultaneously on the multicore processor.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: June 7, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Israel Gold, Hillel Avni, Antonios Iliopoulos
  • Patent number: 11350145
    Abstract: A method, Delivery Node, DN, and Content Delivery Network, CDN, are optimized to deliver content of different categories. The DN is operative to receive a request for a content, obtain a determination of whether or not a category of content is associated with the requested content and responsive to the determination that no category of content is associated with the requested content, forward the request for the content towards an origin server and upon receiving a response from the origin server serve the content. The CDN comprises a plurality of DNs, a data processing service operative to obtain, from the DNs, and assemble, data sets into training and validation data formatted to be used for training and validating a Neural Network, NN. The CDN comprises a NN training service, operative to train and validate the NN and a configuration service, operative to configure the plurality of DNs with the trained and validated NN.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: May 31, 2022
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Zhongwen Zhu
  • Patent number: 11334494
    Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 17, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Hippleheuser
  • Patent number: 11327887
    Abstract: Techniques related to a server-side extension of client-side caches are provided. A storage server computer receives, from a database server computer, an eviction notification indicating that a data block has been evicted from the database server computer's cache. The storage server computer comprises a memory hierarchy including a volatile cache and a persistent cache. Upon receiving the eviction notification, the storage server computer retrieves the data block from the persistent cache and stores it in the volatile cache. When the storage server computer receives, from the database server computer, a request for the data block, the storage server computer retrieves the data block from the volatile cache. Furthermore, the storage server computer sends the data block to the database server computer, thereby causing the data block to be stored in the database server computer's cache. Still further, the storage server computer evicts the data block from the volatile cache.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 10, 2022
    Assignee: Oracle International Corporation
    Inventors: Jia Shi, Wei Zhang, Kothanda Umamageswaran, Neil J. S. MacNaughton, Vijayakrishnan Nagarajan
  • Patent number: 11321146
    Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ralf Winkelmann, Michael Fee, Matthias Klein, Carsten Otte, Edward W. Chencinski, Hanno Eichelberger
  • Patent number: 11320890
    Abstract: Techniques and apparatuses are described that enable power-conserving cache memory usage. Main memory constructed using, e.g., DRAM can be placed in a low-power mode, such as a self-refresh mode, for longer time periods using the described techniques and apparatuses. A hierarchical memory system includes a supplemental cache memory operatively coupled between a higher-level cache memory and the main memory. The main memory can be placed in the self-refresh mode responsive to the supplemental cache memory being selectively activated. The supplemental cache memory can be implemented with a highly- or fully-associative cache memory that is smaller than the higher-level cache memory. Thus, the supplemental cache memory can handle those cache misses by the higher-level cache memory that arise because too many memory blocks are mapped to a single cache line. In this manner, a DRAM implementation of the main memory can be kept in the self-refresh mode for longer time periods.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 3, 2022
    Assignee: Google LLC
    Inventor: Christopher J. Phoenix
  • Patent number: 11316694
    Abstract: A computing device's trusted platform module (TPM) is configured with a cryptographic watchdog timer which forces a device reset if the TPM fails to solve a cryptographic challenge before the expiration of the timer. The computing device's TPM is configured to generate the cryptographic challenge, to which the computing device does not possess the cryptographic token for resolution. While the watchdog timer counts down, the computing device requests a cryptographic token from a remote service to solve the challenge. The remote service transmits the cryptographic token to the computing device so long as the remote service identifies no reason to withhold the token, such as the computing device being infected with malware. The interoperability of the computing device and remote service enables the remote service to exercise control and reset capabilities over the computing device.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 26, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Stefan Thom, Brian Clifford Telfer, Paul England, Dennis James Mattoon, Marcus Peinado
  • Patent number: 11316947
    Abstract: A method, computer system, and a computer program product for execution of a stateless service on a node in a workload execution environment is provided. The present invention may include defining for each node a workload container including a cache component of a cache-mesh. The present invention may include, upon receiving a state request from a stateless requesting service from one of the cache components of the cache-mesh in an execution container, determining whether a requested state is present in the cache component of a related execution container. The present invention may include, upon a cache miss, broadcasting the state request to other cache components of the cache-mesh, determining, by the other cache components, whether the requested state is present in respective caches, and upon any cache component identifying the requested state, sending the requested state to the requesting service using a protocol for communication.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sven Sterbling, Christian Habermann, Sachin Lingadahalli Vittal
  • Patent number: 11294675
    Abstract: A method for accessing a memory of a multi-core system, a related apparatus, a system, and a storage medium involve obtaining data from a system memory according to a prefetch instruction, and sending a message to a core that carries the to-be-accessed data. Each segment of data is stored in an intra-core cache based on the prefetch instruction.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 5, 2022
    Assignee: HUAWEI TECHNOLGOIES CO., LTD.
    Inventors: Jun Yao, Yasuhiko Nakashima, Tao Wang, Wei Zhang, Zuqi Liu, Shuzhan Bi
  • Patent number: 11294932
    Abstract: A massively parallel database management system includes an index store and a payload store including a set of storage systems of different temperatures. Both the stores each include a list of clusters. Each cluster includes a set of nodes with storage devices forming a group of segments. Nodes and clusters are connected over high speed links. The list of clusters within the payload store includes clusters of different temperatures. The payload store transitions data of a segment group from a higher temperature to a segment group in a lower temperature cluster in parallel. A node moves data of a segment in the higher temperature cluster to a corresponding node's segment in the lower temperature cluster. Once the data is written in the destination segment in the lower temperature cluster, the source segment is freed to store other data. The temperatures include blazing, hot, warm and cold.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: April 5, 2022
    Assignee: Ocient Inc.
    Inventors: George Kondiles, Rhett Colin Starr, Joseph Jablonski
  • Patent number: 11288211
    Abstract: A method for moving data includes identifying, by a staging manager in a container, a trigger condition associated with data being used by an application external to the container, performing an analysis on the trigger condition, making a first determination, based on the analysis, that the trigger condition is satisfied, and processing, based on the first determination, a data movement action.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jean-Pierre Bono, Marc A. De Souter, Adrian Michaud