Hierarchical Caches Patents (Class 711/122)
  • Patent number: 11147070
    Abstract: Aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for use in receiving devices employing at least one iterative process for decoding messages. In certain example aspects, a receiving device may comprise a user equipment (UE) or other like device that may be configured to support device-to-device (D2D) communications, such as vehicle-to-vehicle (V2V) communications, or the like.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 12, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Junyi Li, Alexander Leonidov, Thomas Joseph Richardson
  • Patent number: 11126559
    Abstract: A memory system implements any combination of zero or more cache eviction policies, zero or more cache prefetch policies, and zero or more virtual address modification policies. A memory allocation technique implements parameter receiving and processing in accordance with the cache eviction policies, the cache prefetch policies, and the virtual address modification policies. A compiler system optionally processes any combination of zero or more indicators of extended data types usable to indicate one or more of the cache eviction policies, the cache prefetch policies, and/or the virtual address modification policies to associate with a variable, an array of variables, and/or a section of memory. The indicators comprise any combination of zero or more compiler flags, zero or more compiler switches, and/or zero or more pseudo-keywords in source code.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 21, 2021
    Inventor: Michael Henry Kass
  • Patent number: 11119830
    Abstract: Embodiments of the invention are directed to methods for improving performance of a multi-core processor. A non-limiting method includes increasing a first operating frequency to a first elevated operating frequency of a first core of a gang of cores, the gang of cores comprising a plurality of cores of the multi-core processor. The method further includes upon a determination that an operating temperature of the first core is above a threshold temperature, switching processing of a thread from the first core to a second core in the gang of cores. The method further includes reducing the first operating frequency of the first core. The method further includes increasing the operating frequency of the second core to a second elevated operating frequency.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 14, 2021
    Inventors: Oliver Benke, Tobias U. Bergmann
  • Patent number: 11113057
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 7, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Joseph Zbiciak
  • Patent number: 11106588
    Abstract: Embodiments are provided for deferring allocation of storage for segments. The method includes receiving, at a first moment in time, a request to allocate a first segment within a memory. Information corresponding to the first segment is stored in a first entry in a hash table, and memory is allocated for the first segment. Information about the first segment is returned to an entity that requested the allocation of the first segment, where the first segment is not allocated auxiliary storage until predefined criteria are satisfied. At a second moment in time, upon receiving an indication to deallocate the first segment, memory corresponding to the first segment is deallocated, where the first segment is never allocated auxiliary storage and the first entry in the hash table is deleted.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 31, 2021
    Assignee: International Business Machines Corporation
    Inventors: William A. Brown, Michael Corrigan, Kevin C. Griffin, Glen W. Nelson, David G. Carlson
  • Patent number: 11107521
    Abstract: A semiconductor memory device may include a memory cell array; and a cache latch circuit that exchanges data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction. The memory cell array may include a plurality of cache latches arranged in a plurality of columns in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
  • Patent number: 11106393
    Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 11074181
    Abstract: An example method of managing persistent memory (PM) in a computing system includes: issuing, by an application executing in the computing system, store instructions to an address space of the application, the address space including a region mapped to the PM; recording, by a central processing unit (CPU) in the computing system, cache line addresses in a log, the cache line addresses corresponding to cache lines in the address space of the application targeted by the store instructions; and issuing, by the application, one or more instructions to flush cache lines from cache of the CPU identified by the cache line addresses in the log.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 27, 2021
    Assignee: VMware, Inc.
    Inventors: Aasheesh Kolli, Vijaychidambaram Velayudhan Pillai
  • Patent number: 11074075
    Abstract: Systems, apparatuses, and methods for maintaining separate pending load and store counters are disclosed herein. In one embodiment, a system includes at least one execution unit, a memory subsystem, and a pair of counters for each thread of execution. In one embodiment, the system implements a software based approach for managing dependencies between instructions. In one embodiment, the execution unit(s) maintains counters to support the software-based approach for managing dependencies between instructions. The execution unit(s) are configured to execute instructions that are used to manage the dependencies during run-time. In one embodiment, the execution unit(s) execute wait instructions to wait until a given counter is equal to a specified value before continuing to execute the instruction sequence.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 27, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark Fowler, Brian D. Emberling
  • Patent number: 11068410
    Abstract: According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: July 20, 2021
    Assignee: ETA SCALE AB
    Inventors: Alberto Ros, Stefanos Kaxiras
  • Patent number: 11068264
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory address information is to include a plurality of memory address information data elements. An execution unit is coupled with the decode unit and the plurality of packed data registers, the execution unit, in response to the instruction, is to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements in a destination storage location. The destination storage location does not include a register of the plurality of packed data registers.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: William C. Hasenplaugh, Chris J. Newburn, Simon C. Steely, Jr., Samantika S. Sury
  • Patent number: 11061828
    Abstract: A computer-implemented method, according to one approach, includes: receiving an I/O request which includes supplemental information pertaining to an anticipated workload of the I/O request. The supplemental information is used to determine whether to satisfy the I/O request using a primary cache. In response to determining to satisfy the I/O request using the primary cache, the I/O request is initiated using the primary cache, and performance characteristics experienced by the primary cache while satisfying the I/O request are evaluated. The supplemental information and the performance characteristics are further used to determine whether to satisfy a remainder of the I/O request using the secondary cache. In response to determining to satisfy a remainder of the I/O request using the secondary cache, the I/O request is demoted from the primary cache to the secondary cache, and a remainder of the I/O request is satisfied using the secondary cache.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Beth Ann Peterson, Chung Man Fung, Lokesh Mohan Gupta, Kyler A. Anderson
  • Patent number: 11061824
    Abstract: Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative is disclosed. The updating of at least one cache state in the cache memory resulting from a data request is deferred until the data request becomes non-speculative. Thus, a cache state in the cache memory is not updated for requests resulting from mispredictions. Deferring the updating of a cache state in the cache memory can include deferring the storing of received speculative requested data in the main data array of the cache memory as a result of a cache miss until the data request becomes non-speculative. The received speculative requested data can first be stored in a speculative buffer memory associated with a cache memory, and then stored in the main data array if the data request becomes non-speculative.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 13, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vignyan Reddy Kothinti Naresh, Arthur Perais, Rami Mohammad Al Sheikh, Shivam Priyadarshi
  • Patent number: 11061841
    Abstract: A method of implementing a multi-threaded device driver for a computer system is disclosed. A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: July 13, 2021
    Assignee: Rambus, Inc.
    Inventors: Bart Trojanowski, Michael L. Takefman, Maher Amer
  • Patent number: 11033343
    Abstract: Systems and methods for operating a robotic surgical system are provided. The system includes a surgical tool, a manipulator comprising links for controlling the tool, a navigation system comprising a tracker coupled to the manipulator or the tool and a localizer to monitor a state of the tracker. Controller(s) determine a raw (or lightly filtered) relationship between one or more components of the manipulator and one or more components of the navigation system by utilizing one or more of raw kinematic measurement data from the manipulator and raw navigation data from the navigation system. The controller(s) utilize the raw (or lightly filtered) relationship to determine whether an error has occurred relating to at least one of the manipulator and the navigation system.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 15, 2021
    Assignee: MAKO Surgical Corp.
    Inventor: Michael Dale Dozeman
  • Patent number: 11030108
    Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Berkin Akin, Rajat Agarwal, Jong Soo Park, Christopher J. Hughes, Chiachen Chou
  • Patent number: 11016895
    Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Frank T. Hady, Mason Cabot, Mark B. Rosenbluth, John Beck
  • Patent number: 11016859
    Abstract: Content-aware systems and methods for improving de-duplication, or single instancing, in storage operations. In certain examples, backup agents on client devices parse application-specific data to identify data objects that are candidates for de-duplication. The backup agents can then insert markers or other indictors in the data that identify the location(s) of the particular data objects. Such markers can, in turn, assist a de-duplication manager to perform object-based de-duplication and increase the likelihood that like blocks within the data are identified and single instanced. In other examples, the agents can further determine if a data object of one file type can or should be single-instanced with a data object of a different file type. Such processing of data on the client side can provide for more efficient storage and back-end processing.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 25, 2021
    Assignee: Commvault Systems, Inc.
    Inventors: Anand Prahlad, Manoj Kumar Vijayan, Rajiv Kottomtharayil, Parag Gokhale
  • Patent number: 11018978
    Abstract: In a network device, a hash-based lookup system includes a hash generator configured to apply respective hash functions to a lookup key to generate respective hash values. Each hash function corresponds to a respective logical hash bank in a hash table. A number of hash values generated by the hash generator corresponds to the number of logical hash banks in the hash table, and the number of hash values generated by the hash generator is configurable. The hash-based lookup system also includes an address generator that is configured to generate respective addresses to a memory that stores the hash table, the respective addresses within respective address spaces of respective logical hash banks of the hash table. The address generator uses i) a parameter N that specifies the number of logical hash banks in the hash table, and ii) N hash values generated by the hash generator, to generate the respective addresses.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 25, 2021
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Ido Grinberg, Ilan Mayer-Wolf, Itzik Abudi
  • Patent number: 11010163
    Abstract: Disclosed herein is an apparatus which comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: May 18, 2021
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu, Subramaniam Maiyuran, Prasoonkumar Surti, Guei-Yuan Lueh, David Puffer, Supratim Pal, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd
  • Patent number: 11010306
    Abstract: An apparatus and method are provided for managing a cache hierarchy. The apparatus has processing circuitry for executing instructions, and a cache hierarchy for storing content for access by the processing circuitry when executing those instructions. The cache hierarchy has a plurality of levels of cache including a highest level of cache that is accessed prior to the other levels of cache in response to a request from the processing circuitry. Eviction control circuitry is provided in association with each level of cache, and the eviction control circuitry associated with a chosen level of cache in arranged to implement a most recently read eviction policy that causes content most recently read from the chosen level of cache to be selected for eviction from that chosen level of cache. It has been found that such an approach can significantly increase the effective cache capacity within the cache hierarchy, without the complexities often associated with other schemes.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: May 18, 2021
    Assignee: Arm Limited
    Inventors: Andrew Campbell Betts, Max Nicholas Holland
  • Patent number: 11003580
    Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, write and read commands from a client device are placed into a command queue pending servicing to transfer data between the client device and a non-volatile memory (NVM). A write cache temporarily stores sets of writeback data pending transfer. A cache manager detects an overlap condition in which a subsequently received command at least partially overlaps a pending write command. In response, the cache manager enacts a change in caching policy that includes retention of the cached writeback data to aid in the servicing of the subsequently received command. The changes in caching policy can include an increase in the size of the write cache, delays in the writing of hot writeback data sets, the coalescing of different writeback data sets, cache hits using the cached writeback data, etc.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 11, 2021
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Daniel John Benjamin, David W. Claude, Graham David Ferris, Ryan Charles Weidemann
  • Patent number: 10997074
    Abstract: In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Frank R. Dropps
  • Patent number: 10992312
    Abstract: Disclosed is an operating method of a semiconductor device, including acquiring resource information on a plurality of hardware resources, receiving a compression request or a decompression request for data, acquiring context information on the semiconductor device, in response to receiving the compression request or the decompression request for the data, selecting a compression algorithm for compressing or decompressing the data, based on the context information, selecting, among the plurality of hardware resources, a hardware resource for performing the selected compression algorithm, based on the acquired resource information, and compressing or decompressing the data using the selected compression algorithm and the selected hardware resource.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 27, 2021
    Inventor: Seung-Soo Yang
  • Patent number: 10970220
    Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: April 6, 2021
    Assignee: RAMBUS INC.
    Inventors: Michael Miller, Dennis Doidge, Collins Williams
  • Patent number: 10956048
    Abstract: Computing device and method for inferring a predicted number of physical blocks erased from a flash memory. The computing device stores a predictive model generated by a neural network training engine. A processing unit of the computing device executes a neural network inference engine, using the predictive model for inferring the predicted number of physical blocks erased from the flash memory based on inputs. The inputs comprise a total number of physical blocks previously erased from the flash memory, an amount of data to be written on the flash memory, and optionally an operating temperature of the flash memory. In a particular aspect, the flash memory is comprised in the computing device, and an action may be taken for preserving a lifespan of the flash memory based at least on the predicted number of physical blocks erased from the flash memory.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: March 23, 2021
    Assignee: DISTECH CONTROLS INC.
    Inventor: Francois Gervais
  • Patent number: 10956339
    Abstract: A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Paul James Moyer
  • Patent number: 10958729
    Abstract: Non-volatile Memory Express over Fabric (NVMeOF) using Volume Management Device (VMD) schemes and associated methods, systems and software. The schemes are implemented in a data center environment including compute resources in compute drawers and storage resources residing in pooled storage drawers that are communicatively couple via a fabric. Compute resources are composed as compute nodes or virtual machines/containers running on compute nodes to utilize remote storage devices in pooled storage drawers, while exposing the remote storage devices as local NVMe storage devices to software running on the compute nodes. This is facilitated by virtualizing the system's storage infrastructure through use of hardware-based components, firmware-based components, or a combination of hardware/firmware- and software-based components. The schemes support the use of remote NVMe storage devices using an NVMeOF protocol and/or use of non-NVMe storage devices using NVMe emulation.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 10951549
    Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 16, 2021
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: George Elias, Gil Levy, Liron Mula, Aviv Kfir, Benny Koren, Sagi Kuks
  • Patent number: 10936574
    Abstract: In accordance with an embodiment, described herein is a system and method for use of lock-less data structures and processes with a multidimensional database computing environment. Lock-less algorithms or processes can be implemented with specific hardware-level instructions so as to provide atomicity. A memory stores an index cache retaining a plurality of index pages of the multidimensional database. A hash table indexes index pages in the index cache, wherein the hash table is accessible by a plurality of threads in parallel through application of the lock-less process.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: March 2, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Young Joon Kim, Vilas Ketkar, Shubhagam Gupta, Haritha Gongalore
  • Patent number: 10936194
    Abstract: In one aspect of storage device status management in accordance with the present description, a host can determine not only whether a particular volume maintained by a storage unit controlled by a storage controller is on-line with respect to another host, but also whether that volume is actually in use by another host. Accordingly, should one host determine that a volume is in use by another host, the one host can defer its use of the volume until the volume is no longer in use by another host. In this manner, conflicts which may lead to loss of data integrity may be reduced or eliminated, providing a significant improvement in computer technology. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael J. Koester, Kevin L. Miner, Thao Bui, Richard A. Schaeffer
  • Patent number: 10936506
    Abstract: This disclosure provides a method for tagging control information associated with a physical address in a processing system, including setting a hardware tag for the control information, the hardware tag being invisible to a software system in the processing system; joining the hardware tag with the physical address to form a compound physical address, the hardware tag including M bits carried by a dedicated hardware tag control line, the physical address including N bits carried by a physical address bus, M and N being positive integers; and tagging the control information with the hardware tag in the compound physical address.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 2, 2021
    Assignee: CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.
    Inventors: Chunhui Zhang, Ruchir Dalal, Feng Zeng, Jiang Lin
  • Patent number: 10929283
    Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Gary L. Howe
  • Patent number: 10915453
    Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Israel Diamand, Zvika Greenfield, Julius Mandelblat, Asaf Rubinstein
  • Patent number: 10908946
    Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hetul Sanghvi, Niraj Nandan, Mihir Narendra Mody, Kedar Satish Chitnis
  • Patent number: 10911525
    Abstract: Techniques for configuring and operating a multimedia aware cloud, particularly configured for mobile device computing, are described herein. In some instances, clusters of servers are organized for general computing, graphic computing and data storage. A load balancing server may be configured to: identify multimedia types currently being processed within the multimedia edge cloud; determine desired quality of service levels for each identified multimedia type; evaluate individual abilities of devices communicating with the multimedia edge cloud; and assess bandwidth of each network over which the multimedia edge cloud communicates with a mobile device. With that information, multimedia data may be adapted accordingly, to result in an acceptable quality of service level when delivered to a specific mobile device. In one example of the techniques, graphic computing server clusters may be configured to process workload using a configuration that includes elements of both parallel and serial computing.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Wenwu Zhu, Lie Liu, Chong Luo
  • Patent number: 10909039
    Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Vikranth Vemulapalli, Lakshminarayanan Striramassarma, Mike MacPherson, Aravindh Anantaraman, Ben Ashbaugh, Murali Ramadoss, William B. Sadler, Jonathan Pearce, Scott Janus, Brent Insko, Vasanth Ranganathan, Kamal Sinha, Arthur Hunter, Jr., Prasoonkumar Surti, Nicolas Galoppo von Borries, Joydeep Ray, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Altug Koker, Sungye Kim, Subramaniam Maiyuran, Valentin Andrei
  • Patent number: 10901897
    Abstract: Aspects of the disclosure provide a network device. The network device includes a search engine, a ternary content addressable memory (TCAM) cache engine, a search key generation unit and an output controller. The search engine stores a lookup table of entries for rules of packet processing, and searches the lookup table in response to packets received from a network interface of the network device. The TCAM cache engine caches a subset of the entries in the lookup table based on hit statistics of the entries. The search key generation unit generates a search key based on a received packet and provides the search key to the search engine and to the TCAM cache engine. The output controller outputs a search result from the TCAM cache engine when the TCAM cache engine has a matching entry to the search key.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Dovrat Zifroni, Henri Sznajder, Dmitry Lyachover
  • Patent number: 10901902
    Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chad G. Wilson, Robert J Sonnelitter, III, Tim Bronson, Ekaterina M. Ambroladze, Hieu T Huynh, Jason D Kohl, Chakrapani Rayadurgam
  • Patent number: 10901640
    Abstract: A memory access system includes a memory, a controller, and a redundancy elimination unit. The memory is a multi-way set associative memory, and the redundancy elimination unit records M record items. Each record item is used to store a tag of a stored data block in one of storage sets. The controller determines a read data block and a target storage set of the read data block and sends a query message to the redundancy elimination unit. The query message carries a set identifier of the target storage set of the read data block and a tag of the read data block. The redundancy elimination unit determines a record item corresponding to the set identifier of the target storage set, matches the tag of the read data block with a tag of a stored data block in the record item corresponding to the target storage set of the read data block.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 26, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fenglong Song, Guangfei Zhang, Tao Wang
  • Patent number: 10896479
    Abstract: One embodiment provides for a general-purpose graphics processing unit multiple processing elements having a single instruction, multiple thread (SIMT) architecture, the multiple processing elements to perform hardware multithreading during execution of multiple warps of threads, wherein a warp is a group of parallel threads; a scheduler to schedule a set of sub-warps to the multiple processing elements at sub-warp granularity, wherein a sub-warp is a sub-group of parallel threads, a warp includes multiple sub-warps, and the scheduler is to schedule threads in a first sub-warp of a first warp of threads to execute concurrently with the threads in a second sub-warp of a second warp of threads; and a logic unit including hardware or firmware logic, the logic unit to group active threads for execution on the multiple processing elements.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Balaji Vembu, Altug Koker, Joydeep Ray
  • Patent number: 10893101
    Abstract: Disclosed herein are methods, systems, and processes to select storage tiers for data replication and data recovery. A replication stream is received from a replication appliance that is configured to replicate data to a storage tier of multiple storage tiers. Each storage tier differs from at least one other storage tier in at least one storage characteristic. Portions of the replication stream are identified based on input/output (I/O) characteristics. The portions are stored in one storage tier other than the storage tier based on the I/O characteristics, and a storage cost associated with each storage tier, where the storage cost associated with each storage tier is based on storage characteristics of each storage tier.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 12, 2021
    Assignee: VERITAS TECHNOLOGIES LLC
    Inventors: Hrudil Gorantla, Subhadeep Ghosh, Sunil Hasbe, Subash Rajaa
  • Patent number: 10884626
    Abstract: Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a command including a virtual address from a host translating the virtual address to a physical address on volatile memory of a memory device using a translation lookaside buffer (TLB).
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Leidel, Richard C. Murphy
  • Patent number: 10884927
    Abstract: One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 5, 2021
    Assignee: INTEL CORPORATION
    Inventors: Zhe Wang, Alaa R. Alameldeen
  • Patent number: 10877761
    Abstract: A multiprocessor device includes cores and at least one ingress-write ordering circuitry (IWOC) including first and second counters associated with first and second destinations. The IWOC is configured to assign sequential numbers to write transactions received from a source, according to an order of reception at the IWOC, and to forward the write transactions from the IWOC to the first and second write-transaction destinations, while preserving the order, by incrementing the first and second counters such that both the first counter and the second counter track a sequential number of a next write transaction that the IWOC will forward, forwarding a first write transaction to the first destination only provided that the sequential number of the first write transaction matches the first counter, and forwarding a second write transaction to the second destination only provided that the sequential number of the second write transaction matches the second counter.
    Type: Grant
    Filed: December 8, 2019
    Date of Patent: December 29, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Rui Xu, Carl Ramey, Benjamin Cahill, Diane Orf, Mark B. Rosenbluth, Michael Cotsford
  • Patent number: 10877911
    Abstract: Disclosed herein are techniques associated with a Direct Memory Access (DMA) engine that can include a data generation module. The DMA engine can receive, from a processing entity, a particular type of write command with an indicator to write a data pattern to an address. Upon receipt of the particular type of write command, the DMA engine can generate, using a data generation module of the DMA engine, the data pattern to be written to the address. The processing entity can be Central Processing Unit (CPU) including a core configured to process serial commands. The DMA engine can be disposed on a same die as a processing entity or a network interface port.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 29, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Asif Khan, Kiran Kalkunte Seshadri, Thomas A. Volpe, Carlos Javier Cabral, Steven Scott Larson
  • Patent number: 10866893
    Abstract: A method for operating a database and a cache of at least a portion of the database may include receiving a plurality of read requests to read a data entity from the database and counting respective quantities of the requests serviced from the database and from the cache. The method may further include receiving a write request to alter the data entity in the database and determining whether to update the cache to reflect the alteration to the data entity in the write request according to the quantity of the requests serviced from the database and the quantity of the requests serviced from the cache. In an embodiment, the method further includes causing the cache to be updated when a ratio of the quantity of the requests serviced from the database to the quantity of the requests serviced from the cache exceeds a predetermined threshold.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 15, 2020
    Assignee: Home Depot Product Authority, LLC
    Inventors: Hari Ramamurthy, Chandan Venkatesh, Krishna Guggulotu, Rageesh Thekkeyil
  • Patent number: 10860495
    Abstract: Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 8, 2020
    Assignee: ARM Limited
    Inventors: Andreas Hansson, Nikos Nikoleris, Wendy Arnott Elsasser
  • Patent number: 10853904
    Abstract: A processor employs a hierarchical register file for a graphics processing unit (GPU). A top level of the hierarchical register file is stored at a local memory of the GPU (e.g., a memory on the same integrated circuit die as the GPU). Lower levels of the hierarchical register file are stored at a different, larger memory, such as a remote memory located on a different die than the GPU. A register file control module monitors the status of in-flight wavefronts at the GPU, and in particular whether each in-flight wavefront is active, predicted to be become active, or inactive. The register file control module places execution data for active and predicted-active wavefronts in the top level of the hierarchical register file and places execution data for inactive wavefronts at lower levels of the hierarchical register file.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 1, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Yasuko Eckert, Nuwan Jayasena
  • Patent number: 10846230
    Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Brian J. Slechta