Abstract: A next generation antivirus (NGAV) security solution in a virtualized computing environment includes a security sensor at a virtual machine that runs on a host and a security engine remote from the host. The integrity of the NGAV security solution is increased, by providing a verification as to whether a verdict issued by the security engine has been successfully enforced by the security sensor to prevent execution of malicious code at the virtual machine.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.

Abstract: A parallel processing (PP) level coherence directory, also referred to as a Processing In-Memory Probe Filter (PimPF), is added to a coherence directory controller. When the coherence directory controller receives a broadcast PIM command from a host, or a PIM command that is directed to multiple memory banks in parallel, the PimPF accelerates processing of the PIM command by maintaining a directory for cache coherence that is separate from existing system level directories in the coherence directory controller. The PimPF maintains a directory according to address signatures that define the memory addresses affected by a broadcast PIM command. Two implementations are described: a lightweight implementation that accelerates PIM loads into registers, and a heavyweight implementation that accelerates both PIM loads into registers and PIM stores into memory.

Abstract: A circuit and corresponding method map memory addresses onto cache locations within set-associative (SA) caches of various cache sizes. The circuit comprises a modulo-arithmetic circuit that performs a plurality of modulo operations on an input memory address and produces a plurality of modulus results based on the plurality of modulo operations performed. The plurality of modulo operations performed are based on a cache size associated with an SA cache. The circuit further comprises a multiplexer circuit and an output circuit. The multiplexer circuit outputs selected modulus results by selecting modulus results from among the plurality of modulus results produced. The selecting is based on the cache size. The output circuit outputs a cache location within the SA cache based on the selected modulus results and the cache size. Such mapping of the input memory address onto the cache location is performed at a lower cost relative to a general-purpose divider.

Abstract: Methods and systems are provided for a browser in a client device that receives a user interface script-code snippet from a web page. A chain logic engine determines whether an in-memory map indicates an output value of prior execution of the UI script-code snippet. If the in-memory map does indicate the output value, it is returned from the in-memory map to generate the user interface. If not, the engine determines whether an in-local storage map indicates the prior executed snippet output. If the in-local storage map indicates the prior executed snippet output, it is returned from the in-local storage map to generate the user interface, and it is stored in the in-memory map. If not, the UI script-code snippet is executed to generate the output value, which is used to generate the user interface, and is stored in the in-memory map and in the in-local storage map.

Abstract: A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.

Abstract: A graphics processing system is disclosed having a cache system (24) arranged between memory (23) and the graphics processor (20), the cache system comprising a first cache (53) for transferring data to and from the graphics processor (20) and a second cache (54) arranged and configured to transfer data between the first cache (53) and memory (23). When data is to be written from the first cache (53) to memory (23), a cache controller (55) determines a data type of the data and, in dependence on the data type, either causes the data to be written into the second cache (54) without writing the data to memory (23), or causes the data to be written to memory (23) without storing the data in the second cache (54). In embodiments the second cache (54) is write-only allocated.

Abstract: Storage systems are disclosed. For instance, a storage system comprises a first storage device of a first type and a second storage device of a second type, and the first storage device has a higher access velocity than the second storage device. A threshold indicating a volume limit of data stored in the first storage device can be determined. Data, which is specified by a write request for writing data to the storage system, is written to the first storage device in response to determining the data amount in the first storage device is lower than the threshold. A read request from a client device is processed based on data stored in the first storage device. Consequently, the first storage device with a higher access velocity in the storage system may be utilized as much as possible, so that storage device latency in the storage system is managed more effectively.

Abstract: Embodiments of the present disclosure relate to cache memory management. One or more global caches are dynamically partitioned and sized into one or more cache partitions based on anticipated input/output (IO) workloads.

Abstract: Embodiments herein describe transferring ownership of data (e.g., cachelines or blocks of data comprising multiple cachelines) from a host to hardware in an I/O device. In one embodiment, the host and I/O device (e.g., an accelerator) are part of a cache-coherent system where ownership of data can be transferred from a home agent (HA) in the host to a local HA in the I/O device—e.g., a computational slave agent (CSA). That way, a function on the I/O device (e.g., an accelerator function) can request data from the local HA without these requests having to be sent to the host HA. Further, the accelerator function can indicate whether the local HA tracks the data on a cacheline-basis or by a data block (e.g., multiple cachelines). This provides flexibility that can reduce overhead from tracking the data, depending on the function's desired use of the data.

Abstract: The present disclosure provides a method and a system of verifying access by a multi-core interconnect to an L2 cache in order to solve problems of delays and difficulties in locating errors and generating check expectation results. A consistency transmission monitoring circuitry detects, in real time, interactions among a multi-core interconnects system, all single-core processors, an L2 cache and a primary memory, and sends collected transmission information to an L2 cache expectation generator and a check circuitry. The L2 cache expectation generator obtains information from a global memory precise control circuitry according to a multi-core consistency protocol and generates an expected result. The check circuitry is responsible for comparing the expected result with an actual result, thus implementing determination of multi-core interconnect's access accuracy to the L2 cache without delay.

Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM), and control circuitry configured to receive a plurality of access commands, process the plurality of access commands using a customer prediction model to predict a customer of the data storage device, wherein the customer prediction model is trained off-line based on access patterns of a plurality of different customers. The control circuitry then configures access to the NVSM based on the predicted customer.

Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

Abstract: The number of inter-node communications in inter-node deduplication can be reduced and both performance stability and high capacity efficiency can be achieved. A storage drive of storage nodes stores files that are not deduplicated in the plurality of storage nodes, duplicate data storage files in which deduplicated duplicate data is stored, and cache data storage files in which cache data of duplicate data stored in another storage node is stored, in which when a read access request for the cache data is received, the processors of the storage nodes read the cache data if the cache data is stored in the cache data storage file, and request another storage node to read the duplicate data related to the cache data if the cache data is discarded.

Abstract: Systems and methods for capped allocation of storage resources based on connection type are described. A new storage connection request from a host system to a group of data storage devices includes a connection type, such as a remote direct memory access connection or transmission control protocol connection. Based on the connection type, a subset of a pool of allocated storage resources for that connection type is determined. If the new connection request does not exceed the maximum number of connections allocated to the subset, a new storage connection is established. If the new connection request exceeds the maximum number of connections allocated to the subset, the new storage connection request fails.

Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Abstract: A method, computer program product, and computing system for use in a clustered storage system are provided. Embodiments may include providing, using a management network, one or more of external access to the clustered storage system, management of intra-cluster traffic, management of hypervisor traffic, and access to infrastructure services. Embodiments may further include allowing, using a storage network, access to the clustered storage system from within the clustered storage system and one or more external hosts. Embodiments may also include providing a migration network to allow for mobility of one or more virtual machines within clustered storage system. Embodiments may further include splitting the management network into a public management network and an internal intra-cluster management network.

Abstract: The present disclosure relates to a method, a device, and a computer program product for managing a storage system. The storage system includes a first control node, a second control node, and a persistent storage device, the first control node being in an activated state, and the second control node being in a state of transfer from a non-activated state to an activated state. A method includes: loading a first list of page descriptors of the storage system to the second control node to generate a second list of page descriptors at the second control node, the first list including a portion of multiple page descriptors of the storage system that has been modified but has not been flushed to the persistent storage device; receiving a synchronization message from the first control node that indicates that the first list has been modified by the first control node; and updating the second list at the second control node based on the synchronization message.

Abstract: Described are methods and a system for atomic memory operations with contended cache lines. A processing system includes at least two cores, each core having a local cache, and a lower level cache in communication with each local cache. One local cache configured to request a cache line to execute an atomic memory operation (AMO) instruction, receive the cache line via the lower level cache, receive a probe downgrade due to other local cache requesting the cache line prior to execution of the AMO, and send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.

Abstract: Methods and systems are presented for testing software applications in a production-like environment that simulates real-world failures of production environments. A production environment has production applications and databases configured to process user requests from users for conducting transactions with a service provider. A testing system provides an intermediate interface that enables a software application operating in the test environment to access at least one of a production application or a production database. The intermediate interface can be configured based on different failure configurations to simulate production component failures in the production environment. Failure injection and randomized failure modes can be employed, including for network-related failures (latency, dropped packets, connections, etc.) that might occur in the production environment.

Abstract: Techniques for implementing RDMA-based recovery of dirty data in remote memory are provided. In one set of embodiments, upon occurrence of a failure at a first (i.e., source) host system, a second (i.e., failover) host system can allocate a new memory region corresponding to a memory region of the source host system and retrieve a baseline copy of the memory region from a storage backend shared by the source and failover host systems. The failover host system can further populate the new memory region with the baseline copy and retrieve one or more dirty page lists for the memory region from the source host system via RDMA, where the one or more dirty page lists identify memory pages in the memory region that include data updates not present in the baseline copy. For each memory page identified in the one or more dirty page lists, the failover host system can then copy the content of that memory page from the memory region of the source host system to the new memory region via RDMA.

Abstract: Provided herein are systems, methods and computer readable media for providing an out of band cache mechanism for ensuring availability of data. An example system may include a client device configured to, in response to determining requested data is not available in a cache, access the requested data from a data source, transmit, to a cache mechanism, an indication that the requested data is unavailable in the cache, the indication configured to be placed in a queue as an element pointing to the requested data, a cache mechanism configured to receive an indication of requested data, determine whether an element, the element indicative of the requested data, exists in a queue, and in an instance in which the element is not present in the queue, placing the element in the queue, the queue being a list of elements, each indicative of requested data needing to be placed in the cache.

Abstract: A network system includes a storage unit that stores topology information in a graph database in chronological order, the topology information including end point information and connection information of logical resources of the virtual network, end point information and connection information of physical resources of the physical network, and correspondence information between the logical resources and the physical resources; a setting information acquirer that acquires setting information of the virtual network from the orchestrator using a change notification from the orchestrator as a trigger; and a topology information management unit that updates the topology information stored in the graph database of the storage unit on the basis of the acquired setting information.

Abstract: Methods of memory allocation map registers referenced by different groups of instances of the same task to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, relating to multi-task recurrent neural networks. One of the methods includes maintaining data specifying, for a recurrent neural network, a separate internal state for each of a plurality of memory regions; receiving a current input; identifying a particular memory region of the memory access address defined by the current input; selecting, from the internal states specified in the maintained data, the internal state for the particular memory region; processing, in accordance with the selected internal state for the particular memory region, the current input in the sequence of inputs using the recurrent neural network to: generate an output, the output defining a probability distribution of a predicted memory access address, and update the selected internal state of the particular memory region; and associating the updated selected internal state with the particular memory region in the maintained data.

Abstract: A memory system includes: a memory device suitable for storing map information; and a controller suitable for storing a portion of the map information in a map cache, and accessing the memory device based on the map information stored in the map cache or accessing the memory device based on a physical address that is selectively provided together with an access request from a host, wherein the map cache includes a write map cache suitable for storing map information corresponding to a write command, and a read map cache suitable for storing map information corresponding to a read command, and wherein the controller provides the host with map information that is outputted from the read map cache.

Abstract: Embodiments of the disclosure provide techniques managing a log-structured solid state drive (SSD) format in a distributed storage system. SSDs in the distributed storage system maintains a journal of logical changes to storage objects to persist prepared and committed changes in the latency path. The journal includes metadata entries that describe changes and reference data pages. Dense data structures (such as a logical block addressing table) index the metadata entries. To reduce the amount of overhead in I/O operations, the distributed storage system maintains the dense data structures in memory rather than on disk.

Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

Abstract: A method for allocating memory in a computing device having a non-volatile main memory is described. The method comprises receiving, by a memory allocator, a request for non-volatile memory allocation of an object from a program executing on the computing device, the request comprising a requested memory size and registration data from the program. The method comprises finding an available address of one of a plurality of portions of a page of the non-volatile memory and searching an active page table in the non-volatile main memory to find the page and if the page is not found in the active page table: inserting the page into the active page table; and waiting for a memory write for inserting the page into the active page table to complete.

Abstract: A multi-core architecture including: a plurality of processing devices, each processing device including a single processor or a cluster of processors; and a lock manager associated with each processing device, each lock manager being configured to: store a first data value indicating of whether or not it currently owns a first lock, the first lock authorizing access to a resource; and permit an owner of the first lock to be determined by one or more lock managers by broadcasting, over an interconnection network to each of the other lock managers, at least one message.

Abstract: An application and system fast launch may provide a virtual memory address area (VMA) container to manage the restore of a context of a process, i.e., process context, saved in response to a checkpoint to enhance performance and to provide a resource efficient fast launch. More particularly, the fast launch may provide a way to manage, limit and/or delay the restore of a process context saved in response to a checkpoint, by generating a VMA container comprising VMA container pages, to restore physical memory pages following the checkpoint based on the most frequently used or predicted to be used. The application and system fast launch with the VMA container may avoid unnecessary input/output (I/O) bandwidth consumption, page faults and/or memory copy operations that may otherwise result from restoring the entire context of a VMA container without regard to frequency of use.

Abstract: A system architecture can be used to facilitate communication among applications that are native and/or non-native to an application environment. The system architecture can include a first application environment executed on a client-side computing device. The first application environment can execute software applications that are native thereto. The first application environment can further execute software applications that are native thereto, but which software applications themselves comprise second application environments of types different from the first application environment, and which software applications can therefore execute additional software applications that are non-native to the first application environment. The first application environment can further execute a computation engine that is configured to store and execute instructions received from the first software application, the second software application, or both.

Abstract: A computer system includes a use state analysis program that acquires a use history of data in a first computer system and a program that uses the data; and a data migration program that extracts data that is able to be migrated from the first computer system to a second computer system on the basis of the use history, writes the migratable data to a first storage system and a second storage system, and migrates a program to the second computer system on the basis of a use history of the data used by the program.

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

Abstract: A memory system may include a cache memory, a nonvolatile memory, a write back wait queue, and a controller. To evict an eviction cache entry including a target transaction ID from the memory cache to the nonvolatile memory, the controller performs write back operations on cache entries respectively corresponding to waiting entries at a head of the write back wait queue until a waiting entry including the target transaction ID arrives at the head of the write back wait queue, and then performs a write back operation on the eviction cache entry.

Abstract: Shared memory caching resolves latency issues in computing nodes associated with a cluster in a virtual computing environment. A portion of random access memory in one or more of the computing nodes is allocated for shared use by the cluster. Whenever local cache memory is unable in one of the computing nodes, a cluster neighbor cache allocated in a different computing node may be utilized as remote cache memory. Neighboring computing nodes may thus share their resources for the benefit of the cluster.

Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.

Abstract: Systems and techniques for automatic smart propagation of caching directives are described herein. A request may be received for an object of a webpage. A cache state may be determined for a cache control header retrieved for the object. A time to live value may be calculated for the object based on the cache state and a header time to live value included in the cache control header. A cache directive that includes the time to live value may be stored for the object in a cache. The object may be updated in the cache upon receipt of a subsequent request based on the cache directive.

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

Abstract: A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.

Abstract: Lazy Persistency (LP), a software persistency method that allows caches to slowly send dirty blocks to the non-volatile main memory (NVMM) through natural evictions. With LP, there are no additional writes to NVMM, no decrease in write endurance, and no performance degradation from cache line flushes and barriers. Persistency failures are discovered using software error detection (checksum), and the system recovers from them by recomputing inconsistent results. LP was evaluated and compared to the state-of-the-art Eager Persistency technique from prior work. Compared to Eager Persistency, LP reduces the execution time and write amplification overheads from 9% and 21% to only 1% and 3%, respectively.

Abstract: A method of shuffling turbo-write buffers of a universal flash storage system is described. The method includes periodically determining a performance index of each turbo-write buffer allocated to a unique logical unit number of the universal flash storage system. The method also includes shifting a position of at least two of the turbo-write buffers according to the performance index of each of the turbo-write buffers and a threshold performance level.

Abstract: Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.

Abstract: Non-volatile storage circuitry is provided as primary storage accessible to processing circuitry, e.g. as registers, a cache, scratchpad memory, TLB or on-chip RAM. Power control circuitry powers down a given region of the non-volatile storage circuitry when information stored in said given region is not being used. This provides opportunities for more frequent power savings than would be possible if primary storage was implemented using volatile storage.

Abstract: A memory system includes a memory device and a controller. The memory device stores a piece of data in a location which is distinguished by a physical address. The controller generates map data, each piece of map data associating a logical address, inputted along with a request from an external device, with the physical address, selects a piece of map data among the map data based on a status regarding the piece of map data, and transfers selected map data to the external device.

Abstract: The static data masking system may perform one or more operations including unbinding tables in a database, evaluating masking operations on the tables to determine that at least one masking operation on a particular column of a candidate table is a complex masking operation that cannot be completed using a query, adding a temporary key column with unique values to the candidate table, generating a temporary table including the temporary key column and an empty masked column, generating masked values for the particular column at a client, and populating the masked values for the particular column in the empty masked column of the temporary table.

Abstract: The disclosed computer-implemented method for distributing information across failure domains in servers may include (1) dividing, at a computing device, each of a quantity of “K” failure domains (FDs) in a plurality of FDs into a quantity of “P” portions, where the “K” FDs in the plurality of FDs are constituent parts of respective servers in a plurality of servers, “P” is less than “K,” and “P” is a sum of a quantity of “M” data portions and a quantity of “N” parity portions, (2) creating a quantity of “K” erasure-coded volumes in the “K” FDs, where each erasure-coded volume includes “M” data portions and “N” parity portions, and each portion in each erasure-coded volume is stored in a different FD and (3) combining the “K” volumes to create a file system. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Three new software instructions assist a processor in performing indirect prefetching, and managing a next-to-prefetch address list. The software instructions populate hardware register locations according to a hardware register description comprising a data structure of at least seven fields. Multiple instances of the data structure, shared across multiple respectively corresponding threads running concurrently, comprise an indirect-prefetch-tracker table. The indirect-prefetch-tracker table assists the processor to efficiently perform indirect prefetching, from random (not necessarily contiguous) memory locations, and reduces processor core real estate dedicated to control and management of data prefetch and loading operations.

Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.

Abstract: A dedicated input/output (I/O) cache can be used for I/O-to-processor communications. Data received from an I/O device can be written to the I/O cache and also written to a device memory that is accessible to the processor. The processor can then access the data in the fast, dedicated I/O cache if available. Otherwise, the processor can read the data from the memory into a conventional processor cache for processing. Writes to the cache can be full or partial, with partial writes utilizing padding in some embodiments. The data can be written sequentially in a circular manner. Data processed by the processor can be invalidated, and invalidated data can be overwritten on a subsequent write. Phase bits can also be used to indicate the pass during which various writes were performed.