Associative Patents (Class 711/128)
  • Patent number: 11216382
    Abstract: A cache system may maintain size and/or request rate metrics for objects in a lower level cache and for objects in a higher level cache. When an L1 cache does not have an object, it requests the object from an L2 cache and sends to the L2 cache aggregate size and request rate metrics for objects in the L1 cache. The L2 cache may obtain a size metric and a request rate metric for the requested object and then determine, based on the aggregate size and request rate metrics for the objects in the L1 cache and the size metric and the request rate metric for the requested object in the L2 cache, an indication of whether or not the L1 cache should cache the requested object. The L2 cache provides the object and the indication to the L1 cache.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: January 4, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Karthik Uthaman, Ronil Sudhir Mokashi, Prashant Verma
  • Patent number: 11210020
    Abstract: A memory access technology applied to a computer system includes a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. A plurality of access requests for accessing different memory blocks has a mapping relationship with a first cache line in the first-level memory, and the memory controller compares tags of the plurality of access requests with a tag of the first cache line in a centralized manner to determine whether the plurality of access requests hit the first-level memory.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 28, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shihai Xioa, Qiaosha Zou, Wei Yang
  • Patent number: 11204869
    Abstract: One embodiment provides a system for facilitating data placement. The system receives a sector of data to be written to a first non-volatile memory and a second non-volatile memory, wherein the first non-volatile memory resides on a first storage device which supports sequential writes, and wherein the second non-volatile memory resides on a second storage device. The system writes the sector and its corresponding logical block address to the first non-volatile memory in a sequential manner. The system writes, at approximately a same time, the sector and its corresponding logical block address to the second non-volatile memory. In response to completing the write to the first non-volatile memory or the second non-volatile memory, the system generates an acknowledgment that the sector is successfully committed for a host from which the sector is received.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 21, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11188468
    Abstract: A processor includes a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets, each of the sets has a hot way number, at least one warm way number, and at least one confidence value corresponding to the at least one warm way number. The prediction logic circuit generates a prediction result by predicting if the at least one warm way number is an opened way. The prediction verification circuit generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. The prediction verification circuit updates the hot way number, the at least one warm way number and the at least one confidence value of the at least one warm way number according to the update information.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 30, 2021
    Assignee: ANDES TECHNOLOGY CORPORATION
    Inventors: Kun-Ho Liu, Chieh-Jen Cheng, Chuan-Hua Chang, I-Cheng Kevin Chen
  • Patent number: 11138119
    Abstract: There is provided an apparatus that includes storage circuitry. The storage circuitry is made up from a plurality of sets, each of the sets having at least one storage location. Receiving circuitry receives an access request that includes an input address. Lookup circuitry obtains a plurality of candidate sets that correspond with an index part of the input address. The lookup circuitry determines a selected storage location from the candidate sets using an access policy. The access policy causes the lookup circuitry to iterate through the candidate sets to attempt to locate an appropriate storage location. The appropriate storage location is accessed in response to the appropriate storage location being found.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: October 5, 2021
    Assignee: Arm Limited
    Inventors: Damien Guillaume Pierre Payet, Natalya Bondarenko, Florent Begon, Lucas Garcia
  • Patent number: 11126714
    Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 21, 2021
    Assignee: Arm Limited
    Inventors: Alastair David Reid, Dominic Phillip Mulligan, Milosch Meriac, Matthias Lothar Boettcher, Nathan Yong Seng Chong, Ian Michael Caulfield, Peter Richard Greenhalgh, Frederic Claude Marie Piry, Albin Pierrick Tonnerre, Thomas Christopher Grocutt, Yasuo Ishii
  • Patent number: 11119780
    Abstract: A device including a processor configured to access data to execute multiple instructions and a first cache coupled to the processor, are provided. The first cache is configured to hold a first data fetched from a memory by a first instruction that has been retired. The device also includes a side cache coupled to the first cache and to the processor, the side cache configured to hold a second data fetched from the memory by a second instruction, wherein the second instruction has not been retired from the processor. And the device includes a cache management unit configured to move the second data from the side cache to the first cache when the second instruction is retired, the cache management unit further configured to discard the second data when it is determined that the second instruction is abandoned.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 14, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Gregg B. Lesartre
  • Patent number: 11106599
    Abstract: A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node indicator whose value determines the side of the tree structure to which a next memory element replacement operation is directed, and circuitry to cause, responsive to a miss in the associative memory while the decision node indicator points to the minority side of the tree structure, the decision node indicator to point a majority side of the tree structure, and to determine, responsive to a miss while the decision node indicator points to the majority side of the tree structure, whether or not to cause the decision node indicator to point to the minority side of the tree structure, the determination being dependent on a current replacement weight value. The replacement weight value may be counter-based or a probabilistic weight value.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Chunhui Zhang, Robert S. Chappell, Yury N. Ilin
  • Patent number: 11099998
    Abstract: A computer-implemented method includes caching data from a persistent storage device into a cache. The method also includes caching a physical address and a logical address of the data in the persistent storage device into the cache. The method further includes in response to receiving an access request for the data, accessing the data cached in the cache using at least one of the physical address and the logical address. The embodiments of the present disclosure also provide an electronic apparatus and a computer program product.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: August 24, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Wei Cui, Denny Dengyu Wang, Jian Gao, Lester Zhang, Chen Gong
  • Patent number: 11073995
    Abstract: A method and device generates a slab identifier and a hash function identifier in response to a memory allocation request with a request identifier and allocation size from a memory allocation requestor. The slab identifier indicates a memory region associated with a base data size and the hash function identifier indicates a hash function. The method and device provides a bit string including the slab identifier and the hash function identifier to the memory allocation requestor.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: July 27, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Alexander Dodd Breslow
  • Patent number: 11074113
    Abstract: A storage system includes at least two independent storage engines interconnected by a fabric, each storage engine having two compute nodes. A shared global memory is implemented using cache slots of each of the compute nodes. Memory access operations to the slots of shared global memory are managed by a fabric adapter to guarantee that the operations are atomic. To enable local cache operations to be managed independent of the fabric adapter, a cache metadata data structure includes a global flag bit for each cache slot, that is used to designate the cache slot as globally available or temporarily reserved for local IO processing. The cache metadata data structure also includes a mutex (Peterson lock) for each cache slot to enforce a mutual exclusion concurrency control policy on the cache slot between the two compute nodes of the storage engine when the cache slot is used for local IO processing.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: July 27, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Steven Ivester, Kaustubh Sahasrabudhe
  • Patent number: 11074185
    Abstract: Provided are a computer program product, system, and method for adjusting a number of insertion points used to determine locations in a cache list at which to indicate tracks. Tracks added to the cache are indicated in a cache list. The cache list has a least recently used (LRU) end and a most recently used (MRU) end. In response to indicating in a cache list an insertion point interval number of tracks in the cache in a cache list, setting an insertion point to indicate one of the tracks of the insertion point interval number of tracks indicated in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11068335
    Abstract: A memory system may include a first memory device including a first input/output buffer, a second memory device including a second input/output buffer, and a cache memory suitable for selectively and temporarily storing first and second data to be respectively programmed in the first and second memory devices. The first data is programmed to the first memory device in a first program section by being stored in the cache memory only in a first monopoly section of the first program section. The second data is programmed to the second memory device in a second program section by being stored in the cache memory only in a second monopoly section of a second program section. The first monopoly section and the second monopoly section are set not to overlap each other.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 20, 2021
    Assignee: SK hynix Inc.
    Inventor: Byoung-Sung You
  • Patent number: 11048636
    Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11024382
    Abstract: Methods, systems, and devices for fully associative cache management are described. A memory subsystem may receive an access command for storing a first data word in a storage component associated with an address space. The memory subsystem may include a fully associative cache for storing the data words associated with the storage component. The memory subsystem may determine an address within the cache to store the first data word. For example, the memory subsystem may determine an address of the cache indicated by an address pointer (e.g., based on the order of the addresses) and determine a quantity of accesses associated with the data word stored in that cache address. Based on the indicated cache address and the quantity of accesses, the memory subsystem may store the first data word in the indicated cache address or a second cache address sequential to the indicated cache address.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Pawlowski
  • Patent number: 11010297
    Abstract: A memory unit includes a data storage to store data, an operation controller to receive operation requests issued by an upstream source, a downstream capabilities storage to store an indication of operations performable by at least one downstream memory unit, and processing circuitry to perform operations on data stored in the data storage under control of the operation controller. When an operation request to perform an operation on target data is received from the upstream request source, the operation controller is arranged to determine when to control the processing circuitry to perform the operation, and when to forward the operation to a downstream memory unit in dependence on whether the target data is stored in the data storage unit and the indication of operations performable by at least one downstream memory unit.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 18, 2021
    Assignee: ARM Limited
    Inventor: Andreas Hansson
  • Patent number: 10990589
    Abstract: A computing apparatus may process an operation. The computing apparatus may output information regarding an aggregation operation and an operand corresponding to a variable stored in a memory, store information regarding an operator and the aggregation operands regarding the aggregation operation, perform a first partial operation with respect to the aggregation operands and store a result value of the first partial operation, and process the aggregation operation based on storing the variable, performing a second partial operation with respect to the result value of the first partial operation stored in the cache and the operand corresponding to the variable, and storing a result value of the second partial operation.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
  • Patent number: 10990575
    Abstract: Technologies are described for a system and method for reorganizing a tablespace in a database such that rows of the tablespace are arranged in a sequence defined in a balanced tree-type clustering index of the tablespace. The method includes sectioning the clustering index and the tablespace into sections including logically distinct sets of data by reading only tree pages of the clustering index to determine logical divisions. The method further includes allocating an amount of output space on a storage device for each section of the tablespace and of the clustering index, to provide for each section a first range of storage space for an output clustering index for the section, and a second range of storage space for an output tablespace for the section. The method further includes scheduling a reorg task for each section, and executing, by at least one processor, the scheduled reorg tasks on the sections.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 27, 2021
    Inventor: Richard E Barry
  • Patent number: 10922230
    Abstract: A processing system indicates the pendency of a memory access request for data at the cache entry that is assigned to store the data in response to the memory access request. While executing instructions, the processor issues requests for data to the cache most proximal to the processor. In response to a cache miss, the cache controller identifies an entry of the cache to store the data in response to the memory access request, and stores an indication that the memory access request is pending at the identified cache entry. If the cache controller receives a subsequent memory access request for the data while the memory access request is pending at the higher level of the memory hierarchy, the cache controller identifies that the memory access request is pending based on the indicator stored at the entry.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 16, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Paul James Moyer
  • Patent number: 10908955
    Abstract: A method is provided. The method comprises: commencing a time window, where the time window has a fixed or variable time duration; determining a shared resource access quota for at least one time partition for the time window, where the shared resource access quota may vary by time window; allocating each determined shared resource access quota to a corresponding time partition for the window; determining if allocated shared resource access quota for any time partition in the time window has been met or exceeded; and if an allocated shared resource access quota for a time partition in the time window has been met or exceeded, then halting an executing process in the time partition.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 2, 2021
    Assignee: Honeywell International Inc.
    Inventors: Srivatsan Varadarajan, Larry James Miller, Chittaranjan Kashiwar, Pavel Zaykov
  • Patent number: 10896103
    Abstract: A first system receives values with identifiers of the values from one or more clients. The first system enters the values sequentially into a first data store. The first system associates each of the values with a sequence ID indicating a position in entry sequence of the values into the first data store. The first system transmits a first identifier of a first value and a first sequence ID associated with the first value to a second system. The first system transmits the first sequence ID and the first value to the second system after transmitting the first identifier and the first sequence ID. The second system holds the first identifier and the first sequence ID transmitted from the first system in a first queue. The second system enters the first value received after the first identifier from the first system into a second data store.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: January 19, 2021
    Assignee: HITACHI, LTD.
    Inventors: Arif Herusetyo Wicaksono, Kazuhide Aikoh
  • Patent number: 10884959
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 5, 2021
    Assignee: Google LLC
    Inventors: Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao, Benjamin Dodge, Albert Meixner, Allan Douglas Knies, Manu Gulati, Rahul Jagdish Thakur, Jason Rupert Redgrave
  • Patent number: 10866904
    Abstract: There is provided an apparatus that includes an input address port to receive an input address from processor circuitry. Address storage stores a translation between the input address and an output address in an output address space. An output address port outputs the output address. An input data port receives data. Data storage stores the data. An output data port outputs the data stored in the data storage and control circuitry causes the data storage to store the translation between the input address and the output address. The control circuitry issues a signal to cause a page walk to occur in response to the input address being absent from the address storage and the data storage.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: December 15, 2020
    Assignee: Arm Limited
    Inventors: Prakash S. Ramrakhyani, Andreas Lars Sandberg, Nikos Nikoleris, Stephan Diestelhorst
  • Patent number: 10810126
    Abstract: The present disclosure is concerned with improvements to cache systems that can be used to improve the performance (e.g. hit performance) and/or bandwidth within a memory hierarchy. For instance, a data processing apparatus is provided that comprises a cache. Access circuitry receives one or more requests for data and when the data is present in the cache the data is returned. Retrieval circuitry retrieves the data and stores the data in the cache, either proactively or in response to the one or more requests for the data. Control circuitry evicts the data from the cache and, in dependence on at least one condition, stores the data in the further cache. The at least one condition comprises a requirement that the data was stored into the cache proactively and that a number of the one or more requests is above a threshold value.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: October 20, 2020
    Assignee: Arm Limited
    Inventors: Joseph Michael Pusdesris, Adrian Montero, Klas Magnus Bruce, Chris Abernathy
  • Patent number: 10795821
    Abstract: A computer system performs a technique for reducing memory usage when a key-value store is being implemented. A first key associated with data is received. A block address of a block of keys is obtained from memory. The block of keys is stored on disk storage, and the keys in the block of keys correspond to respective values stored on the disk storage. The block of keys is obtained from the disk storage using the block address. A second key in the block of keys is located. Locating the second key includes determining that the second key matches the first key. A value of the respective values is obtained using the second key.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: October 6, 2020
    Assignee: VMware, Inc.
    Inventor: Oleg Zaydman
  • Patent number: 10776022
    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 15, 2020
    Assignee: Apple Inc.
    Inventors: James Wang, Zongjian Chen, James B. Keller, Timothy J. Millet
  • Patent number: 10733100
    Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 10725912
    Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Andrew M. Kowles
  • Patent number: 10725527
    Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Oluleye Olorode, Mehrdad Nourani
  • Patent number: 10719434
    Abstract: A cache stores 2{circumflex over (?)}J-byte cache lines has an array of 2{circumflex over (?)}N sets each holds tags each X bits and 2{circumflex over (?)}W ways. An input receives a Q-bit address, MA[(Q?1):0], having a tag MA[(Q?1):(Q?X)] and index MA[(Q?X?1):J]. Q is at least (N+J+X?1). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2{circumflex over (?)}W ways of the selected set when operating in a first mode; and into a subset of the 2{circumflex over (?)}W ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: July 21, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTORS CO., LTD.
    Inventor: Douglas R. Reed
  • Patent number: 10698827
    Abstract: A cache memory comprising: a mode input indicates in which of a plurality of allocation modes the cache memory is to operate; a set-associative array of entries having a plurality of sets by W ways; an input receives a memory address comprising: an index used to select a set from the plurality of sets; and a tag used to compare with tags stored in the entries of the W ways of the selected set to determine whether the memory address hits or misses; and allocation logic, when the memory address misses in the array: selects one or more bits of the tag based on the allocation mode; performs a function, based on the allocation mode, on the selected bits of the tag to generate a subset of the W ways of the array; and allocates into one way of the subset of the ways of the selected set.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: June 30, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Douglas R. Reed
  • Patent number: 10691606
    Abstract: An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided to implement a first cache feature that is applied to the way groups, and second cache feature circuitry is provided to implement a second cache feature that is applied to the way groups. Way group control circuitry is then arranged to provide a first mapping defining which cache ways belong to each way group when the first cache feature is applied to the way groups, and a second mapping defining which cache ways belong to each way group when the second cache feature is applied to the way groups.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 23, 2020
    Assignee: ARM Limited
    Inventors: Davide Marani, Alex James Waugh
  • Patent number: 10691604
    Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dwifuzi Coe, Christian Jacobi, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Patent number: 10684951
    Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dwifuzi Coe, Christian Jacobi, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Patent number: 10650021
    Abstract: A mechanism for managing data operations in an integrated database system. The method includes receiving a request to perform a data operation and retrieving a data set from a primary data source (PDS) in view of the request. The method also includes storing the data set in a temporary data store (TDS). The method further includes performing the data operation on the stored data set in the TDS.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: May 12, 2020
    Assignee: Red Hat, Inc.
    Inventors: Filip Elias, Filip Nguyen
  • Patent number: 10635593
    Abstract: A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Daniel Greenspan, Anant V. Nori, Supratik Majumder, Yoav Lossin, Asaf Rubinstein
  • Patent number: 10628052
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Kaburaki, Katsuya Ohno, Hiroshi Katougi
  • Patent number: 10606509
    Abstract: A data storage device includes a storage medium; a buffer memory configured to temporarily store data to be inputted to, or outputted from, the storage medium; and a controller configured to control data exchange with the storage medium, allocate a write tag to a write command, and change an attribute of the write tag according to a processing status of the write command.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Soong Sun Shin, Han Choi, Jin Soo Kim
  • Patent number: 10606600
    Abstract: Techniques are disclosed for receiving an instruction for processing data that includes a plurality of sectors. A method includes decoding the instruction to determine which of the plurality of sectors are needed to process the instruction and fetching at least one of the plurality of sectors from memory. The method includes determining whether each sector that is needed to process the instruction has been fetched. If all sectors needed to process the instruction have been fetched, the method includes transmitting a sector valid signal and processing the instruction. If all sectors needed to process the instruction have not been fetched, the method includes blocking a data valid signal from being transmitted, fetching an additional one or more of the plurality of sectors until all sectors needed to process the instruction have been fetched, transmitting a sector valid signal, and reissuing and processing the instruction using the fetched sectors.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventor: David A. Hrusecky
  • Patent number: 10599210
    Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-lae Park, Ju-hwan Kim, Bum-gyu Park, Dae-yeong Lee, Dong-hyeon Ham
  • Patent number: 10592414
    Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Simon H. Friedmann, Girish G. Kurup, Markus Kaltenbach, Ulrich Mayer, Martin Recktenwald
  • Patent number: 10585797
    Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
  • Patent number: 10579535
    Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Jared Warner Stark, IV, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler
  • Patent number: 10552331
    Abstract: An arithmetic processing device includes a memory access request issuance unit and a cache including a cache memory for tags and data and a move-in buffer control unit for issuing a move-in request for data on the memory access request when a cache miss occurs. The move-in buffer control unit, when the cache miss occurs, determines to acquire a move-in buffer and issue the move-in request when the memory access request has the same index as an index of any move-in request registered in the move-in buffer and the number of move-in requests of the same index registered in the move-in buffer is less than the number of ways, and determines not to acquire the move-in buffer and does not issue the move-in request when the memory access request has the same index and the number of the move-in requests of the same index reaches the number of the ways.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 4, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yuki Kamikubo, Noriko Takagi, Takahito Hirano
  • Patent number: 10545867
    Abstract: A device, method, and a data storage medium, configured to enhance an item access bandwidth and atomic operation are provided. The device comprises: a comparison module, a cache, and a distribution module; wherein the comparison module is configured to receive a query request from a service side, determine whether an address pointed to by the query request and an item address stored in the cache are identical. If so, and a valid identifier vld is valid, the comparison module is configured to directly return the item data stored in the cache to the service side without initiating a request for looking up an off-chip memory, so as to reduce a frequency of accessing the off-chip memory. If not, the comparison module is configured to initiate a request for looking up the off-chip memory, so as to process, according to a first preconfigured rule, item data returned by the off-chip memory.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: January 28, 2020
    Assignee: SANECHIPS TECHNOLOGY CO., LTD.
    Inventors: Chuang Bao, Zhenlin Yan, Chunhui Zhang, Kang An
  • Patent number: 10522209
    Abstract: One of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) may be repurposed to an address input. One of a plurality of memory ranks of the LRDIMM may be selected based on a remainder of the plurality of chip select inputs. The repurposed chip select input may be used to support non-binary rank multiplication of the LRDIMM.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: December 31, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Melvin K. Benedict
  • Patent number: 10496551
    Abstract: Method, system, and apparatus for leveraging non-uniform miss penalty in cache replacement policy to improve performance and power in a chip multiprocessor platform is described herein. One embodiment of a method includes: determining a first set of cache line candidates for eviction from a first memory in accordance to a cache line replacement policy, the first set comprising a plurality of cache line candidates; determining a second set of cache line candidates from the first set based on replacement penalties associated with each respective cache line candidate in the first set; selecting a target cache line from the second set of cache line candidates; and responsively causing the selected target cache line to be moved from the first memory to a second memory.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Binh Q. Pham, Ren Wang
  • Patent number: 10482018
    Abstract: An arithmetic processing unit includes a cache including a cache memory for storing states of data and data in a block at an index of the memory access request, a move-in buffer control unit that issues a move-in request when cache miss, and move-in buffers for registering the move-in request. The move-in buffer control unit, in response to cache miss, (a) secures a vacant move-in buffer when the vacant move-in buffer exists, (b) issues a move-in request when a move-in request having a same index as the memory access request is not registered in the move-in buffers, (c) issues the move-in request when the move-in request having the same index is registered in the move-in buffers and all ways are not used by the move-in request having the same index in the move-in buffers, and (d) releases the secured move-in buffer when all the ways are used.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yuki Kamikubo, Noriko Takagi
  • Patent number: 10482032
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
  • Patent number: 10467140
    Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: November 5, 2019
    Assignee: Arm Limited
    Inventors: Roko Grubisic, Hakan Persson, Neil Andrew Jameson