Associative Patents (Class 711/128)
-
Patent number: 11074185Abstract: Provided are a computer program product, system, and method for adjusting a number of insertion points used to determine locations in a cache list at which to indicate tracks. Tracks added to the cache are indicated in a cache list. The cache list has a least recently used (LRU) end and a most recently used (MRU) end. In response to indicating in a cache list an insertion point interval number of tracks in the cache in a cache list, setting an insertion point to indicate one of the tracks of the insertion point interval number of tracks indicated in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list.Type: GrantFiled: August 7, 2019Date of Patent: July 27, 2021Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
-
Patent number: 11068335Abstract: A memory system may include a first memory device including a first input/output buffer, a second memory device including a second input/output buffer, and a cache memory suitable for selectively and temporarily storing first and second data to be respectively programmed in the first and second memory devices. The first data is programmed to the first memory device in a first program section by being stored in the cache memory only in a first monopoly section of the first program section. The second data is programmed to the second memory device in a second program section by being stored in the cache memory only in a second monopoly section of a second program section. The first monopoly section and the second monopoly section are set not to overlap each other.Type: GrantFiled: June 18, 2015Date of Patent: July 20, 2021Assignee: SK hynix Inc.Inventor: Byoung-Sung You
-
Patent number: 11048636Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.Type: GrantFiled: July 31, 2019Date of Patent: June 29, 2021Assignee: Micron Technology, Inc.Inventor: Steven Jeffrey Wallach
-
Patent number: 11024382Abstract: Methods, systems, and devices for fully associative cache management are described. A memory subsystem may receive an access command for storing a first data word in a storage component associated with an address space. The memory subsystem may include a fully associative cache for storing the data words associated with the storage component. The memory subsystem may determine an address within the cache to store the first data word. For example, the memory subsystem may determine an address of the cache indicated by an address pointer (e.g., based on the order of the addresses) and determine a quantity of accesses associated with the data word stored in that cache address. Based on the indicated cache address and the quantity of accesses, the memory subsystem may store the first data word in the indicated cache address or a second cache address sequential to the indicated cache address.Type: GrantFiled: August 29, 2019Date of Patent: June 1, 2021Assignee: Micron Technology, Inc.Inventor: Joseph T. Pawlowski
-
Patent number: 11010297Abstract: A memory unit includes a data storage to store data, an operation controller to receive operation requests issued by an upstream source, a downstream capabilities storage to store an indication of operations performable by at least one downstream memory unit, and processing circuitry to perform operations on data stored in the data storage under control of the operation controller. When an operation request to perform an operation on target data is received from the upstream request source, the operation controller is arranged to determine when to control the processing circuitry to perform the operation, and when to forward the operation to a downstream memory unit in dependence on whether the target data is stored in the data storage unit and the indication of operations performable by at least one downstream memory unit.Type: GrantFiled: June 26, 2017Date of Patent: May 18, 2021Assignee: ARM LimitedInventor: Andreas Hansson
-
Patent number: 10990575Abstract: Technologies are described for a system and method for reorganizing a tablespace in a database such that rows of the tablespace are arranged in a sequence defined in a balanced tree-type clustering index of the tablespace. The method includes sectioning the clustering index and the tablespace into sections including logically distinct sets of data by reading only tree pages of the clustering index to determine logical divisions. The method further includes allocating an amount of output space on a storage device for each section of the tablespace and of the clustering index, to provide for each section a first range of storage space for an output clustering index for the section, and a second range of storage space for an output tablespace for the section. The method further includes scheduling a reorg task for each section, and executing, by at least one processor, the scheduled reorg tasks on the sections.Type: GrantFiled: March 22, 2019Date of Patent: April 27, 2021Inventor: Richard E Barry
-
Patent number: 10990589Abstract: A computing apparatus may process an operation. The computing apparatus may output information regarding an aggregation operation and an operand corresponding to a variable stored in a memory, store information regarding an operator and the aggregation operands regarding the aggregation operation, perform a first partial operation with respect to the aggregation operands and store a result value of the first partial operation, and process the aggregation operation based on storing the variable, performing a second partial operation with respect to the result value of the first partial operation stored in the cache and the operand corresponding to the variable, and storing a result value of the second partial operation.Type: GrantFiled: August 9, 2017Date of Patent: April 27, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi
-
Patent number: 10922230Abstract: A processing system indicates the pendency of a memory access request for data at the cache entry that is assigned to store the data in response to the memory access request. While executing instructions, the processor issues requests for data to the cache most proximal to the processor. In response to a cache miss, the cache controller identifies an entry of the cache to store the data in response to the memory access request, and stores an indication that the memory access request is pending at the identified cache entry. If the cache controller receives a subsequent memory access request for the data while the memory access request is pending at the higher level of the memory hierarchy, the cache controller identifies that the memory access request is pending based on the indicator stored at the entry.Type: GrantFiled: July 15, 2016Date of Patent: February 16, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Paul James Moyer
-
Patent number: 10908955Abstract: A method is provided. The method comprises: commencing a time window, where the time window has a fixed or variable time duration; determining a shared resource access quota for at least one time partition for the time window, where the shared resource access quota may vary by time window; allocating each determined shared resource access quota to a corresponding time partition for the window; determining if allocated shared resource access quota for any time partition in the time window has been met or exceeded; and if an allocated shared resource access quota for a time partition in the time window has been met or exceeded, then halting an executing process in the time partition.Type: GrantFiled: March 22, 2018Date of Patent: February 2, 2021Assignee: Honeywell International Inc.Inventors: Srivatsan Varadarajan, Larry James Miller, Chittaranjan Kashiwar, Pavel Zaykov
-
Patent number: 10896103Abstract: A first system receives values with identifiers of the values from one or more clients. The first system enters the values sequentially into a first data store. The first system associates each of the values with a sequence ID indicating a position in entry sequence of the values into the first data store. The first system transmits a first identifier of a first value and a first sequence ID associated with the first value to a second system. The first system transmits the first sequence ID and the first value to the second system after transmitting the first identifier and the first sequence ID. The second system holds the first identifier and the first sequence ID transmitted from the first system in a first queue. The second system enters the first value received after the first identifier from the first system into a second data store.Type: GrantFiled: September 5, 2016Date of Patent: January 19, 2021Assignee: HITACHI, LTD.Inventors: Arif Herusetyo Wicaksono, Kazuhide Aikoh
-
Patent number: 10884959Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.Type: GrantFiled: July 22, 2019Date of Patent: January 5, 2021Assignee: Google LLCInventors: Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao, Benjamin Dodge, Albert Meixner, Allan Douglas Knies, Manu Gulati, Rahul Jagdish Thakur, Jason Rupert Redgrave
-
Patent number: 10866904Abstract: There is provided an apparatus that includes an input address port to receive an input address from processor circuitry. Address storage stores a translation between the input address and an output address in an output address space. An output address port outputs the output address. An input data port receives data. Data storage stores the data. An output data port outputs the data stored in the data storage and control circuitry causes the data storage to store the translation between the input address and the output address. The control circuitry issues a signal to cause a page walk to occur in response to the input address being absent from the address storage and the data storage.Type: GrantFiled: October 24, 2018Date of Patent: December 15, 2020Assignee: Arm LimitedInventors: Prakash S. Ramrakhyani, Andreas Lars Sandberg, Nikos Nikoleris, Stephan Diestelhorst
-
Patent number: 10810126Abstract: The present disclosure is concerned with improvements to cache systems that can be used to improve the performance (e.g. hit performance) and/or bandwidth within a memory hierarchy. For instance, a data processing apparatus is provided that comprises a cache. Access circuitry receives one or more requests for data and when the data is present in the cache the data is returned. Retrieval circuitry retrieves the data and stores the data in the cache, either proactively or in response to the one or more requests for the data. Control circuitry evicts the data from the cache and, in dependence on at least one condition, stores the data in the further cache. The at least one condition comprises a requirement that the data was stored into the cache proactively and that a number of the one or more requests is above a threshold value.Type: GrantFiled: September 24, 2018Date of Patent: October 20, 2020Assignee: Arm LimitedInventors: Joseph Michael Pusdesris, Adrian Montero, Klas Magnus Bruce, Chris Abernathy
-
Patent number: 10795821Abstract: A computer system performs a technique for reducing memory usage when a key-value store is being implemented. A first key associated with data is received. A block address of a block of keys is obtained from memory. The block of keys is stored on disk storage, and the keys in the block of keys correspond to respective values stored on the disk storage. The block of keys is obtained from the disk storage using the block address. A second key in the block of keys is located. Locating the second key includes determining that the second key matches the first key. A value of the respective values is obtained using the second key.Type: GrantFiled: December 4, 2018Date of Patent: October 6, 2020Assignee: VMware, Inc.Inventor: Oleg Zaydman
-
Patent number: 10776022Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.Type: GrantFiled: February 4, 2019Date of Patent: September 15, 2020Assignee: Apple Inc.Inventors: James Wang, Zongjian Chen, James B. Keller, Timothy J. Millet
-
Patent number: 10733100Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.Type: GrantFiled: June 8, 2018Date of Patent: August 4, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventor: Shay Benisty
-
Patent number: 10725527Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.Type: GrantFiled: January 22, 2019Date of Patent: July 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Oluleye Olorode, Mehrdad Nourani
-
Patent number: 10725912Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.Type: GrantFiled: December 19, 2018Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventor: Andrew M. Kowles
-
Patent number: 10719434Abstract: A cache stores 2{circumflex over (?)}J-byte cache lines has an array of 2{circumflex over (?)}N sets each holds tags each X bits and 2{circumflex over (?)}W ways. An input receives a Q-bit address, MA[(Q?1):0], having a tag MA[(Q?1):(Q?X)] and index MA[(Q?X?1):J]. Q is at least (N+J+X?1). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2{circumflex over (?)}W ways of the selected set when operating in a first mode; and into a subset of the 2{circumflex over (?)}W ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion.Type: GrantFiled: December 14, 2014Date of Patent: July 21, 2020Assignee: VIA ALLIANCE SEMICONDUCTORS CO., LTD.Inventor: Douglas R. Reed
-
Patent number: 10698827Abstract: A cache memory comprising: a mode input indicates in which of a plurality of allocation modes the cache memory is to operate; a set-associative array of entries having a plurality of sets by W ways; an input receives a memory address comprising: an index used to select a set from the plurality of sets; and a tag used to compare with tags stored in the entries of the W ways of the selected set to determine whether the memory address hits or misses; and allocation logic, when the memory address misses in the array: selects one or more bits of the tag based on the allocation mode; performs a function, based on the allocation mode, on the selected bits of the tag to generate a subset of the W ways of the array; and allocates into one way of the subset of the ways of the selected set.Type: GrantFiled: December 14, 2014Date of Patent: June 30, 2020Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventor: Douglas R. Reed
-
Patent number: 10691606Abstract: An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided to implement a first cache feature that is applied to the way groups, and second cache feature circuitry is provided to implement a second cache feature that is applied to the way groups. Way group control circuitry is then arranged to provide a first mapping defining which cache ways belong to each way group when the first cache feature is applied to the way groups, and a second mapping defining which cache ways belong to each way group when the second cache feature is applied to the way groups.Type: GrantFiled: December 28, 2016Date of Patent: June 23, 2020Assignee: ARM LimitedInventors: Davide Marani, Alex James Waugh
-
Patent number: 10691604Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.Type: GrantFiled: November 16, 2017Date of Patent: June 23, 2020Assignee: International Business Machines CorporationInventors: Dwifuzi Coe, Christian Jacobi, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Patent number: 10684951Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.Type: GrantFiled: August 4, 2017Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Dwifuzi Coe, Christian Jacobi, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
-
Patent number: 10650021Abstract: A mechanism for managing data operations in an integrated database system. The method includes receiving a request to perform a data operation and retrieving a data set from a primary data source (PDS) in view of the request. The method also includes storing the data set in a temporary data store (TDS). The method further includes performing the data operation on the stored data set in the TDS.Type: GrantFiled: December 3, 2013Date of Patent: May 12, 2020Assignee: Red Hat, Inc.Inventors: Filip Elias, Filip Nguyen
-
Patent number: 10635593Abstract: A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.Type: GrantFiled: October 26, 2017Date of Patent: April 28, 2020Assignee: Intel CorporationInventors: Daniel Greenspan, Anant V. Nori, Supratik Majumder, Yoav Lossin, Asaf Rubinstein
-
Patent number: 10628052Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.Type: GrantFiled: August 27, 2018Date of Patent: April 21, 2020Assignee: Toshiba Memory CorporationInventors: Satoshi Kaburaki, Katsuya Ohno, Hiroshi Katougi
-
Patent number: 10606509Abstract: A data storage device includes a storage medium; a buffer memory configured to temporarily store data to be inputted to, or outputted from, the storage medium; and a controller configured to control data exchange with the storage medium, allocate a write tag to a write command, and change an attribute of the write tag according to a processing status of the write command.Type: GrantFiled: December 13, 2018Date of Patent: March 31, 2020Assignee: SK hynix Inc.Inventors: Soong Sun Shin, Han Choi, Jin Soo Kim
-
Patent number: 10606600Abstract: Techniques are disclosed for receiving an instruction for processing data that includes a plurality of sectors. A method includes decoding the instruction to determine which of the plurality of sectors are needed to process the instruction and fetching at least one of the plurality of sectors from memory. The method includes determining whether each sector that is needed to process the instruction has been fetched. If all sectors needed to process the instruction have been fetched, the method includes transmitting a sector valid signal and processing the instruction. If all sectors needed to process the instruction have not been fetched, the method includes blocking a data valid signal from being transmitted, fetching an additional one or more of the plurality of sectors until all sectors needed to process the instruction have been fetched, transmitting a sector valid signal, and reissuing and processing the instruction using the fetched sectors.Type: GrantFiled: June 3, 2016Date of Patent: March 31, 2020Assignee: International Business Machines CorporationInventor: David A. Hrusecky
-
Patent number: 10599210Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.Type: GrantFiled: January 10, 2018Date of Patent: March 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-lae Park, Ju-hwan Kim, Bum-gyu Park, Dae-yeong Lee, Dong-hyeon Ham
-
Patent number: 10592414Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.Type: GrantFiled: July 14, 2017Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Girish G. Kurup, Markus Kaltenbach, Ulrich Mayer, Martin Recktenwald
-
Patent number: 10585797Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: GrantFiled: July 14, 2017Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
-
Patent number: 10579535Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.Type: GrantFiled: December 15, 2017Date of Patent: March 3, 2020Assignee: Intel CorporationInventors: Lihu Rappoport, Jared Warner Stark, IV, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler
-
Patent number: 10552331Abstract: An arithmetic processing device includes a memory access request issuance unit and a cache including a cache memory for tags and data and a move-in buffer control unit for issuing a move-in request for data on the memory access request when a cache miss occurs. The move-in buffer control unit, when the cache miss occurs, determines to acquire a move-in buffer and issue the move-in request when the memory access request has the same index as an index of any move-in request registered in the move-in buffer and the number of move-in requests of the same index registered in the move-in buffer is less than the number of ways, and determines not to acquire the move-in buffer and does not issue the move-in request when the memory access request has the same index and the number of the move-in requests of the same index reaches the number of the ways.Type: GrantFiled: August 23, 2017Date of Patent: February 4, 2020Assignee: FUJITSU LIMITEDInventors: Yuki Kamikubo, Noriko Takagi, Takahito Hirano
-
Patent number: 10545867Abstract: A device, method, and a data storage medium, configured to enhance an item access bandwidth and atomic operation are provided. The device comprises: a comparison module, a cache, and a distribution module; wherein the comparison module is configured to receive a query request from a service side, determine whether an address pointed to by the query request and an item address stored in the cache are identical. If so, and a valid identifier vld is valid, the comparison module is configured to directly return the item data stored in the cache to the service side without initiating a request for looking up an off-chip memory, so as to reduce a frequency of accessing the off-chip memory. If not, the comparison module is configured to initiate a request for looking up the off-chip memory, so as to process, according to a first preconfigured rule, item data returned by the off-chip memory.Type: GrantFiled: May 10, 2016Date of Patent: January 28, 2020Assignee: SANECHIPS TECHNOLOGY CO., LTD.Inventors: Chuang Bao, Zhenlin Yan, Chunhui Zhang, Kang An
-
Patent number: 10522209Abstract: One of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) may be repurposed to an address input. One of a plurality of memory ranks of the LRDIMM may be selected based on a remainder of the plurality of chip select inputs. The repurposed chip select input may be used to support non-binary rank multiplication of the LRDIMM.Type: GrantFiled: November 13, 2013Date of Patent: December 31, 2019Assignee: Hewlett Packard Enterprise Development LPInventor: Melvin K. Benedict
-
Patent number: 10496551Abstract: Method, system, and apparatus for leveraging non-uniform miss penalty in cache replacement policy to improve performance and power in a chip multiprocessor platform is described herein. One embodiment of a method includes: determining a first set of cache line candidates for eviction from a first memory in accordance to a cache line replacement policy, the first set comprising a plurality of cache line candidates; determining a second set of cache line candidates from the first set based on replacement penalties associated with each respective cache line candidate in the first set; selecting a target cache line from the second set of cache line candidates; and responsively causing the selected target cache line to be moved from the first memory to a second memory.Type: GrantFiled: June 28, 2017Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Binh Q. Pham, Ren Wang
-
Patent number: 10482032Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.Type: GrantFiled: April 12, 2018Date of Patent: November 19, 2019Assignee: International Business Machines CorporationInventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
-
Patent number: 10482018Abstract: An arithmetic processing unit includes a cache including a cache memory for storing states of data and data in a block at an index of the memory access request, a move-in buffer control unit that issues a move-in request when cache miss, and move-in buffers for registering the move-in request. The move-in buffer control unit, in response to cache miss, (a) secures a vacant move-in buffer when the vacant move-in buffer exists, (b) issues a move-in request when a move-in request having a same index as the memory access request is not registered in the move-in buffers, (c) issues the move-in request when the move-in request having the same index is registered in the move-in buffers and all ways are not used by the move-in request having the same index in the move-in buffers, and (d) releases the secured move-in buffer when all the ways are used.Type: GrantFiled: August 23, 2018Date of Patent: November 19, 2019Assignee: FUJITSU LIMITEDInventors: Yuki Kamikubo, Noriko Takagi
-
Patent number: 10467140Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.Type: GrantFiled: April 14, 2016Date of Patent: November 5, 2019Assignee: Arm LimitedInventors: Roko Grubisic, Hakan Persson, Neil Andrew Jameson
-
Patent number: 10430341Abstract: A log-structured storage method and a server, where the method includes obtaining a current incremental update of an object when the object is updated, wherein a current version of the object is stored in a log-structured storage area of the server, determining whether there is a previous incremental update of the object stored in the log-structured storage area, writing the current incremental update as a latest incremental update in the log-structured storage area when there is no previous incremental update of the object stored in the log-structured storage area such that the utilization of memory can be improved.Type: GrantFiled: August 31, 2017Date of Patent: October 1, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Vinoth Veeraraghavan, Zhibiao Chen
-
Patent number: 10417005Abstract: A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.Type: GrantFiled: September 11, 2017Date of Patent: September 17, 2019Assignee: Huawei Technologies Co., Ltd.Inventors: Uri Weiser, Tal Horowitz, Jintang Wang
-
Patent number: 10402344Abstract: Methods and systems for in direct data access in, e.g., multi-level cache memory systems are described. A cache memory system includes a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory. The system also includes a first cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer, and a second cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer. Responsive to a memory access request for a cacheline, the cache location buffer generates access information using one of the cache location tables which enables access to the cacheline without performing a tag comparison at the one of the first and second cache memories.Type: GrantFiled: November 20, 2014Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer, Stefanos Kaxiras
-
Patent number: 10402092Abstract: A method may include receiving, by a controller of a storage device and from a host device, a command to resize a first namespace of a plurality of namespaces stored in a non-volatile memory device of the storage device. The method may further include, relocating, by the controller, a physical block address for the non-volatile memory device from an entry in a virtual to physical table identified by a first index value to an entry in the virtual to physical table identified by a second index value, and in response to relocating the physical block address, updating, by the controller, a mapping, by a namespace table, to indicate an initial index value of a second namespace of the plurality of namespaces.Type: GrantFiled: June 1, 2016Date of Patent: September 3, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Dylan Mark Dewitt, Piyush Garg
-
Patent number: 10404603Abstract: An appliance o for evicting data based on traffic priority of data is described. The appliance has one or more processors and includes a compression history manager configured to acquire traffic priority information of data, the data being conveyed over a connection and to assign a compression history set based on the traffic priority information of the data. The compression history manager is also configured to, if cache space does not exist to store the data and another compression history set corresponds to lower traffic priority in a cache queue, evict data from the other compression history set corresponding to lower traffic priority.Type: GrantFiled: January 22, 2016Date of Patent: September 3, 2019Assignee: CITRIX SYSTEMS, INC.Inventors: Praveen Raja Dhanabalan, Chaitra Maraliga Ramaiah, Karthick Srivatsan
-
Patent number: 10380027Abstract: An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. Locally, within an individual memory, the virtual space may be composed of discontinuous “real” segments or “chunks” within the memory, allowing bad blocks of memory to be bypassed without alteration of the virtual addresses. The delays and additional bus traffic associated with translating from virtual to real addresses are substantially reduced or eliminated.Type: GrantFiled: September 29, 2016Date of Patent: August 13, 2019Assignee: Friday Harbor LLCInventors: Jerome Vincent Coffin, Douglas A. Palmer
-
Patent number: 10366013Abstract: The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.Type: GrantFiled: January 15, 2016Date of Patent: July 30, 2019Assignee: Futurewei Technologies, Inc.Inventors: Lee McFearin, Sushma Wokhlu, Alan Gatherer
-
Patent number: 10339055Abstract: A cache system stores a number of different datasets. The cache system includes a number of cache units, each in a state associated with one of the datasets. In response to determining that a hit ratio of a cache unit drops below a threshold, the state of the cache unit is changed and the dataset is replaced with that associated with the new state.Type: GrantFiled: April 20, 2017Date of Patent: July 2, 2019Assignee: Red Hat, Inc.Inventors: Filip Eliá{hacek over (s)}, Filip Nguyen
-
Patent number: 10332614Abstract: Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair.Type: GrantFiled: December 21, 2017Date of Patent: June 25, 2019Assignee: Micron Technology, Inc.Inventor: Todd Houg
-
Patent number: 10320935Abstract: A method includes, with a computing system, receiving a first resource request for a Representational State Transfer (REST) web service, in response to determining that a resource request result of the first resource request is not cached, passing the first resource request to the REST web service, receiving from the REST web service, the resource request result and metadata associated with the resource request result, the metadata indicating a set of entities associated with the resource request result, caching the result and storing the metadata with the cached result, receiving a second resource request, the second resource request being the same as the first resource request, in response to determining that an entity from the set of entities has changed since the resource request result was cached, invalidating the cached resource request result and passing the first resource request to the REST web service.Type: GrantFiled: January 28, 2015Date of Patent: June 11, 2019Assignee: RED HAT, INC.Inventors: Pavel Slavicek, Rostislav Svoboda
-
Patent number: 10318425Abstract: A method for coordinating cache and memory reservation in a computerized system includes identifying at least one running application, recognizing the at least one application as a latency-critical application, monitoring information associated with a current cache access rate and a required memory bandwidth of the at least one application, allocating a cache partition, a size of the cache partition corresponds to the cache access rate and the required memory bandwidth of the at least one application, defining a threshold value including a number of cache misses per time unit, determining a reduction of cache misses per time unit, in response to the reduction of cache misses per time unit being above the threshold value, retaining the cache partition, assigning a priority of scheduling memory request including a medium priority level, and assigning a memory channel to the at least one application to avoid memory channel contention.Type: GrantFiled: July 12, 2017Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Robert Birke, Yiyu Chen, Navaneeth Rameshan, Martin Schmatz