Abstract: Methods, systems, and computer program products for receiving a memory access request, the memory access request including a virtual memory address; locating a page entry in a page entry structure, the page entry corresponding to the virtual memory address; identifying that a page corresponding to the page entry includes a sub-page, the sub-page included within a subset of a memory space allocated to the page; determining a page frame number corresponding to the sub-page and an offset corresponding to the sub-page; and accessing the offset within the sub-page.

Abstract: A multi-way set associative cache and a processing method thereof, where the cache includes M pipelines, a controller, and a data memory, where any one of the pipelines includes an arbitration circuit, a tag memory, and a determining circuit, where the arbitration circuit receives at least one lookup request at an Nth moment, and determines a first lookup request among the at least one lookup request, the tag memory looks up locally stored tag information according to a first index address in order to acquire at least one target tag address corresponding to the first index address, the determining circuit determines whether an address that matches a first tag address exists in the at least one target tag address, and the controller sends the first lookup request to a next-level device or other pipelines for processing when the address that matches the first tag address does not exist.

Abstract: The present invention provides a data storage device including a flash memory, a random access memory, and a controller. The controller selects a first read command where the required mapping table has already been loaded on the random access memory from a plurality of read commands. Before a first read task prepared by the first read command is executed, the controller selects a second read command from the remaining read commands, selectively reads a first data sector of the first read command and the mapping table of the second read command at the same time, or reads the first data sector and a second data sector of the second read command at the same time.

Abstract: In one embodiment, a computing device receives a request for content in a first portion of a content layout in a displayable region of a screen associated with the computing device. The device may pre-inflate at least one selected element of a display object for a second portion of the content layout, and then store the element in an application-tailored recycler. Selection of the at least one selected element may be based on dimensions of the displayable region, available memory of the computing device, or application-specific rules. The device may then retrieve, in response to a request for content in the second portion of the content layout, the element from the application-tailored recycler, update other elements of the display object as needed for the second portion of the content layout, and return the display object.

Abstract: A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions. The first memory allocator is configured to handle a first memory request size distribution. The second memory allocator is configured to handle a second memory request size distribution. The second memory request size distribution is different than the first memory request size distribution. At least the first memory allocator and the second memory allocator that have been configured are deployed within the computing system in support of at least one application. Deploying at least the first memory allocator and the second memory allocator within the computing system improves at least one of performance and memory utilization of the at least one application.

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Abstract: A set associative cache memory comprises an M×N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one. Within each group of P mutually exclusive groups of the M sets, the N ways are separately powerable. A controller, for each group of the P groups, monitors a utilization trend of the group and dynamically causes power to be provided to a different number of ways of the N ways of the group during different time instances based on the utilization trend.

Abstract: A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions. The first memory allocator is configured to handle a first memory request size distribution. The second memory allocator is configured to handle a second memory request size distribution. The second memory request size distribution is different than the first memory request size distribution. At least the first memory allocator and the second memory allocator that have been configured are deployed within the computing system in support of at least one application. Deploying at least the first memory allocator and the second memory allocator within the computing system improves at least one of performance and memory utilization of the at least one application.

Abstract: Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

Abstract: A data storage subsystem includes a data storage array and a host device in communication with the data storage array. Applications on servers and user terminals communicate with the host to access data maintained by the storage array. In order to enhance performance, the host includes a cache resource and a computer program including cache configuration logic which determines whether an IO received from an application is associated with a predetermined type of business process, and configures the cache resource to store data associated with the received IO where it is determined that the IO is associated with the predetermined type of business process, thereby enabling the data to be available directly from the host without accessing the storage subsystem in response to a subsequent Read request.

Abstract: An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.

Abstract: Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache).

Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

Abstract: Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.

Abstract: A set associative cache memory, comprising: an array of storage elements arranged as N ways; an allocation unit that allocates the storage elements of the array in response to memory accesses that miss in the cache memory; wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs, wherein the MAT is received by the cache memory; a mapping that, for each MAT of the plurality of predetermined MATs, associates the MAT with a subset of one or more ways of the N ways; wherein for each memory access of the memory accesses, the allocation unit allocates into a way of the subset of one or more ways that the mapping associates with the MAT of the memory access; and wherein the mapping is dynamically updatable during operation of the cache memory.

Abstract: In dynamic data access, a request is received to access data of a core data service view of an in-memory database. It is determined that an aging temperature parameter is specified in an annotation in a core data service view definition. An aging temperature value corresponding to the aging temperature parameter is received as a range restriction. A default access behavior associated with the core data service view definition is overridden. A partition where the aging temperature value lies in a secondary memory is determined. Latest or recent partition in the secondary memory is referred to as a latest partition. Data from the latest partition until the determined partition is accessed in the secondary memory. The accessed data is loaded from the secondary memory to the main memory.

Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.

Abstract: In a network element a decision apparatus has a plurality of multi-way hash tables of single size and double size associative entries. A logic pipeline extracts a search key from each of a sequence of received data items. A hash circuit applies first and second hash functions to the search key to generate first and second indices. A lookup circuit reads associative entries in the hash tables that are indicated respectively by the first and second indices, matches the search key against the associative entries in all the ways. Upon finding a match between the search key and an entry key in an indicated associative entry. A processor uses the value of the indicated associative entry to insert associative entries from a stash of associative entries into the hash tables in accordance with a single size and a double size cuckoo insertion procedure.

Abstract: A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored in the data array of one of the plurality of ways. A way tracker of the cache has a plurality of entries, each entry of the plurality of entries for storing a data item identifier and for storing, in association with the data item identifier, an indication of a selected way of the plurality of ways to indicate that a data item identified by the data item identifier is stored in the selected way. Each entry of the way tracker is further for storing a miss indicator in association with the data item identifier, wherein the miss indicator is set by the cache when a lookup for a data item identified by that data item identifier has resulted in a cache miss. A corresponding method of caching data is also provided.

Abstract: Maintaining store order with high throughput in a distributed shared memory system. A request is received for a first ordered data store and a coherency check is initiated. A signal is sent that pipelining of a second ordered data store can be initiated. If a delay condition is encountered during the coherency check for the first ordered data store, rejection of the first ordered data store is signaled. If a delay condition is not encountered during the coherency check for the first ordered data store, a signal is sent indicating a readiness to continue pipelining of the second ordered data store.

Abstract: A method that may include determining, for each user of a group of users, a time difference between an event of a first type that is related to a storage of a user data unit of the user within a cache of a storage system and to an eviction of the user data unit from the cache, in response to (a) a service-level agreement (SLA) associated with the user and to (b) multiple data hit ratios associated with multiple different values of a time difference between events of the first type and evictions, from the cache, of multiple user data units of the user; and evicting from the cache, based upon the determination, one or more user data units associated with one or more users of the group.

Abstract: A method and apparatus for processing graphic data, which are capable of decreasing a bandwidth of a memory, are provided. The method of processing graphic data includes receiving first graphic data and processing the first graphic data to generate second graphic data, and storing the generated second graphic data in a first shared memory line in which a state bit is set to a first state, wherein the first shared memory line is included in a first memory line set which is a part of an n-way set associative cache structure (n is a natural number equal to or greater than 2), at least one of the memory lines of the first memory line set is set to a second state which is different from the first state, and the state bit represents whether data stored in the memory line is replaceable.

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

Abstract: Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode.

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

Abstract: Some implementations disclosed herein provide techniques for caching memory data and for managing cache retention. Different cache retention policies may be applied to different cached data streams such as those of a graphics processing unit. Actual performance of the cache with respect to the data streams may be observed, and the cache retention policies may be varied based on the observed actual performance.

Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

Abstract: Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores.

Abstract: Described are methods, systems and computer readable media for external table index mapping.

Abstract: An assignment control method including: assigning, by circuitry, a processor core among a plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identifying, by the circuitry, address information of memory area, with which the processor core assigned to the thread accesses, based on identification information identifying the processor core assigned to the thread and associating information stored in a storage unit, the associating information associating identification information of the plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing the process of the thread; and controlling, by the circuitry, the processor core assigned to the thread to access corresponding memory area using the identified address information.

Abstract: Network interface circuitry forms a local node. At least one processor offloads from a host computer at least one stateful communication connection between the host computer and a peer, and also operates a cache coherence protocol to scale coherent memory to multiple nodes. The processor operates the communication protocol processing offload at least in part according to communication connection states maintained in the memory, including accessing each communication connection state in the memory using the access procedure, to access that communication connection state in the memory according to an identifier corresponding to that communication connection state. The processor further operates the cache coherence protocol at least in part according to coherence states maintained in the memory, including accessing each coherence state in the memory using the access procedure, to access that coherence state in the memory according to an identifier corresponding to that coherence state.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.

Abstract: With the increasing demand for improved processor performance, memory systems have been growing increasingly larger to keep up with this performance demand. Caches, which dictate the performance of memory systems are often the focus of improved performance in memory systems, and the most common techniques used to increase cache performance are increased size and associativity. Unfortunately, these methods yield increased static and dynamic power consumption. In this invention, a technique is shown that reduces the power consumption in associative caches with some improvement in cache performance. The architecture shown achieves these power savings by reducing the number of ways queried on each cache access, using a simple hash function and no additional storage, while skipping some pipe stages for improved performance. Up to 90% reduction in power consumption with a 4.6% performance improvement was observed.

Abstract: A computer processing system includes execution logic that generates memory requests that are supplied to a hierarchical memory system. The computer processing system includes a hardware map storing a number of entries associated with corresponding cache lines, where each given entry of the hardware map indicates whether a corresponding cache line i) currently stores valid data in the hierarchical memory system, or ii) does not currently store valid data in hierarchical memory system and should be interpreted as being implicitly zero throughout.

Abstract: A cache memory includes a tag memory array and a data memory array. A control register records a reconfiguration status of at least one cache way, a start address of the tag memory array, and a start address of the data memory array. A memory controller is electrically connected to the tag memory array, the data memory array, and the control register. The memory controller controls a data access state of the tag memory array according to the mode byte and the tag base address. The memory controller controls a data access state of the data memory array according to the mode byte and the data base address. A selection module is electrically connected between the tag memory array, the data memory array, and the memory controller. The cache memory solves the problem of idle tag memory of the tag memory array.

Abstract: Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Abstract: A system includes a set-associative storage container and a processor configured to generate a vector that is a random number. Two or more residue functions are applied to the vector that each produces a state signal including a different number of states based on the vector. A set status is determined that identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.

Abstract: In an approach for backing up designated data located in a cache, data stored within an index of a cache is identified, wherein the data has an associated designation indicating that the data is applicable to be backed up to a higher level memory. It is determined that the data stored to the cache has been updated. A status associated with the data is adjusted, such that the adjusted status indicates that the data stored to the cache has not been changed. A copy of the data is created. The copy of the data is stored to the higher level memory.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: Embodiments of the present invention provide a method and apparatus for removing cached data. The method comprises determining activeness of a plurality of divided lists; ranking the plurality of divided lists according to the determined activeness of the plurality of divided lists. The method comprises removing a predetermined amount of cached data from the plurality of divided lists according to the ranking result when the used capacity in the cache area reaches a predetermined threshold. Through embodiments of the present invention, the activeness of each divided list may be used to wholly measure the heat of access to the cached data included by each divided list, and upon removal, the cached data with lower heat of access in the whole system can be removed and the cached data with higher heat of access in the whole system can be retained so as to improve the read/write rate of the system.

Abstract: Technology is provided for partitioning a shared unified cache in a multi-processor computer system. The technology can receive a request to allocate a portion of a shared unified cache memory for storing only executable instructions, partition the cache memory into multiple partitions, and allocate one of the partitions for storing only executable instructions. The technology can further determine the size of the portion of the cache memory to be allocated for storing only executable instructions as a function of the size of the multi-processor's L1 instruction cache and the number of cores in the multi-processor.

Abstract: A memory management unit for I/O devices uses page table entries to translate virtual addresses to physical addresses. The page table entries include removal rules allowing the I/O memory management unit to delete page table entries without CPU involvement significantly reducing the CPU overhead involved in virtualized I/O data transactions.

Abstract: A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract: A system and methods for automatically detecting temporal music trends by observing music consumption by users of online services, for example, social networks, and user sharing habits. In some embodiments, the system and methods gather music consumption patterns (e.g., downloading, listening, sharing or the like) of users, including music identifiers for a track, album, or playlist in a user's music library and time stamps that indicate consumption times corresponding to the music identifiers. A temporal trends detection engine determines music of interest to users by analyzing music consumption patterns of users, user interests and tastes in music, and social affinity between users. A recommendations engine automatically generates and transmits recommendations of music determined by the temporal trends detection engine to be of interest to users.

Abstract: The present disclosure relates to apparatus, systems, and methods that implement a less-recently-used data eviction mechanism for identifying a memory block of a cache for eviction. The less-recently-used mechanism can achieve a similar functionality as the least-recently-used data eviction mechanism, but at a lower memory requirement. A memory controller can implement the less-recently-used data eviction mechanism by selecting a memory block and determining whether the memory block is one of the less-recently-used memory blocks. If so, the memory controller can evict data in the selected memory block; if not, the memory controller can continue to select other memory blocks until the memory controller selects one of the less-recently-used memory blocks.

Abstract: Process control system and methods are disclosed. An example method includes operating a first cluster including first virtual machines and first servers and operating a second cluster including second virtual machines and second servers. The example method also includes storing first data from the first virtual machines at a first data store of the first cluster and storing a replica of the first data at a second data store of the second cluster. The example method also includes storing second data from the second virtual machines at the second data store and storing a replica of the second data at the first data store and identifying a failure of the first cluster. The method also includes, in response to the failure, restarting the first virtual machines using the second servers and the replica of the first data at the second data store.

Abstract: Front-end optimization (FEO) configuration information is leveraged to identify “key” resources required to load other pages on a site, and to automatically cause key resources to be prefetched to a server, and to the browser. In this approach, an FEO analyzer uses knowledge of configured optimization templates to determine the key resources required to load pages for each template. The key resources for pages belonging to other optimization templates are then selectively prefetched by other pages. In a preferred approach, the FEO analyzer provides an edge server cache process a list of key resources and instructions to prefetch the key resources, as well as instructions to rewrite the HTML of the page to include instructions for the browser to prefetech the key resources. On the client, key resources are prefetched if missing from a cache on the browser. Key resources preferably are stored in the browser's HTML5 local storage cache.

Abstract: A processor includes an instruction fetch unit and an execution unit. The instruction fetch unit retrieves instructions from memory to be executed by the execution unit. The instruction fetch unit includes a branch prediction unit which is configured to predict whether a branch instruction is likely to be executed. The memory includes an instruction cache comprising a portion of the fetch blocks available in the memory. The instruction fetch unit may use a combination of way prediction and serialized access to retrieve instructions from the instruction cache. The instruction fetch unit initially accesses the instruction cache to retrieve the predicted fetch block associated with a way prediction. The instruction fetch unit compares a cache tag associated with the way prediction with the address of the cache line that includes the predicted fetch block. If the tag matches, then the way prediction is correct and the retrieved fetch block is valid.