Abstract: A system is provided. The system includes a storage controller configured to receive a prefetch command from a host interface. The storage controller includes a read cache memory that stores prefetch data in response to the prefetch command and a plurality of storage tiers coupled to the storage controller and providing the prefetch data. The plurality of storage tiers includes a fastest storage tier that stores the prefetch data if the read cache memory discards the prefetch data after storing the prefetch data.

Abstract: The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

Abstract: Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

Abstract: A method for processor parameter adjustment using a performance optimization engine is provided. An aspect includes receiving, by the performance optimization engine comprising a hardware module in a processor of a computer system, a request to adjust an operating parameter of the processor from software that is executing on the computer system. Another aspect includes determining an adjusted value for the operating parameter by the performance optimization engine during execution of the software. Another aspect includes setting the operating parameter to the adjusted value in a parameter register of the processor. Yet another aspect includes executing the software according to the parameter register by the processor.

Abstract: Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, a decoder circuit decodes an instruction, wherein the instruction to include at least an opcode, a field for source operand, and a field for a destination operand. Execution circuitry executes the decoded instruction to determine if a tag from the address from the source operand matches a tag in a selected non-volatile memory address cache (NVMAC) cache line, wherein when there is a match a hit indication is stored in the destination operand, and when there is not a match, a no hit indication is stored in the destination operand and the NVMAC is updated with the tag from the address from the source operand.

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.

Abstract: A cache directory processing method for a multi-core processor system, and directory controllers is presented. The method includes obtaining a first directory entry corresponding to first-type storage space in shared storage space of the multi-core processor system and in a directory of the shared storage space; performing a directory entry combination operation on the first directory entry according to each directory entry in the first directory entry and according to an access type and a sharer, to form a second directory entry of the first-type storage space; and when a record quantity of the second directory entry is less than a record quantity of the first directory entry, replacing the first directory entry with the second directory entry, and using the second directory entry as a directory entry corresponding to the first-type storage space and in the directory of the shared storage space.

Abstract: A method, system and computer program product for cache replacement. The present invention leverages Belady's optimal replacement algorithm by applying it to past cache accesses to inform future cache replacement decisions. The occupied cache capacity of a cache is tracked at every time interval using an occupancy vector. The cache capacity is retroactively assigned to the cache lines of the cache in order of their reuse, where a cache line is considered to a cache hit if the cache capacity is available at all times between two subsequent accesses. The occupancy vector is updated using a last touch timestamp of a current memory address. A determination is made as to whether the current memory address results in a cache hit or a cache miss based on the updated occupancy vector. The replacement state for the cache line is stored using the results of the determination.

Abstract: A system and method for low latency and higher bandwidth communication between a central processing unit (CPU) and an accelerator is disclosed. When the CPU updates a copy of data stored at a shared memory, the CPU also sends an “invalidate” command to a cache coherent interconnect (CCI). The CCI forwards the invalidate command to a dedicated cache register (DCR). The DCR marks its copy of the data as “out-of-date” and requests an up-to-date copy of the data from the CCI. The CCI then retrieves up-to-date data for the DCR. When the DCR receives the up-to-date data from the CCI, the DCR replaces the out-of-date data with the up-to-date data, and marks the up-to-date data with the status of “valid.” The DCR can then provide data to an accelerator with a status of “out-of-date” or “valid.

Abstract: A computer system has a plurality of computer servers, each including at least one central processing unit (CPU). A memory appliance is spaced remotely from the plurality of computer servers. The memory appliance includes a memory controller and random access memory (RAM). At least one photonic interconnection is between the plurality of computer servers and the memory appliance. An allocated portion of the RAM is addressable by a predetermined CPU selected during a configuration event from the plurality of computer servers.

Abstract: A processor includes an arithmetic processing circuit, a cache memory including a plurality of ways, a usage information register storing usage information indicating whether to use each of the plurality of ways, a purge control circuit performing purge processing on a basis of rewriting of the usage information within the usage information register according to an instruction executed by the arithmetic processing circuit, the purge processing including processing of deleting, from the cache memory, target data retained in a target way to be stopped and processing of writing back part of the target data, the part of the target data being data rewritten in the cache memory, to a main memory at a lower level than the cache memory, and an access control circuit controlling accessing the cache memory on a basis of a memory access request received from the arithmetic processing circuit and status of the purge processing.

Abstract: Described are methods, systems and computer readable media for external table index mapping.

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.

Abstract: Methods, systems, and computer program products for receiving a memory access request, the memory access request including a virtual memory address; locating a page entry in a page entry structure, the page entry corresponding to the virtual memory address; identifying that a page corresponding to the page entry includes a sub-page, the sub-page included within a subset of a memory space allocated to the page; determining a page frame number corresponding to the sub-page and an offset corresponding to the sub-page; and accessing the offset within the sub-page.

Abstract: A multi-way set associative cache and a processing method thereof, where the cache includes M pipelines, a controller, and a data memory, where any one of the pipelines includes an arbitration circuit, a tag memory, and a determining circuit, where the arbitration circuit receives at least one lookup request at an Nth moment, and determines a first lookup request among the at least one lookup request, the tag memory looks up locally stored tag information according to a first index address in order to acquire at least one target tag address corresponding to the first index address, the determining circuit determines whether an address that matches a first tag address exists in the at least one target tag address, and the controller sends the first lookup request to a next-level device or other pipelines for processing when the address that matches the first tag address does not exist.

Abstract: The present invention provides a data storage device including a flash memory, a random access memory, and a controller. The controller selects a first read command where the required mapping table has already been loaded on the random access memory from a plurality of read commands. Before a first read task prepared by the first read command is executed, the controller selects a second read command from the remaining read commands, selectively reads a first data sector of the first read command and the mapping table of the second read command at the same time, or reads the first data sector and a second data sector of the second read command at the same time.

Abstract: In one embodiment, a computing device receives a request for content in a first portion of a content layout in a displayable region of a screen associated with the computing device. The device may pre-inflate at least one selected element of a display object for a second portion of the content layout, and then store the element in an application-tailored recycler. Selection of the at least one selected element may be based on dimensions of the displayable region, available memory of the computing device, or application-specific rules. The device may then retrieve, in response to a request for content in the second portion of the content layout, the element from the application-tailored recycler, update other elements of the display object as needed for the second portion of the content layout, and return the display object.

Abstract: A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions. The first memory allocator is configured to handle a first memory request size distribution. The second memory allocator is configured to handle a second memory request size distribution. The second memory request size distribution is different than the first memory request size distribution. At least the first memory allocator and the second memory allocator that have been configured are deployed within the computing system in support of at least one application. Deploying at least the first memory allocator and the second memory allocator within the computing system improves at least one of performance and memory utilization of the at least one application.

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Abstract: A set associative cache memory comprises an M×N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one. Within each group of P mutually exclusive groups of the M sets, the N ways are separately powerable. A controller, for each group of the P groups, monitors a utilization trend of the group and dynamically causes power to be provided to a different number of ways of the N ways of the group during different time instances based on the utilization trend.

Abstract: A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions. The first memory allocator is configured to handle a first memory request size distribution. The second memory allocator is configured to handle a second memory request size distribution. The second memory request size distribution is different than the first memory request size distribution. At least the first memory allocator and the second memory allocator that have been configured are deployed within the computing system in support of at least one application. Deploying at least the first memory allocator and the second memory allocator within the computing system improves at least one of performance and memory utilization of the at least one application.

Abstract: Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

Abstract: A data storage subsystem includes a data storage array and a host device in communication with the data storage array. Applications on servers and user terminals communicate with the host to access data maintained by the storage array. In order to enhance performance, the host includes a cache resource and a computer program including cache configuration logic which determines whether an IO received from an application is associated with a predetermined type of business process, and configures the cache resource to store data associated with the received IO where it is determined that the IO is associated with the predetermined type of business process, thereby enabling the data to be available directly from the host without accessing the storage subsystem in response to a subsequent Read request.

Abstract: An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.

Abstract: Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache).

Abstract: Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.

Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

Abstract: In dynamic data access, a request is received to access data of a core data service view of an in-memory database. It is determined that an aging temperature parameter is specified in an annotation in a core data service view definition. An aging temperature value corresponding to the aging temperature parameter is received as a range restriction. A default access behavior associated with the core data service view definition is overridden. A partition where the aging temperature value lies in a secondary memory is determined. Latest or recent partition in the secondary memory is referred to as a latest partition. Data from the latest partition until the determined partition is accessed in the secondary memory. The accessed data is loaded from the secondary memory to the main memory.

Abstract: A set associative cache memory, comprising: an array of storage elements arranged as N ways; an allocation unit that allocates the storage elements of the array in response to memory accesses that miss in the cache memory; wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs, wherein the MAT is received by the cache memory; a mapping that, for each MAT of the plurality of predetermined MATs, associates the MAT with a subset of one or more ways of the N ways; wherein for each memory access of the memory accesses, the allocation unit allocates into a way of the subset of one or more ways that the mapping associates with the MAT of the memory access; and wherein the mapping is dynamically updatable during operation of the cache memory.

Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.

Abstract: In a network element a decision apparatus has a plurality of multi-way hash tables of single size and double size associative entries. A logic pipeline extracts a search key from each of a sequence of received data items. A hash circuit applies first and second hash functions to the search key to generate first and second indices. A lookup circuit reads associative entries in the hash tables that are indicated respectively by the first and second indices, matches the search key against the associative entries in all the ways. Upon finding a match between the search key and an entry key in an indicated associative entry. A processor uses the value of the indicated associative entry to insert associative entries from a stash of associative entries into the hash tables in accordance with a single size and a double size cuckoo insertion procedure.

Abstract: A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored in the data array of one of the plurality of ways. A way tracker of the cache has a plurality of entries, each entry of the plurality of entries for storing a data item identifier and for storing, in association with the data item identifier, an indication of a selected way of the plurality of ways to indicate that a data item identified by the data item identifier is stored in the selected way. Each entry of the way tracker is further for storing a miss indicator in association with the data item identifier, wherein the miss indicator is set by the cache when a lookup for a data item identified by that data item identifier has resulted in a cache miss. A corresponding method of caching data is also provided.

Abstract: Maintaining store order with high throughput in a distributed shared memory system. A request is received for a first ordered data store and a coherency check is initiated. A signal is sent that pipelining of a second ordered data store can be initiated. If a delay condition is encountered during the coherency check for the first ordered data store, rejection of the first ordered data store is signaled. If a delay condition is not encountered during the coherency check for the first ordered data store, a signal is sent indicating a readiness to continue pipelining of the second ordered data store.

Abstract: A method and apparatus for processing graphic data, which are capable of decreasing a bandwidth of a memory, are provided. The method of processing graphic data includes receiving first graphic data and processing the first graphic data to generate second graphic data, and storing the generated second graphic data in a first shared memory line in which a state bit is set to a first state, wherein the first shared memory line is included in a first memory line set which is a part of an n-way set associative cache structure (n is a natural number equal to or greater than 2), at least one of the memory lines of the first memory line set is set to a second state which is different from the first state, and the state bit represents whether data stored in the memory line is replaceable.

Abstract: A method that may include determining, for each user of a group of users, a time difference between an event of a first type that is related to a storage of a user data unit of the user within a cache of a storage system and to an eviction of the user data unit from the cache, in response to (a) a service-level agreement (SLA) associated with the user and to (b) multiple data hit ratios associated with multiple different values of a time difference between events of the first type and evictions, from the cache, of multiple user data units of the user; and evicting from the cache, based upon the determination, one or more user data units associated with one or more users of the group.

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

Abstract: Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode.

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

Abstract: Some implementations disclosed herein provide techniques for caching memory data and for managing cache retention. Different cache retention policies may be applied to different cached data streams such as those of a graphics processing unit. Actual performance of the cache with respect to the data streams may be observed, and the cache retention policies may be varied based on the observed actual performance.

Abstract: Described are methods, systems and computer readable media for external table index mapping.

Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

Abstract: Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores.

Abstract: An assignment control method including: assigning, by circuitry, a processor core among a plurality of processor cores to a thread in accordance with receiving an instruction for starting a process for the thread; identifying, by the circuitry, address information of memory area, with which the processor core assigned to the thread accesses, based on identification information identifying the processor core assigned to the thread and associating information stored in a storage unit, the associating information associating identification information of the plurality of processor cores with address information of different memory areas each of which corresponds to one of the plurality of processor cores executing the process of the thread; and controlling, by the circuitry, the processor core assigned to the thread to access corresponding memory area using the identified address information.

Abstract: Network interface circuitry forms a local node. At least one processor offloads from a host computer at least one stateful communication connection between the host computer and a peer, and also operates a cache coherence protocol to scale coherent memory to multiple nodes. The processor operates the communication protocol processing offload at least in part according to communication connection states maintained in the memory, including accessing each communication connection state in the memory using the access procedure, to access that communication connection state in the memory according to an identifier corresponding to that communication connection state. The processor further operates the cache coherence protocol at least in part according to coherence states maintained in the memory, including accessing each coherence state in the memory using the access procedure, to access that coherence state in the memory according to an identifier corresponding to that coherence state.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: With the increasing demand for improved processor performance, memory systems have been growing increasingly larger to keep up with this performance demand. Caches, which dictate the performance of memory systems are often the focus of improved performance in memory systems, and the most common techniques used to increase cache performance are increased size and associativity. Unfortunately, these methods yield increased static and dynamic power consumption. In this invention, a technique is shown that reduces the power consumption in associative caches with some improvement in cache performance. The architecture shown achieves these power savings by reducing the number of ways queried on each cache access, using a simple hash function and no additional storage, while skipping some pipe stages for improved performance. Up to 90% reduction in power consumption with a 4.6% performance improvement was observed.

Abstract: A computer processing system includes execution logic that generates memory requests that are supplied to a hierarchical memory system. The computer processing system includes a hardware map storing a number of entries associated with corresponding cache lines, where each given entry of the hardware map indicates whether a corresponding cache line i) currently stores valid data in the hierarchical memory system, or ii) does not currently store valid data in hierarchical memory system and should be interpreted as being implicitly zero throughout.

Abstract: One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.

Abstract: A cache memory includes a tag memory array and a data memory array. A control register records a reconfiguration status of at least one cache way, a start address of the tag memory array, and a start address of the data memory array. A memory controller is electrically connected to the tag memory array, the data memory array, and the control register. The memory controller controls a data access state of the tag memory array according to the mode byte and the tag base address. The memory controller controls a data access state of the data memory array according to the mode byte and the data base address. A selection module is electrically connected between the tag memory array, the data memory array, and the memory controller. The cache memory solves the problem of idle tag memory of the tag memory array.