Abstract: Provided are a method, system and program for selecting storage clusters to use to access storage. Input/Output (I/O) requests are transferred to a first storage cluster over a network to access storage. The storage may be additionally accessed via a second storage cluster over the network and both the first and second storage clusters are capable of accessing the storage. An unavailability of a first storage cluster is detected when the second storage cluster is available. A request is transmitted to hosts over the network to use the second storage cluster to access the storage. Hosts receiving the transmitted request send I/O requests to the storage via the second storage cluster if the second storage cluster is available.

Abstract: One embodiment of the present invention provides a system that facilitates efficient transactional execution. During operation, the system executes a starvation-avoiding transaction for a thread, wherein executing the starvation-avoiding transaction involves: (1) placing load-marks on cache lines which are loaded during the starvation-avoiding transaction; (2) placing store-marks on cache lines which are stored to during the starvation-avoiding transaction; and (3) writing a timestamp value into metadata for load-marked and store-marked cache lines. While the thread is executing the starvation-avoiding transaction, the system prevents other threads from executing another starvation-avoiding transaction. Whereby the load-marks and store-marks prevent interfering accesses from other threads to the cache lines during the starvation-avoiding transaction.

Abstract: The invention relates to a system and method for controlling implementation of a command to a memory device. In the method, it comprises the following steps: monitoring an instruction stream destined for the memory device for an assertion of a command for the memory device; if the command is detected, evaluating whether the command is a restricted command; and if the command is a restricted command, preventing assertion of the command on the memory device.

Abstract: A shared memory controller is provided for controlling access to a shared memory by a plurality of processors. At least one device includes a storage area for storing a respective address range for each of a plurality of memory regions. The at least one device further includes a permission table containing, for each of the plurality of memory regions, read and write permission data for each of the plurality of processors. A memory fault detector is coupled to the at least one device and has an input for receiving a memory access request including a memory address, a processor identification and a read/write indicator. The memory fault detector includes logic for determining whether a memory access according to the memory access request would conflict with the read and write permission data in the permission table.

Abstract: A method and apparatus for collecting information from ports on a storage network and performing flow control is provided. The data collection method and apparatus includes, identifying a data type transported on the storage network, selecting a port-storage identifier to measure the data type transported across the storage network, monitoring the port-storage identifier on the storage network for the data type, and enumerating occurrences of the data type associated with the port-storage identifier while monitoring the port-storage identifier and the data type.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

Abstract: A computing node which reduces substantially and effectively reduces the power consumed by a memory is provided without affecting the efficiency whereby a processor accesses the memory. The computing node executes a user program sent by a control node. In case of which a message including the capacity of the memory required to execute a user program is received, a memory rank corresponding to the capacity of the required memory is made active by a memory controller before the user program is loaded into the memory.

Abstract: Systems and methods for I/O fencing in a shared storage environment are provided. Prior to initiating an I/O request, when feasible, the current time from a local timer is compared to the current state of an interval obtained for the target device. As a result, a device reset occurring while the interval is viable does not arbitrarily end a multiphase I/O operation. However, a device reset occurring once the lease has expired results in a delay or termination of the multiphase I/O operation. As a result, multiphase I/O operations from initiating hosts that have lost contact with the shared storage environment are not allowed to corrupt the shared storage devices.

Abstract: Arrangements for controlling the updating of a storage device, which investigates the number of times that a lock waiting time exceeds an upper limit value to judge whether or not the number of times that the upper limit value has been exceeded exceeds a frequency threshold value; stops the reception of write requests by the file system if the result of this judgment is affirmative; and stops the copy-on-write by cutting off the logical connection between the primary storage device and the secondary storage device.

Abstract: Method and system for managing a heap. A map is employed to indicate which areas of the heap are inaccessible to a program. Such areas constitute garbage which is potentially returnable to a data structure which identifies free storage available for reallocation to the program. By choosing map entries corresponding to portions of storage whose size is of the same order of magnitude as a predetermined minimum unit size for the data structure, a small map can be used. Such a map can be scanned more quickly than a larger map of higher granularity to identify only relatively larger areas of garbage for reallocation.

Abstract: A multiple-processor system and boot procedure are provided. The system includes an integrated circuit having first and second embedded processors. A volatile memory and a non-volatile memory are shared by the first and second processors. The non-volatile memory includes a set of boot load instructions executable by the first and second processors.

Abstract: A system and method operable to manage a message queue is provided. This management may involve out-of-order asynchronous heterogeneous remote direct memory access (RDMA) to the message queue. This system includes a pair of processing devices, a primary processing device and an additional processing device, a memory in storage location and a data bus coupled to the processing devices. The processing devices cooperate to process queue data within a shared message queue wherein when an individual processing device successfully accesses queue data the queue data is locked for the exclusive use of the processing device. When the processing device acquires the queue data, the queue data is locked and the queue data acquired by the acquiring processing device includes the queue data for both the primary processing device and additional processing device such that the processing device has all queue data necessary to process the data and return processed queue data.

Abstract: Locks are used to protect variables. All variables protected by a lock are allocated on a page associated with a lock. When a thread (called the owner) acquires the lock, a local copy of the memory page containing the variable is created, the original memory page is protected, and all access of the variable in the owner thread is directed to the local copy. Upon releasing the lock, the changes from the local copy are carried over to the memory page and the memory page is unprotected. Any concurrent access of the variable by non-owner threads triggers an exception handler (due to the protection mechanism) and delays such an access until after the owner thread has finished accessing the variable.

Abstract: By exploiting an early release facility that may be provided by certain transactional memory designs, we allow for transaction software constructs that wait on removal (or satisfaction) of a condition that would otherwise result in transaction abort. Absent exploitation of such a such a facility, the act of checking the condition would typically introduce a corresponding location into the read set of the transaction, and a subsequent modification of that location that removed (or satisfied) the condition, would result in abortion of the blocked transaction. By exploiting an early release facility such as described herein, a transaction may release the location (or locations) corresponding the condition, retry, and once the transient condition is removed (or satisfied), complete and commit. In this way, computation effort may be conserved while still employing a conceptually simple and convenient coordination facility.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A method of allowing exclusive access to shared data by a computing device and a computer readable article embodying instructions for executing the method. The method includes: reading from a storage unit into a memory a program including a code for execution in a critical section and an instruction to write a value into or read a value from a shared data area in the memory; acquiring a lock on the critical section before start of a first instruction in the critical section; writing a value into a thread-local area in the memory in response to an instruction to write the value into the shared data area; writing into the shared data area the value written into the thread-local area upon completion of a final instruction in the critical section; and releasing the lock on the critical section, thereby allowing exclusive access to shared data.

Abstract: Tasks are assigned to processors of a system. The resident set size of each task is determined, specifying the amount of physical information allocated thereto, and locational information of this memory with respect to the processors is determined. Each task is assigned one processor, based on the task's resident set size, and the locational information of the task's allocated physical memory. Each task is attempted to be assigned to the processor closest to the largest portion of the physical memory allocated thereto. A number of the tasks may be determined as best suited to run on a given processor, but the given processor may be unable to run them all. The processor may be thus assigned only those tasks that have a greatest amount of physical memory allocated that is closest to the processor, such as the greatest amount or percentage of physical memory allocated that is local to the processor.

Abstract: An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.

Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Abstract: A portable storage system for connecting to a host, the portable storage system includes a storage device for storing information and a switch. The switch includes a get mode wherein the host sees only the free space in the storage device and not the part storing the information. Optionally, the portable storage system includes a give mode wherein the storage medium shows an empty space to the host and any file or directory is marked as shared and wherein the host sees a file-system whose size equals the amount of empty storage space on the storage device and an owner mode showing all of the stored information to the host and enabling the owner of the system to uncheck a shared flag on a storage device that received from another user that added files.

Abstract: A method for managing a cluster of file servers is disclosed. The method has the first step of writing coordinating information for a plurality of servers of the cluster of servers to a master mailbox record, the master mailbox record written to a specific location on each disk of a set of lock disks, the set of lock disks having a plurality of disks, the plurality of disks chosen so that in the event of failure of a server of the plurality of servers, at least one lock disk will be available to the remaining servers. The method has the second step of writing a second copy of eth coordinating information to the master mailbox record of the set of lock disks.

Abstract: Kernel and user stack data is stored in relocatable memory. A kernel thread or a user thread can move its own stack data by creating a relocation request and adding the relocation request to a queue of a dedicated thread. The dedicated thread performs the relocation on behalf of the requesting kernel or user thread.

Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.

Abstract: The present disclosure describes a unique way for each of multiple processes to operate in parallel using (e.g., reading, modifying, and writing to) the same shared data without causing corruption to the shared data. For example, each of multiple processes utilizes current and past data values associated with a global counter or clock for purposes of determining whether any shared variables used to produce a respective transaction outcome were modified (by another process) when executing a respective transaction. If a respective process detects that shared data used by respective process was modified during a transaction, the process can abort and retry the transaction rather than cause data corruption by storing locally maintained results associated with the transaction to a globally shared data space.

Abstract: Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.

Abstract: A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.

Abstract: A disk array apparatus capable of effecting saving and operation of data through a simple construction. When a host computer sets “write inhibit” or “read/write inhibit” for an LDEV which is set on a first storage device, this setting is registered in an access attribute management table and is also reflected onto a migration management table. A migration control program moves the LDEV for which access limitation has been set to a lower-speed (lower-performance) second storage device or to an external storage device. When the access limitation is released, the moved LDEV is restored to the first storage device from the storage device to which the LDEV has been moved. By performing migration control in interlocking relation to control of access attributes, it is possible to obtain a simple data saving function and data management function.

Abstract: A method is provided for determining whether a logical processor of an information processing system has access to an address space of the information processing system. An instruction is issued by a first processor, the instruction referencing a target logical processor and a target address space. In response to the instruction, first information is checked to determine whether the target logical processor is running. When it is determined that the target logical processor is not running, second information is checked by a host program to determine whether the target logical processor has access to the target address space.

Abstract: A data storage resource is identifiable by physical addresses, and optionally by a virtual address. A policy defines which resources are accessible and which resources are not accessible. A request to access a resource is allowed if access to the resource is permitted by the policy, and if carrying out the access will not cause virtual addresses to be assigned to resources to which the policy disallows access. Since resources to which access is disallowed do not have virtual addresses, certain types of access requests that identify a resource by a virtual address can be allowed without consulting the policy.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism operating to set a lock when an atomic memory sequence is started and to clear a lock when an atomic memory sequence is completed. In preferred embodiments the lock mechanism comprises one or more storage locations associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.

Abstract: A computing device having partitions, and a method of communicating between partitions, are disclosed wherein each partition comprises at least one address area readable but not writable from the other of the at least two partitions. In one embodiment one partition sends to the other partition a request for information, which information is in the other partition in an address area not accessible to the one partition, the other partition copies the information to an address area accessible to the one partition, and the one partition reads the information from the accessible address area. In another embodiment the at least one accessible address area of each partition includes a data area and a consumer pointer indicating the position to which that partition has read the data area in another partition.

Abstract: A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least one shared resource. The multiple bus interfaces are connected to a multi-layer bus respectively. Furthermore, data buffers for holding read data and write data respectively are provided for each bus interface. An arbiter arbitrates access requests from the respective bus interfaces, and the shared resource reads and writes data in response to the access request which has been given an access right.

Abstract: In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

Abstract: A transactional shared memory system has a plurality of discrete application nodes; a plurality of discrete memory nodes; a network interconnecting the application nodes and the memory nodes, and a controller for directing transactions in a distributed system utilizing the shared memory. The memory nodes collectively provide an address space of shared memory that is provided to the application nodes via the network. The controller has instructions to transfer a batched transaction instruction set from an application node to at least one memory node. This instruction set includes one or more write, compare and read instruction subsets, and/or combinations thereof. At least one subset has a valid non null memory node identifier and memory address range. The memory node identifier may be indicated by the memory address range.

Abstract: A data storage resource is identifiable by physical addresses, and optionally by a virtual address. A policy defines which resources are accessible and which resources are not accessible. A request to access a resource is allowed if access to the resource is permitted by the policy, and if carrying out the access will not cause virtual addresses to be assigned to resources to which the policy disallows access. Since resources to which access is disallowed do not have virtual addresses, certain types of access requests that identify a resource by a virtual address can be allowed without consulting the policy.

Abstract: The present disclosure describes a unique way for each of multiple processes to operate in parallel and use the same shared data without causing corruption to the shared data. For example, during a commit phase, a corresponding transaction can attempt to increment a globally accessible version information variable and store a current value of the globally accessible version information variable for updating version information associated with modified data regardless of whether an associated attempt by the corresponding transaction to modify the globally accessible version information variable was successful. As an alternative mode, a corresponding transaction can merely read and store a current value of the globally accessible version information variable without attempting to update the globally accessible version information variable before such use.

Abstract: Disclosed is a virtual machine monitor (VMM) that controls access to a page table hierarchy by a guest operating system (OS). For example, the guest operating system may operate as part of a virtual machine. Particularly, the virtual machine monitor obtains control of memory access transactions responsive to the guest operating system attempting to access the page table hierarchy. More particularly, when the guest operating system attempts to access a page table, control of memory access transactions is trapped to the virtual machine monitor.

Abstract: To provide a storage system capable of minimizing a performance deterioration, saving power consumption, and realizing a high reliability. A storage system according to the present invention includes a computer, a storage apparatus 1 connected with the computer, and a storage management apparatus connected to the storage apparatus, the storage apparatus including a hard disk unit to control a data write operation and a data read operation between the computer and the hard disk unit, and control on/off states of power supply of the hard disk unit on a group basis, and the system management apparatus collecting running information about the computer and computer execution job information for each computer, and determining an on/off time of the power supply of the hard disk unit on the group basis to record the collected information and the on/off time of the power supply on the group basis.

Abstract: A method for providing proactive synchronization in a computer system includes a processor requesting exclusive access to a given memory resource. The request may include one or more addresses associated with the given memory resource. The method also includes comparing each of the addresses in the request to each address in a plurality of sets of addresses. Each address in the sets of addresses may correspond to a respective memory resource to which a requestor has exclusive access. In addition, in response to any address of the one or more addresses matching any address in the plurality of sets of addresses, the method includes returning a count value associated with the set including the matching address. The count value may be indicative of the number of requestors contending for the matching address. Software may utilize this count value to proactively choose an item with lower contention probabilities in subsequent attempts.

Abstract: A method and apparatus for processing a file system operation at a database server is provided. A request to perform a file system operation on a resource stored in a database is received at a database system. The request may be implemented using the NFS protocol. The request may include state identification data that identifies state information associated with the request. State information associated with the request is retrieved within the database system based on the state identification data. State information is information that describes the operational state of the requestor for a particular file. The request is then processed based, at least in part, on the state identification. File system operations may be processed a database management system to access any data, such as a file, relational data, and object-relational data.

Abstract: A method for denying probes during proactive synchronization includes a first processor operating in an advanced synchronization mode, which includes the first processor specifying and acquiring exclusive access to a given memory resource. During operation in the advanced synchronization mode, specifying comprises executing a code sequence including: one or more locked memory reference instructions having a LOCK prefix and one or more addresses associated with the given memory resource. Specifying also includes executing an ACQUIRE instruction that is subsequent to the one or more locked memory reference instructions. The method further includes a second processor requesting access to the given memory resource and issuing a probe message. In response to receiving the probe message, the first processor responding to the probe message with a failure message, thereby denying the second processor access to the given memory resource.

Abstract: Apparatus for controlling atomic access to a memory includes an access request evaluator for receiving an atomic access request to an address in the memory from a client and determining whether to allow atomic access to the requested address. An access indicator indicates whether a select address is currently under atomic access in the memory, and an access release indicates whether the atomic access is completed at the select address. The access request evaluator enables the client atomic access to the requested address if the access indicator indicates that the requested address is currently not under atomic access.

Abstract: A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation.

Abstract: Each processor in a distributed shared memory system has an associated memory and a coherence directory. The processor that controls a memory is the Home processor. Under certain conditions, another processor may obtain exclusive control of a data block by issuing a Load Lock instruction, and obtaining a writeable copy of the data block that is stored in the cache of the Owner processor. If the Owner processor does not complete operations on the writeable copy of the data prior to the time that the data block is displaced from the cache, it issues a Victim To Shared message, thereby indicating to the Home processor that it should remain a sharer of the data block. In the event that another processor seeks exclusive rights to the same data block, the Home processor issues an Invalidate message to the Owner processor.

Abstract: A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.

Abstract: Enabling secure and efficient marshaling, utilization, and releasing of handles in either of an operating system or runtime environment includes wrapping a handle with a counter to tabulate a number of threads using currently using the handle. Thus, handle administration is implemented to circumvent potential security risks, avoid correctness problems, and foster more efficient handle releasing.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: An apparatus and method for managing a memory of a computer and controlling a booting operation of the computer, are provided. The computer includes a memory having a user area and a protected security area (PSA). The user area has a management area. The method includes assigning a first partition to the user area of the memory; storing first partition information in the management area of the user area, the first partition information pertaining to the first partition; assigning a second partition to the PSA in response to an access signal, the access signal authorizing access to the PSA; storing, in the management area, second partition information pertaining to the second partition; storing the second partition information in the PSA; and removing the second partition information from the management area after storing the second partition information in the PSA.