Abstract: A technique for reducing reader overhead when referencing a shared data element while facilitating realtime-safe detection of a grace period for deferring destruction of the shared data element. The grace period is determined by a condition in which all readers that are capable of referencing the shared data element have reached a quiescent state subsequent to a request for a quiescent state. Common case local quiescent state tracking may be performed using only local per-reader state information for all readers that have not blocked while in a read-side critical section in which the data element is referenced. Uncommon case non-local quiescent state tracking may be performed using non-local multi-reader state information for all readers that have blocked while in their read-side critical section. The common case local quiescent state tracking requires less processing overhead than the uncommon case non-local quiescent state tracking.

Abstract: Described are techniques for providing a host identifier for a host. A first portion including a first identifier associated with a system for the host is received. A second portion including a second identifier generated in accordance with a hardware property of the host is received. The host identifier is formed using the first and second portions. The host identifier is used to uniquely identify the host in a storage area network.

Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.

Abstract: Interrupts and code threads are assigned in a particular way to the core CPUs of a network file server in order to reduce latency for processing client requests for file access. Threads of the network stack are incorporated into real time threads that are scheduled by a real-time scheduler and executed exclusively by a plurality of the core CPUs that are not interrupted by disk adapter interrupts so that the disk adapter interrupts do not interrupt execution of the network stack. Instances of a storage access driver are hard affinity threads, and soft affinity threads include a multitude of instances of a thread of the file system stack for file access request processing so that file access request processing for a multitude of concurrent file access requests is load balanced over the core CPUs.

Abstract: A communication device management program that enables efficient use of memory space in receiving data using remote direct memory access (RDMA) techniques. The receiving node transmits a virtual ID corresponding to a receiving process to a remote sending node. A sending process in the sending node specifies this virtual ID when starting data transmission. If the receiving node has not reserved a memory area corresponding to that virtual ID, the sending node transmits a reservation request to the receiving node, which causes a data receiving memory area to be reserved for use by a communication device in the receiving node. In the sending node, the sending communication device begins sending transmission data in RDMA mode, from a memory area managed by the sending process to the reserved data receiving memory area. The receiving communication device directs incoming transmission data to a memory area managed by the receiving process.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. An enhanced suppression-on-protection facility is provided that enables the determination of which level of protection (host or guest) caused a fault condition, in response to an attempted storage access.

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Abstract: A data object is stored in a hosted storage system and includes an access control list specifying access permissions for data object stored in the hosted storage system. The hosted storage system provides hosted storage to a plurality of clients that are coupled to the hosted storage system. A request to store a second data object is received. The request includes an indicator that the first data object stored in the hosted storage system should be used as an access control list for the second data object. The second data object is stored in the hosted storage system. The first data object is assigned as an access control list for the second data object stored in the hosted storage system.

Abstract: The present invention discloses a Locking Protocol using Dynamic Locks and Dynamic Shared Memory which provides a method whereby a designated critical section monitors object status through employment of counters attached to the object=s definition that will increment and decrement during reading and writing.

Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.

Abstract: Transparent hypervisor pinning of critical memory areas is provided for a shared memory partition data processing system. The transparent hypervisor pinning includes receiving at a hypervisor a hypervisor call initiated by a logical partition to register a logical memory area of the logical partition with the hypervisor. Responsive to this hypervisor call, the hypervisor transparently determines whether the logical memory is a critical memory area for access by the hypervisor. If the logical memory area is a critical memory area, then the hypervisor automatically pins the logical memory area to physical memory of the shared memory partition data processing system, thereby ensuring that the memory area will not be paged-out from physical memory to external storage, and thus ensuring availability of the logic memory area to the hypervisor.

Abstract: Shared storage systems and methods are provided. A particular shared storage system is a system including multiple instances of shared storage. Each of the instances of shared storage includes data and file system metadata separated from the data. The file system metadata includes location data specifying storage location information related to the data. A persistent common view is provided of local and remote files, file systems, and services in the shared storage.

Abstract: In a write protection method for at least one random access memory device, the inherent problems of such memory devices with regard to data integrity and security with respect to hacker attacks, such that they can also be used for secure archiving in particular of a large volume of data, are avoided by virtue of the fact that commands directed to the at least one memory device are received by a write protection device connected upstream of the at least one memory device before said commands are forwarded to the at least one memory device, wherein commands received in the write protection device are compared with a positive list of permitted commands previously stored in the write protection device, wherein in one case, where the comparison determines that a permitted command is present, said command is forwarded to the at least one memory device, and in the other case, where the comparison determines that no permitted command is present, said command is not forwarded to the at least one memory device.

Abstract: A multiport semiconductor memory device and a multiprocessor system employing the same directly accesses a shared nonvolatile memory. The multiport semiconductor memory device includes a plurality of port units coupled with respective corresponding processors. A shared memory area is accessed by both the processors through the port units. A data path control unit controls a data path between the shared memory area and the port units and data transmission/reception is performed between the processors through the shared memory area. An access authority information storage unit is positioned outside of the memory cell array and stores information for an access authority of nonvolatile memory and provides the information to the processors. Accordingly, a direct access is performed by a processor indirectly connected to nonvolatile memory.

Abstract: A memory managing apparatus manages a memory shared by processors. The apparatus includes an allocator, an updater and a releaser. The allocator secures a memory area in the memory allocated to each processor based on a request of each processor and registers reference counters corresponding one-to-one to the processors. The updater adds 1 to a value of the reference counter corresponding to the processor managing the memory area when the memory area is allocated to each processor and subtracts 1 from the value of the reference counter corresponding to the processor managing the memory area when the memory area is released from the processor to which the memory area is allocated. The releaser releases the memory area from the processor to which the memory area is allocated when a sum of the values of the reference counters in the memory area updated by the updater is 0.

Abstract: A method, system, and computer usable program product for using a dual mode reader writer lock. A contention condition is detected in the use of a lock in a data processing system, the lock being used for managing read and write access to a resource in the data processing system. A determination of the data structure used for implementing the lock is made. If the data structure is a data structure of a reader writer lock (RWL), the data structure is transitioned to a second data structure suitable for implementing the DML. A determination is made whether the DML has been expanded. If the DML is not expanded, the DML is expanded such that the data structure includes an original lock and a set of expanded locks. The original lock and each expanded lock in the set of expanded locks forms an element of the DML.

Abstract: Aspects of the present invention comprise systems and methods for protecting multi-threaded access to shared memory. Some aspects provide higher data concurrency than other methods. Some aspects relate to methods and systems that provide access to data for all threads during the first phases of one thread's write operation. Some aspects provide all threads access to a particular data unit until one thread enters the commit phase of the write operation. Some aspects manage a computing data resource such that, when a thread enters the commit phase, all pending read requests are fulfilled, all pending write requests are allowed to proceed to commit phase at which point they are blocked, all new read and write requests are blocked and the commit phase is completed by updating the target data and releasing the blocked requests. Some aspects provide improved concurrency by performing reduced cross-thread interference. Some aspects may be implemented at any level from hardware to high-level languages.

Abstract: A method to qualify access to a block storage device via augmentation of the device's controller and firmware flow. The method employs one or more block exclusion vectors (BEVs) that include attributes specifying allowed access operations for corresponding block address ranges. Logic in accordance with the BEVs is programmed into the controller for the block storage device, such as a disk drive controller for a disk drive. In response to an access request, a block address range corresponding to the storage block(s) requested to be accessed is determined. Based on the BEV entries, a determination is made to whether the determined logical block address range is covered by a corresponding BEV entry. If so, the attributes of the BEV are used to determine whether the access operation is allowed. The method may be used to secure access to firmware stored on a disk drive, thus enabling a system configuration that does not require a conventional firmware storage device.

Abstract: According to an embodiment of the invention, a method for operating a data processing machine is described in which data about a state of the machine is written to a location in storage. The location is one that is accessible to software that may be written for the machine. The state data as written is encoded. This state data may be recovered from the storage according to a decoding process. Other embodiments are also described and claimed.

Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: Apparatus and method for employing a Hardware Processing Function in a processor system using a hierarchical memory. Embodiments of the disclosed invention may be used to enhance processor performance and functionality while maintaining cache coherency and reducing cache pollution. A system includes a processor, a hierarchical memory system coupled to the processor, and a Hardware Processing Function coupled to the hierarchical memory system. The processor is configured to decode an instruction and the hierarchical memory system is configured to execute the instruction. The instruction directs the memory system to perform a data manipulation. The processor transfers a value to the memory system. The value comprises a location of source data to be manipulated, a selection of a Hardware Processing Function to perform the data manipulation, and a destination storage location where the manipulated data is to be stored.

Abstract: Various embodiments of the present invention provide a system for caching information in a multi-process environment. The system includes a processor. A shared memory is communicatively coupled to the processor. The shared memory includes a set of data. A writer process is communicatively coupled to the shared memory. The write process reads and updates the set of data. A plurality of reader processes is communicatively coupled to the shared memory. Each reader process reads at least part of the set of data directly from the shared memory and sends a set of update information to the writer process. The writer process then updates the set of data stored in the shared memory based on the set of update information.

Abstract: A scalable locking system is described herein that allows processors to access shared data with reduced cache contention to increase parallelism and scalability. The system provides a reader/writer lock implementation that uses randomization and spends extra space to spread possible contention over multiple cache lines. The system avoids updates to a single shared location in acquiring/releasing a read lock by spreading the lock count over multiple sub-counts in multiple cache lines, and hashing thread identifiers to those cache lines. Carefully crafted invariants allow the use of partially lock-free code in the common path of acquisition and release of a read lock. A careful protocol allows the system to reuse space allocated for a read lock for subsequent locking to avoid frequent reallocating of read lock data structures. The system also provides fairness for write-locking threads and uses object pooling techniques to make reduce costs associated with the lock data structures.

Abstract: A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates a wake-and-go storage array with the target address and snooping the target address on the system bus without data exclusivity. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity.

Abstract: A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: In an apparatus for controlling the access operation by a plurality of data processing devices to a memory, each data processing device (10, 11, 12) is assigned a respective address region which indicates the part of the addresses of the memory (13) which the respective data processing device can access. A control device (21) blocks an access operation by a data processing device to the memory (13) if the access operation address is not located in the address region which is assigned to the respective data processing device (10, 11, 12).

Abstract: A number of coherence domains are maintained among the multitude of processing cores disposed in a microprocessor. A cache coherency manager defines the coherency relationships such that coherence traffic flows only among the processing cores that are defined as having a coherency relationship. The data defining the coherency relationships between the processing cores is optionally stored in a programmable register. For each source of a coherent request, the processing core targets of the request are identified in the programmable register. In response to a coherent request, an intervention message is forwarded only to the cores that are defined to be in the same coherence domain as the requesting core. If a cache hit occurs in response to a coherent read request and the coherence state of the cache line resulting in the hit satisfies a condition, the requested data is made available to the requesting core from that cache line.

Abstract: Flash memory stored data modification is described. In embodiments, a flash memory system includes flash memory and a memory controller that manages data write and erase operations to the flash memory. The flash memory includes a first flash memory region of single-write flash memory cells that are each configured for a data write operation and a corresponding erase operation before a subsequent data write operation. The flash memory also includes a second flash memory region of multiple-write flash memory cells that are each configured for multiple data write operations before an erase operation.

Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.

Abstract: This invention provides a request controlling apparatus, processor and method. The request controlling apparatus is connected to a request storage unit and includes: a queue unit storing flag recording region configured to record a storing flag corresponding to a queue unit in the request storage unit, a comparing means configured to judge whether a incoming first queue unit corresponds to a same message as an already existing queue unit, where the already existing queue unit is in the request storage unit and a flag setting means is configured to set the storing flag corresponding to the already existing queue unit in the queue unit storing flag recording region, to indicate that a message state related to the already existing queue unit will not be stored if the first queue unit corresponds to the same message as in the already existing queue unit.

Abstract: A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address and snoops the target address on the system bus.

Abstract: Transparent hypervisor pinning of critical memory areas is provided for a shared memory partition data processing system. The transparent hypervisor pinning includes receiving at a hypervisor a hypervisor call initiated by a logical partition to register a logical memory area of the logical partition with the hypervisor. Responsive to this hypervisor call, the hypervisor transparently determines whether the logical memory is a critical memory area for access by the hypervisor. If the logical memory area is a critical memory area, then the hypervisor automatically pins the logical memory area to physical memory of the shared memory partition data processing system, thereby ensuring that the memory area will not be paged-out from physical memory to external storage, and thus ensuring availability of the logic memory area to the hypervisor.

Abstract: A method, system, and computer program product for implementing Serviceability Level Indicator Processing (SLIPs) for storage alterations in a computer system is provided. A plurality of storage release requests is analyzed to identify an address monitored by a storage alteration slip. Upon identification of the address, the storage alteration slip is disabled and an initialization slip is re-enabled.

Abstract: A multiple computer environment is disclosed in which an application program executes simultaneously on a plurality of computers (M1, M2, . . . Mn) interconnected by a communications network (53) and in which the local memory of each computer is maintained substantially the same by updating in due course. A lock mechanism is provided to permit exclusive access to an asset, object, or structure (ie memory location) by acquisition and release of the lock. In particular, before a new lock can be acquired by any other computer on a memory location previously locked by one computer, any re-written content(s) for the previously locked memory location are transmitted to all the other computers and their corresponding memory locations (before the in due course updating). Thus when the new lock is acquired all the corresponding memory locations of all computers have been updated.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: A system comprises a general-purpose memory, a lockable memory, a memory management unit, and a processor. The general-purpose memory includes data for a first set of addresses. The lockable memory includes data for a second set of addresses. The memory management unit selectively writes data to one of the general-purpose memory and the lockable memory and selectively locks the lockable memory by preventing writes to the lockable memory. The processor instructs the memory management unit to unlock the lockable memory before requesting a write to one of the second set of addresses.

Abstract: A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location.

Abstract: Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test.

Abstract: Concurrent threads in a multithreaded processor share access to a memory, with any location in the shared memory being accessible by any thread. In one embodiment, the shared memory has multiple independently-addressable memory banks, and one location per bank can be accessed in parallel. Parallel processing engines executing the threads generate a group of parallel memory access requests. Address conflict logic determines whether the requests can be satisfied in parallel (e.g., based on bank access constraints) and serializes the requests to the extent needed to avoid conflicts. In some embodiments, data read from one address in the shared memory can be broadcast to multiple processing engines.

Abstract: A transactional memory system, method and apparatus are disclosed. An embodiment of the method includes attempting to acquire a write lock provided by an implementation of a software transactional memory (STM) system for each of a set of memory locations of the STM; if a write lock is acquired for each of the set of memory locations, comparing the value in each of the set of memory locations to a corresponding expected value; and if the comparing yields the same, predetermined result for each of the set of memory locations, storing in each memory location a corresponding new value. Other embodiments are also described and claimed.

Abstract: In traditional transactional locking systems, such as Transactional Locking with Read-Write locks (TLRW), threads may frequently update lock metadata, causing system performance degradation. A system and method for implementing transactional locking using reader-lists (TLRL) may associate a respective reader-list with each stripe of data in a shared memory system. Before reading a given stripe as part of a transaction, a thread may add itself to the stripe's reader-list, if the thread is not already on the reader-list. A thread may leave itself on a reader-list after finishing the transaction. Before a thread modifies a stripe, the modifying thread may acquire a write-lock for the stripe. The writer thread may indicate to each reader thread on the stripe's reader-list that if the reader thread is executing a transaction, the reader thread should abort. The indication may include setting an invalidation flag for the reader. The writer thread may clear the reader-list of a stripe it modified.

Abstract: In an embodiment, a method and computer product is presented for executing a command in a replicated environment comprising a replication appliance and a production site, the method comprising: intercepting the command at a splitter; wherein the command comprises a atomic test and set request.

Abstract: In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed.

Abstract: The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.

Abstract: A method and apparatus are provided for controlling access to logical units, a logical unit being an addressable entity that accept commands. A plurality of logical units are accessible by one or more ports, a port being an addressable entity that sends commands. A communication means which may be a storage area network (SAN) (102, 202) provides access to the plurality of logical units by the one or more ports. One or more ports that require access to the same logical units are grouped in a named set (301, 302, 303) in a first location. The named set (301, 302, 303) is associated (300) in a subsequent location with selected logical units (304) thereby controlling the access to the logical units. Identification information for the ports in a named set is extracted at the subsequent location by referencing the named set. The sets can be physically defined, for example, by switch zoning, or logically defined by logically grouping port names.

Abstract: A portable multifunction computing device optimizes cache storage when processing media files and the like. During a playback operation, the device caches as many media items as possible such that during playback media items are retrieved from cache rather than from a hard disk memory. The device monitors memory requirements of other programs and applications currently in use on the device to insure sufficient cache memory is available for such programs and applications.

Abstract: A method and apparatus for improved algorithm and key agility for a cryptosystem, comprising a CAM-type key manager. The key manager uses two memories, an index RAM and a key RAM, to virtualize each algorithm or key using pointers from the index RAM to the key RAM, allowing simple reference to algorithm/key pairs, and to dynamically allocate storage for keys. An autonomous free memory management design improves latency in future key write operations by transforming the search for free location addresses in the key RAM memory into a background task, and employing a free address stack. The index RAM is resizable so that data for a plurality of cryptographic algorithms may be stored dynamically.