Abstract: A method for managing a plurality of servers is disclosed. Each server of the plurality of servers has access to data stored by other servers. The data is stored to one or more data storage devices. Coordinating information is written for the plurality of servers to a master mailbox record. The coordinating information includes data that each server uses to recover after a failure by a server. The master mailbox record is stored on a selected storage device at a location known to the plurality of servers, and the selected storage device is designated as a lock storage device. A plurality of lock storage devices is chosen so that in the event of failure of a server of the plurality of servers, at least one lock storage device will be available to the remaining servers.

Abstract: A write-protection module for a storage device and the method thereof are disclosed. The write-protection module includes a power supply circuit, a fingerprint sensor, a database, and a microprocessor. The microprocessor for receiving the working power produced by the power supply circuit to maintain operation is respectively coupled to the power supply circuit, the fingerprint sensor, and the database. The fingerprint sensor receives the fingerprint input of a user, and the microprocessor receives the output signal of the fingerprint sensor and converts the output signal into an input cryptograph. Finally, the microprocessor compares the input cryptograph with a predetermined cryptograph stored in the database to produce a comparison information, and determines whether or not the user may access data.

Abstract: A method includes determining that a driver load address is in a system service dispatch table (SSDT) addressable area. The method further includes determining whether the driver is authorized to be in the SSDT addressable area. If the driver is authorized to be in the SSDT addressable area, the driver is loaded in the SSDT addressable area and is able to hook operating system functions. Conversely, if the driver is not authorized to be in the SSDT addressable area, the driver is loaded outside the SSDT addressable area and is not able to hook operating system functions. In this manner, only authorized drivers are allowed to hook operating system functions.

Abstract: An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.

Abstract: Locks are used to protect variables. All variables protected by a lock are allocated on a page associated with a lock. When a thread (called the owner) acquires the lock, a local copy of the memory page containing the variable is created, the original memory page is protected, and all access of the variable in the owner thread is directed to the local copy. Upon releasing the lock, the changes from the local copy are carried over to the memory page and the memory page is unprotected. Any concurrent access of the variable by non-owner threads triggers an exception handler (due to the protection mechanism) and delays such an access until after the owner thread has finished accessing the variable.

Abstract: Systems and methods for monitoring high-speed network traffic via sequentially multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module configured to be coupled to a first server chassis, a first data port disposed on the first switch module and a set of first port data links configured to be coupled to a set of data port data links, each data link configurable to channel at least one of a normal data stream and a monitored data stream.

Abstract: A system and method of providing trusted service transactions includes associating a commitment with a remote service. The commitment includes a trusted list of runtime dependencies to execute a transaction. The method includes monitoring an actual list of runtime dependencies invoked during execution of the transaction using a trusted monitor. Execution is blocked if a deviation of the actual list from the trusted list is detected. Therefore, a completed transaction is allowed only if no deviation is found between the trusted and invoked list of runtime dependencies. A certificate authority in cooperation with software vendors preferably provide a signed commitment. The commitment is delivered by the provider to a user upon request and verified by the requester. The transaction is then executed by the user. Therefore, trust is verified before and during the transaction and privacy of data is guaranteed after completion.

Abstract: A method within a data processing system in which a processor handles conflicts, which occur during performance by an asynchronous memory mover of an asynchronous memory move (AMM) operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation by which the actual data is moved from a source to a destination memory location, independent of the processor. The memory mover sets a flag bit to indicate that the asynchronous memory mover is currently performing an AMM operation at the memory. When the processor receives a memory access operation, the processor checks the value of the flag bit before issuing the new memory access operation, and checks the associated address of the AMM operation to determine possible address conflicts. The processor then evaluates and responds to address conflicts to prevent corruption of data during an AMM operation.

Abstract: A hardware Secure Processing Unit (SPU) is described that can perform both security functions and other information appliance functions using the same set of hardware resources. Because the additional hardware required to support security functions is a relatively small fraction of the overall device hardware, this type of SPU can be competitive with ordinary non-secure CPUs or microcontrollers that perform the same functions. A set of minimal initialization and management hardware and software is added to, e.g., a standard CPU/microcontroller. The additional hardware and/or software creates an SPU environment and performs the functions needed to virtualize the SPU's hardware resources so that they can be shared between security functions and other functions performed by the same CPU.

Abstract: Intelligent prediction of critical sections is implemented using a method comprising updating a critical section estimator based on historical analysis of atomic/store instruction pairs during runtime and performing lock elision when the critical section estimator indicates that the atomic/store instruction pairs define a critical section.

Abstract: Methods and systems for processing more securely. More specifically, embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where processor and/or northbridge modifications implementing these mechanisms effectively reduce APIC attacks and increase the security of proprietary, confidential or otherwise secure data stored in SMRAM.

Abstract: The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.

Abstract: A system and method for providing security for an Internet server. The system comprises: a logical security system for processing login and password data received from a client device during a server session in order to authenticate a user; and a physical security system for processing Internet protocol (IP) address information of the client device in order to authenticate the client device for the duration of the server session.

Abstract: The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.

Abstract: According to one embodiment, an information recording apparatus has a control unit configured to control mutual transfer of information between each of a disc-shaped recording medium, a cache memory, and a non-volatile memory and the outside, control mutual transfer of information between the disc-shaped recording medium, the cache memory, and the non-volatile memory, and control to set a substituting region corresponding to a defect region generated in the disc-shaped recording medium in the non-volatile memory.

Abstract: Solutions to a value recycling problem facilitate implementations of computer programs that may execute as multithreaded computations in multiprocessor computers, as well as implementations of related shared data structures. Some exploitations allow non-blocking, shared data structures to be implemented using standard dynamic allocation mechanisms (such as malloc and free). Some exploitations allow non-blocking, indeed even lock-free or wait-free, implementations of dynamic storage allocation for shared data structures. In some exploitations, our techniques provide a way to manage dynamically allocated memory in a non-blocking manner without depending on garbage collection. While exploitations of solutions to the value recycling problem that we propose include management of dynamic storage allocation wherein values managed and recycled tend to include values that encode pointers, they are not limited thereto.

Abstract: Mapping tables are for stipulating information for primarily identifying computers, information for identifying a group of the computers and a logical unit number permitting access from the host computer inside storage subsystem, in accordance with arbitrary operation method by a user, and for giving them to host computer. The invention uses management table inside the storage subsystem and allocates logical units inside the storage subsystem to a host computer group arbitrarily grouped by a user in accordance with the desired form of operation of the user, can decide access approval/rejection to the logical unit inside the storage subsystem in the group unit and at the same time, can provide the security function capable of setting interface of connection in the group unit under single port of storage subsystem without changing existing processing, limitation and other functions of computer.

Abstract: A lock-based software transactional memory (STM) implementation may determine whether a transaction's write-set is static (e.g., known in advance not to change). If so, and if the read-set is not static, the STM implementation may execute, or attempt to execute, the transaction as a semi-static transaction. A semi-static transaction may involve obtaining, possibly after incrementing, a reference version value against which to subsequently validate that memory locations, such as read-set locations, have not been modified concurrently with the semi-static transaction. The read-set locations may be validated while locks are held for the locations to be written (e.g., the write-set locations). After committing the modifications to the write-set locations and as part of releasing the locks, versioned write-locks associated with the write-set locations may be updated to reflect the previously obtained, or newly incremented, reference version value.

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Abstract: A host device transmits a command from a command transmission unit (101a) along a predetermined command sequence. A storage device (2) receives the command in a command reception unit (202a). An access determination unit (202c) determines the sequence of the command transmitted from the host device (1) and determines that reception of the access to the host device (1) is enabled only when the sequence is identical with a predetermined sequence. Thus, with simple control, it is possible to prevent data destruction by a host device of an old version.

Abstract: A method for storing an information block that includes determining to store a current version of an information block stored in a memory unit. The checking if a current version of the information is already stored in a storage unit. The current version of the information block is sent from the memory unit to the storage unit if the answer is negative. Generating storage unit location information indicative of a location, at the storage unit, of the current version of the information block if the answer is positive.

Abstract: A database management system has a plurality of database servers and data can be transferred between them by partitioning a data area into small areas and altering allocation of the small areas to the database servers. After altering the configuration, there occurs degradation in processing speed that accompanies re-creation of the index. If this problem is solved by using conventional techniques, noticeable degradation in processing speed will occur to a specific query at the time of a steady state operation. Accordingly, an index created for each of the small areas and an index to all of the small areas are allocated to the database server and used in combination.

Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.

Abstract: A protection register array in which the lock status of the protection register is stored outside of the array. An initial verify function is used to read lock status.

Abstract: Some embodiments of the present invention provide a system that manages a performance of a computer system. During operation, a current expert policy in a set of expert policies is executed, wherein the expert policy manages one or more aspects of the performance of the computer system. Next, a set of performance parameters of the computer system is monitored during execution of the current expert policy. Then, a next expert policy in the set of expert policies is dynamically selected to manage the performance of the computer system, wherein the next expert policy is selected based on the monitored set of performance parameters to improve an operational metric of the computer system.

Abstract: A sequentially performed implementation of a compound compare-and-swap (nCAS) operation has been developed. In one implementation, a double compare-and-swap (DCAS) operation does not result in a fault, interrupt, or trap in the situation where memory address A2 is invalid and the contents of memory address A1 are unequal to C1. In some realizations, memory locations addressed by a sequentially performed nCAS or DCAS instruction are reserved (e.g., locked) in a predefined order in accordance with a fixed total order of memory locations. In this way, deadlock between concurrently executed instances of sequentially performed nCAS instructions can be avoided. Other realizations defer responsibility for deadlock avoidance to the programmer.

Abstract: A system for controlling concurrency of access to data in a database system is provided. The system includes receiving a lock request for access to data in the database system, in which the lock request is a request for a page lock or a row lock for a corresponding row or page in the database system containing the data. The method further includes identifying a partition in the database system that contains the row or the page in the database system containing the data; associating the lock request with a partition lock on the partition that contains the row or the page in the database system containing the data; and accessing the data using the partition lock.

Abstract: A mechanism is disclosed for implementing fast locking in a multi-threaded system. This mechanism enables fast locking to be performed even on an operating system platform that does not allow one thread to assign ownership of a lock on a mutex to another thread. In addition, the mechanism performs locking in a manner that ensures priority correctness and is low-memory safe. In one implementation, the priority correctness is achieved by using operating system mutexes to implement locking, and the low-memory safe aspect is achieved by pre-allocating a memory section to each thread. This pre-allocated memory section ensures that a thread will have sufficient memory to obtain a lock, even when a system is in a low-memory state. With this mechanism, it is possible to implement locking in a safe and efficient manner.

Abstract: A first plurality of operating system processes is assigned to a first protection domain, and a second plurality of operating system processes is assigned to a second protection domain. One or more hardware protection mechanisms are used to prevent the first plurality of operating system processes from accessing the memory space of the second plurality of operating system processes, and also to prevent the second plurality of operating system processes from accessing the memory space of the first plurality of operating system processes.

Abstract: In general, this disclosure describes techniques of ensuring cache coherency in a multi-processor computing system. More specifically, a relaxed coherency mechanism is described that provides the appearance of strong coherency and consistency to correctly written software executing on the multi-processor system. The techniques, as described herein, combine software synchronization instructions with certain hardware-implemented instructions to ensure cache coherency.

Abstract: Aspects of the subject matter described herein relate to sharing volume data via shadow copies. In aspects, an active computer creates a shadow copy of a volume. The shadow copy is exposed to one or more passive computers that may read but not write to the volume. A passive computer may obtain data from the shadow copy by determining whether the data has been written to a differential area and, if so, reading it from the differential area. If the data has not been written to the differential area, the passive computer may obtain it by first reading it from the volume, then re-determining whether it has been written to the differential area, and if so, reading the data from the differential area. Otherwise, the data read from the volume corresponds to the data needed for the shadow copy.

Abstract: A data storage apparatus includes a memory, a monitoring unit for monitoring an unauthorized action on data stored in the memory, a first power supply for supplying power to the monitoring unit, and a power storage unit which supplies power to the monitoring unit when supply of the power from the first power supply to the monitoring unit is stopped and which is charged while the power is being supplied from the first power supply to the monitoring unit.

Abstract: An apparatus for providing storage control in a network of storage controllers is disclosed. The apparatus includes an owner storage controller; an I/O performing component, an ownership assignment component, a lock manager and a messaging component. The ownership assignment component assigns ownership of metadata for data to an owner storage controller. The lock manager controls the locking of metadata during I/O. The messaging component passes messages among storage controllers to request metadata state, to grant locks, to request release of locks, and to signal lock release. The I/O is performed on data whose metadata is owned by an owner storage controller, subject to compliance with metadata lock protocols controlled by the owner storage controller, and any copy of the data held from time to time is maintained in a coherency relation with the data.

Abstract: Unobservable memory regions, referred to as stealth memory regions, are allocated or otherwise provided to store data whose secrecy is to be protected. The stealth memory is prevented from exposing information about its usage pattern to an attacker or adversary. In particular, the usage patterns may not be deduced via the side-channels.

Abstract: Embodiments relate to systems and methods for managing stalled storage devices of a storage system. In one embodiment, a method for managing access to storage devices includes determining that a first storage device, which stores a first resource, is stalled and transitioning the first storage device to a stalled state. The method also includes receiving an access request for at least a portion of the first resource while the first storage device is in the stalled state and attempting to provide access to a representation of the portion of the first resource from at least a second storage device that is not in a stalled state. In another embodiment, a method of managing access requests by a thread for a resource stored on a storage device includes initializing a thread access level for an access request by a thread for the resource.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register acess to the first or second processor. The hardware mechanisim includes a hard semaphore and/or soft semaphore.

Abstract: This invention is a system and method for managing data in a secure manner in a data storage environment that is in communication with a network including an internet-based network. The system includes logic for securely managing internet client's access to data volumes stored on a data storage system, and may also include logic operating with a file server for providing dynamic access of data available to such clients in a secure fashion.

Abstract: An apparatus for providing storage control in a network of storage controllers is disclosed. The apparatus includes an owner storage controller; an I/O performing component, an ownership assignment component, a lock manager and a messaging component. The ownership assignment component assigns ownership of metadata for data to an owner storage controller. The lock manager controls the locking of metadata during I/O. The messaging component passes messages among storage controllers to request metadata state, to grant locks, to request release of locks, and to signal lock release. The I/O is performed on data whose metadata is owned by an owner storage controller, subject to compliance with metadata lock protocols controlled by the owner storage controller, and any copy of the data held from time to time is maintained in a coherency relation with the data.

Abstract: A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors, locally determines an amount to delay a later attempt to directly acquire ownership of the access coordinator. Upon a failure of the later and/or a subsequent attempt to directly acquire ownership of the access coordinator the processor would enter into an indirect waiting arrangement for ownership of the access coordinator.

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

Abstract: Representative is a computer-implemented method of detecting a buffer overflow condition. In accordance with the method, a destination address for a computer process' desired right operation is received and a determination is made as to whether the destination address is within an illegitimate writable memory segment within the process' virtual address space (VAS). If so, the process is preferably alerted of the potential buffer overflow condition. A determination may also be made as to whether the destination address is legitimate, in which case the process may be informed of the memory segment which corresponds to the destination address.

Abstract: In general, in one aspect, the disclosure describes a processor that includes multiple multi-threaded programmable units integrated on a single die. The die also includes circuitry communicatively coupled to the programmable units that reorders and grants lock requests received from the threads based on an order in which the threads requested insertion into a sequence of lock grants.

Abstract: In a method for controlling a processor which accesses information of a storage device through cache memory, when reading information stored in a target address or an address range of the storage device, it is monitored whether there is an update access to the address or address range from another processor, and also the processor is entered into a suspense status, which is released using the occurrence of the update access to the storage device from another processor as a trigger.

Abstract: A method, an apparatus, and a system for enabling a processor to access shared data are provided to overcome low efficiency of a storage system. The method includes that the processor sends a storage block locking command to the storage system through a hardware thread, where the command instructs the storage system to lock a storage block; the processor judges whether a storage block locking completion message has been received from the storage system in a preset clock period; and, schedules the hardware thread to access shared data in the storage block if the storage block locking completion message has been received from the storage system in the preset clock period, or schedules the hardware thread to keep waiting for the storage block locking completion message from the storage system if no storage block locking completion message has been received from the storage system in the preset clock period.

Abstract: Protection mechanism is provided for data stored in logical volumes, especially during the time the corresponding host computer is off line. Additionally, integrity check mechanism is provided for logical volume when the host computer is started, so that host computer can detect unauthorized access to its assigned logical volume during off-line period, and execute security check.

Abstract: A method for automatically detecting an attempted invalid access to a memory address in accordance with an exemplary embodiment is provided. The method includes reading a first data set having a software application name and a memory address stored therein utilizing the mainframe computer. The memory address indicates a portion of a memory that is not allowed to be changed. The method further includes detecting when a software application is attempting to access the memory address and setting a first bit in the memory to a first value in response to the detection utilizing the mainframe computer. The method further includes storing a name of the software application, the memory address, and contents of the portion of the memory specified by the memory address, in a second data set, when the first bit has the first value utilizing the mainframe computer. The method further includes displaying an error message on a display device when the first bit has the first value.

Abstract: In one embodiment, a solution is provided wherein a lock manager is kept moving among multiple cores or processors in a multi-core or multi-processor environment. By “hopping” the lock manager from processor to processor, a bottleneck at any of the processors is prevented. The frequency of movement may be based on, for example, a counter that counts the number of input/outputs handled by the lock manager and moves the lock manager to a different processor once a determined threshold is met. In another embodiment of the present invention, the frequency of the movement between processors may be based on a time that counts the amount of time the lock manager has been operating on the processor and moves the lock manager to a different processor once a predetermined time is reached.

Abstract: A data processing system with memory access comprising an operating system for supporting processes, such that the process are associated with one or more resources and the operating system being arranged to police the accessing by processes of resources so as to inhibit a process from accessing resources with which it is not associated. Part of this system is an interface for interfacing between each process and the operating system and a memory for storing state information for at least one process. The interface may be arranged to analyze instructions from the processes to the operating system, and upon detecting an instruction to re-initialize a process cause state information corresponding to that pre-existing state information to be stored in the memory as state information for the re-initialized process and to be associated with the resource.

Abstract: Aspects of the present invention comprise systems and methods for protecting multi-threaded access to shared memory. Some aspects provide higher data concurrency than other methods. Some aspects relate to methods and systems that provide access to data for all threads during the first phases of one thread's write operation. Some aspects provide all threads access to a particular data unit until one thread enters the commit phase of the write operation. Some aspects manage a computing data resource such that, when a thread enters the commit phase, all pending read requests are fulfilled, all pending write requests are allowed to proceed to commit phase at which point they are blocked, all new read and write requests are blocked and the commit phase is completed by updating the target data and releasing the blocked requests. Some aspects provide improved concurrency by performing reduced cross-thread interference. Some aspects may be implemented at any level from hardware to high-level languages.

Abstract: In a memory system using a removable recording medium and data stored in the recording medium, identifying information for identifying each recording medium from others is held in the recording medium, and when data stored in the recording medium is used, the identifying information of the recording medium is required. As a result, when a flash memory card, etc. is used, a copyright is reliably protected.