Shared Memory Partitioning Patents (Class 711/153)
  • Publication number: 20140237196
    Abstract: A charged particle beam writing apparatus includes a buffer memory including a memory region capable of contemporarily storing writing data for data processing regions, wherein writing data including data files is temporarily stored for each of the data processing regions, a dividing unit to divide the memory region of the buffer memory into a first region being large and a second region being small, a specifying unit to specify the memory region such that a data file being large is preferentially stored in the first region and a data file being small is stored at least in the second region, concerning the data files for each of the data processing regions included in the writing data, and a data processing unit to read data files corresponding to each of the data processing regions from the buffer memory, and to perform data processing using the read data files.
    Type: Application
    Filed: February 11, 2014
    Publication date: August 21, 2014
    Applicant: Nuflare Technology, Inc.
    Inventors: Jun Yashima, Yasuo Kato
  • Publication number: 20140237197
    Abstract: A system and a method are disclosed for providing for non-uniform memory access (NUMA) resource assignment and re-evaluation. In one example, the method includes receiving, by a processing device, a request to launch a first process in a system having a plurality of Non-Uniform Memory Access (NUMA) nodes, determining, by the processing device, a resource requirement of the first process, determining, based on resources available on the plurality of NUMA nodes, a preferred NUMA node of the plurality of NUMA nodes to execute the first process, the preferred NUMA node being determined by the processing device without user input, and binding, by the processing device, the first process to the preferred NUMA node.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 21, 2014
    Applicant: RED HAT, INC.
    Inventor: William Samuel Gray
  • Patent number: 8799615
    Abstract: A memory heap is allocated to a contiguous range of memory. One end of the heap is designated as a small object area. The other end of the heap is designated as a large object area. When the two object areas grow, the small object area grows inward within the heap toward the large object area, and the large object area grows inward within the heap toward the small object area.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bhaktavatsal Maram, Vinod Nalla, Bipin Patil
  • Patent number: 8798085
    Abstract: Techniques are described herein that can be used to process inbound network protocol units. In some implementations, the techniques may process inbound DDP segments. In some implementations, a steering tag of an inbound network protocol unit may be used to access a context accessible to a network component. In some implementations, the context may include an array useful to determine whether all segments in a group have been received by the network component. In some implementations, the segments may be stored in a first buffer and transferred to a second buffer after all segments in a group have been received.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventor: Mark W. Wunderlich
  • Patent number: 8799728
    Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
  • Patent number: 8782646
    Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machnies Corporation
    Inventors: Vaijayanthimala K. Anand, Mark R. Funk, Steven R. Kunkel, Mysore S. Srinivas, Randal C. Swanberg, Ronald D. Young
  • Patent number: 8769206
    Abstract: This disclosure describes, generally, methods and systems for implementing transcendent page caching. The method includes establishing a plurality of virtual machines on a physical machine. Each of the plurality of virtual machines includes a private cache, and a portion of each of the private caches is used to create a shared cache maintained by a hypervisor. The method further includes delaying the removal of the at least one of stored memory pages, storing the at least one of stored memory pages in the shared cache, and requesting, by one of the plurality of virtual machines, the at least one of the stored memory pages from the shared cache. Further, the method includes determining that the at least one of the stored memory pages is stored in the shared cache, and transferring the at least one of the stored shared memory pages to the one of the plurality of virtual machines.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: July 1, 2014
    Assignee: Oracle International Corporation
    Inventor: Daniel Magenheimer
  • Patent number: 8769205
    Abstract: This disclosure describes, generally, methods and systems for implementing transcendent page caching. The method includes establishing a plurality of virtual machines on a physical machine. Each of the plurality of virtual machines includes a private cache, and a portion of each of the private caches is used to create a shared cache maintained by a hypervisor. The method further includes delaying the removal of the at least one of stored memory pages, storing the at least one of stored memory pages in the shared cache, and requesting, by one of the plurality of virtual machines, the at least one of the stored memory pages from the shared cache. Further, the method includes determining that the at least one of the stored memory pages is stored in the shared cache, and transferring the at least one of the stored shared memory pages to the one of the plurality of virtual machines.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: July 1, 2014
    Assignee: Oracle International Corporation
    Inventor: Daniel Magenheimer
  • Publication number: 20140181425
    Abstract: According to one embodiment, a method for a plurality of users to write at least one file to a medium in such a manner that the file is divisionally managed in a system environment in which an input/output control is performed on a storage system includes saving, in the medium as metadata, a user identifier (ID) for identifying a user and file attribute information about the file managed by a user associated with the user ID, and writing, as data, the file managed by the user to the medium as indicated by the file attribute information. In other embodiments, a writing program product, a reading program product, and a system are presented that allow a plurality of users to write at least one file to a medium in such a manner that the file is divisionally managed in a system environment.
    Type: Application
    Filed: December 5, 2013
    Publication date: June 26, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ashida, Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Terue Watanabe
  • Publication number: 20140173201
    Abstract: Methods, parallel computers, and computer program products for acquiring remote shared variable directory (SVD) information in a parallel computer are provided. Embodiments include a runtime optimizer determining that a first thread of a first task requires shared resource data stored in a memory partition corresponding to a second thread of a second task. Embodiments also include the runtime optimizer requesting from the second thread, in response to determining that the first thread of the first task requires the shared resource data, SVD information associated with the shared resource data. Embodiments also include the runtime optimizer receiving from the second thread, the SVD information associated with the shared resource data.
    Type: Application
    Filed: February 13, 2013
    Publication date: June 19, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: CHARLES J. ARCHER, JAMES E. CAREY, PHILIP J. SANDERS, BRIAN E. SMITH
  • Patent number: 8737417
    Abstract: A computer-implemented system and method for a lock-less, zero data copy messaging mechanism in a multi-core processor for use on a modem in a telecommunications network are described herein. The method includes, for each of a plurality of processing cores, acquiring a kernel to user-space (K-U) mapped buffer and corresponding buffer descriptor, inserting a data packet into the buffer; and inserting the buffer descriptor into a circular buffer. The method further includes creating a frame descriptor containing the K-U mapped buffer pointer, inserting the frame descriptor onto a frame queue specified by a dynamic PCD rule mapping IP addresses to frame queues, and creating a buffer descriptor from the frame descriptor.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: May 27, 2014
    Assignee: Alcatel Lucent
    Inventors: Mohammad R. Khawer, Lina So
  • Publication number: 20140136800
    Abstract: In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Birkestrand, Peter J. Heyrman, Wade B. Ouren, Edward C. Prosser
  • Publication number: 20140136801
    Abstract: In a computer system that includes multiple nodes and multiple logical partitions, a dynamic partition manager computes current memory affinity and potential memory affinity to help determine whether a reallocation of resources between nodes may improve memory affinity for a logical partition or for the computer system. If so, the reallocation of resources is performed so memory affinity for the logical partition or computer system is improved. Memory affinity is computed relative to the physical layout of the resources according to a hardware domain hierarchy that includes a plurality of primary domains and a plurality of secondary domains.
    Type: Application
    Filed: December 7, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Birkestrand, Peter J. Heyrman, Wade B. Ouren, Edward C. Prosser
  • Patent number: 8725955
    Abstract: A chip having integrated multiple processor cores and a data processing method are disclosed. The processor chip includes an MP core (main processor core), an AP core (application processor core) which performs a processing function designated by a control of the MP core, a first SM controller which sets a path such that the MP core is coupled with a shared memory, and a second SM controller which sets a path such that the AP core is coupled with the shared memory. By virtue of the present invention, the number of chips installed can be minimized, to allow efficient utilization of PCB space and enable a compact size for a portable terminal.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: May 13, 2014
    Assignee: Mtekvision Co., Ltd.
    Inventor: Jong-Sik Jeong
  • Patent number: 8725972
    Abstract: Various method, system, and computer program product embodiments for performing a backup of a source storage volume to a target storage volume are provided. In one exemplary embodiment, a flashcopy of the source storage volume to the target storage volume is initiated. The content of the source storage volume is stored on the target storage volume in a space efficient manner. The space requirement of the stored content on the target storage volume is monitored. The flashcopy is terminated when the space requirement reaches a predetermined level. The stored content on the target storage volume is copied to a backup storage medium. A new flashcopy of the source storage volume is initiated.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gordon D. Hutchison, Cameron J. McAllister, Lucy Raw, Bruce J. Smith
  • Patent number: 8706977
    Abstract: A method for inter-processor communication in a mobile terminal is disclosed. The method of inter-processor communication for a mobile terminal having a first processor, a second processor, and a shared memory includes determining, by the first processor, the size of data to be sent to the second processor, comparing the determined size of the data with the size of one of multiple buffer areas in the shared memory to be used for transmission, rearranging the shared memory according to the data size when the size of the data is greater than the size of the buffer area to be used, and sending the data to the second processor through the rearranged shared memory. It is possible to increase data transfer rates between processors when inter-processor communication is performed through a shared memory in a mobile terminal having multiple processors.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Ki Yong Lee, Jae Kyong Choi
  • Patent number: 8706926
    Abstract: A hard disk controller (HDC) of a hard disk drive (HDD) includes an encoder module, a buffer manager module, N first-in first-out (FIFO) modules, and N read channel modules, where N is an integer greater than 1. The encoder module is configured to encode data received from a host and to generate P units of encoded data, where P is an integer greater than 1. The buffer manager module is configured to store the P units of encoded data in a buffer, retrieve N of the P units from the buffer, and output the N units in parallel. The N FIFO modules are configured to receive the N units in parallel from the buffer manager. The N read channel modules are configured to receive the N units from the N FIFO modules in parallel, respectively, and to output the N units to a magnetic medium of the HDD.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: April 22, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Tony Yoon, Siu-Hung Fred Au
  • Patent number: 8700846
    Abstract: The present invention is directed to a method and software for managing the host-to-volume mappings of a SAN storage system. The host-to-volume mappings of the SAN storage system are represented in mapping configuration components. The active mapping configuration component represents the current host-to-volume mapping for the SAN storage system. Only one mapping configuration component is active at a time. The host-to-volume mappings of a SAN storage system are changed by deactivating the active mapping configuration component and activating an inactive mapping configuration component that represents a different mapping configuration, effecting a repartition, repurpose, disaster recovery, or other business activity. This can be a scheduled task or performed in an on-demand manner. The mapping configuration components are managed and controlled through the management component of the SAN storage system.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: April 15, 2014
    Assignee: Netapp, Inc.
    Inventors: Yanling Qi, Jason Sherman
  • Patent number: 8700862
    Abstract: A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts
  • Publication number: 20140101459
    Abstract: Various embodiments of the present invention are related to integrated circuits for processing data at a microcontroller interface. The microcontroller interfaces to a memory. The method is employed to process input data provided by the microcontroller during a memory write operation, or input data extracted from the memory during a memory read operation, respectively. A write/read control is used to indicate the memory write or read operation, and a logic address is translated to at least one physical address in the memory. The write/read control and the logic address are further employed to determine a data process mode. In various data processing modes, the input data are processed according to at least one of a plurality of data processing methods to result in processed data in different data formats. Data in different formats may be stored in various regions of the memory.
    Type: Application
    Filed: August 28, 2012
    Publication date: April 10, 2014
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Vincent DEBOUT, Frank LHERMET, Yann Yves Rene Lose
  • Patent number: 8695003
    Abstract: Multiple types of executable agents operating within a domain. The domain includes mutable shared state and immutable shared state, with agents internal to the domain only operating on the shared state. Writer agents are defined to be agents that have read access and write access to mutable shared state and read access only to immutable shared state. General reader agents have read access to both mutable shared state and immutable shared state and have no write access. Immutable reader agents have read access to only immutable shared state and have no write access. By appropriate scheduling of the different types of agents, data races may be reduced or eliminated.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: April 8, 2014
    Assignee: Microsoft Corporation
    Inventors: Artur Laksberg, Joshua D. Phillips, Niklas Gustafsson
  • Patent number: 8694640
    Abstract: Communication protocols, systems, and methods that facilitate communication between disaggregated elements, and also to devices adapted to function as such disaggregated elements, particularly across peer-to-peer (masterless) and include one or more unique features such as packet atomicity, blind ACKs, NAT bridging, locking, multicast spanning and mirroring, and authentication.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: April 8, 2014
    Assignee: Rateze Remote Mgmt. L.L.C.
    Inventors: Charles Frank, Thomas Ludwig, Thomas Hanan, William Babbitt
  • Patent number: 8688932
    Abstract: In a virtual computer system controlling a disk volume and a virtual server which is connected to the disk volume, to which the area of the disk volume is allocated as a virtual disk and which executes a process using the allocated virtual disk, the virtual computer system erases information stored in the virtual disk allocated to the virtual server to be deleted correspondingly with the deletion of the virtual server. An administrative server may be provided to select a server system which is low in load from among plural server systems controlling virtual servers as a server system for erasing information stored in the virtual disk allocated to the virtual server to be deleted.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 1, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Eri Kataoka, Yoshifumi Takamoto
  • Patent number: 8688923
    Abstract: Dynamic control of memory affinity is provided for a shared memory logical partition within a shared memory partition data processing system having a plurality of nodes. The memory affinity control approach includes: determining one or more home node assignments for the shared memory logical partition, with each assigned home node being one node of the plurality of nodes of the system; determining a desired physical page level per node for the shared memory logical partition; and allowing the shared memory partition to run and using the home node assignment(s) and its desired physical page level(s) in the dispatching of tasks to physical processors in the nodes and in hypervisor page memory management to dynamically control memory affinity of the shared memory logical partition in the data processing system.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stuart Z. Jacobs, David A. Larson, Wade B. Ouren, Edward C. Prosser, Kenneth C. Vossen
  • Publication number: 20140082301
    Abstract: An example method for storing data includes providing a plurality of physical storage pools, each storage pool including a plurality of storage nodes coupled to a network. The method also includes mapping a partition of a plurality of partitions to a set of physical storage pools, where each physical storage pool of the set of physical storage pools is located in a different availability zone, and the storage nodes within an availability zone are subject to a correlated loss of access to stored data. The method further includes receiving a data management request over the network, the data management request being associated with a data object. The method also includes identifying a first partition of the plurality of partitions corresponding to the received data management request and manipulating the data object in the physical storage pools mapped to the first partition in accordance with the data management request.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 20, 2014
    Applicant: Rackspace US, Inc.
    Inventors: Michael Barton, Will Reese, John A. Dickinson, Jay B. Payne, Charles B. Thier, Gregory Holt
  • Patent number: 8677077
    Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Lisa Cranton Heller, Damian L. Osisek, Peter K. Szwed
  • Patent number: 8677095
    Abstract: An apparatus and method to allocate memory in a storage system. Firmware running the method uses an iterative approach to find the best optimal memory configuration for a particular storage system given a variety of configuration data parameters stored as persistent data in non-volatile flash memory. The configuration data relates to resources in the environment that the storage system is found in, such as the number of virtual ports, targets and initiators supported by a storage system IOC. The configuration data is alterable, to allow flexibility in updating and changing parameters, and is employed at runtime when the storage system powers on, to enable the most flexible resource allocation.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: March 18, 2014
    Assignee: LSI Corporation
    Inventors: Roger T. J Clegg, Brad D. Besmer, Guy Kendall
  • Publication number: 20140075130
    Abstract: The disclosed embodiments provide a system that processes data from a user. During operation, the system obtains, at a cloud computing system, a set of data-sharing preferences for the user. Next, the system creates a set of virtual storage partitions for the user with the cloud computing system based on the data-sharing preferences. Upon receiving data from the user to the cloud computing system, the system associates the data with a virtual storage partition from the set of virtual storage partitions based on the data-sharing preferences and a set of data attributes for the data. Finally, the system manages access to the virtual storage partition by one or more other users based on the data-sharing preferences.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 13, 2014
    Applicant: APPLE INC.
    Inventors: Monika Bansal, Swapnil R. Dave, Devrim Varoglu
  • Patent number: 8665283
    Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: March 4, 2014
    Assignee: Ambarella, Inc.
    Inventor: Melvyn Lim
  • Publication number: 20140059302
    Abstract: A hypervisor as a movement source stores key information, and the key information is registered in a storage using the stored key information through a logical HBA which is used for migration.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 27, 2014
    Applicant: HITACHI, LTD.
    Inventors: Norimitsu HAYAKAWA, Eiichiro OIWA, Yukari HATTA, Hiroshi MIKI, Takuji TERAYA
  • Patent number: 8650387
    Abstract: An IC chip, an information processing apparatus, a software module control method, an information processing system, an information processing method, and a program for ensuring security before booting a software module reliably are provided. A reader/writer and a mobile phone terminal to be accessed by the reader/writer through proximity communication are provided. In the mobile phone terminal, a first software module transmits commands to second and third software modules. The first software module manages states of the second and third software modules. If during boot-up of the third software module, the processing of the second software module is started and completed, then the first software module resumes the boot-up of the third software module.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: February 11, 2014
    Assignee: Sony Corporation
    Inventor: Hirokazu Sugiyama
  • Patent number: 8631212
    Abstract: A memory management unit is configured to receive requests for memory access from a plurality of I/O devices. The memory management unit implements a protection mode wherein the unit prevents memory accesses by the plurality of I/O devices by mapping memory access requests (from the I/O devices) to the same set of memory address translation data. When the memory management unit is not in the protected mode, the unit maps memory access requests from the plurality of I/O devices to different respective sets of memory address translation data. Thus, the memory management unit may protect memory from access by I/O devices using fewer address translation tables than are typically required (e.g., none).
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: January 14, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew G. Kegel, Ronald Perez, Wei Huang
  • Publication number: 20140006726
    Abstract: A storage system includes a first storage apparatus and a second storage apparatus. The first storage apparatus includes a capacity pool that is partitioned into multiple pool pages and includes a storage area of an external logical volume provided by at least one storage apparatus. The second storage apparatus provides first virtual volume which is a virtual logical volume comprising multiple first virtual areas. In a case of receiving a write request from the computer to a virtual area in the first virtual volume to which a page is not allocated, an unallocated pool page of the external logical volume is allocated to the virtual area. An authority to allocate the unallocated pool page of the external logical volume is assigned to the first storage apparatus.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 2, 2014
    Inventors: Akira YAMAMOTO, Noboru MORISHITA, Hideo SAITO, Yoshiaki EGUCHI, Masayuki YAMAMOTO
  • Patent number: 8621168
    Abstract: Systems, methods, computer programs, and devices are disclosed herein for partitioning the namespace of a secure element in contactless smart card devices and for writing application data in the secure element using requests from a software application outside the secure element. The secure element is a component of a contactless smart card incorporated into a contactless smart card device. A control software application resident in the same or a different secure element provides access types and access bits, for each access memory block of the secure element namespace, thereby portioning the namespace into different access types. Further, a software application outside the secure element manages the control software application by passing commands using a secure channel to the secure element, thereby enabling an end-user of the contactless smart card device or a remote computer to control the partitioning and use of software applications within the secure element.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: December 31, 2013
    Assignee: Google Inc.
    Inventors: Rob von Behren, Jonathan Wall, Ismail Cem Paya, Alexej Muehlberg, Hauke Meyn
  • Patent number: 8612684
    Abstract: Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory controller; a buffer; a bidirectional data bus connecting the controller and the buffer; a control interface connecting the controller and the buffer, the buffer being connected to at least two logical memory busses for memory read and write operations, the buffer comprising data storage areas to buffer data between the controller and the logical memory busses, and logic circuits to decode memory interface control commands from the controller; and a data access and control bus connecting the buffer and each of the logical memory busses to control memory read and write operations.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: December 17, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore Carter Briggs, John Michael Wastlick, Gary Belgrave Gostin
  • Patent number: 8607008
    Abstract: A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example a memory store information and instructions for the engines. The shared resource management unit independently caches and invalidates page table entries on a per engine basis.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: December 10, 2013
    Assignee: NVIDIA Corporation
    Inventors: David B. Glasco, Lingfeng Yuan
  • Patent number: 8607004
    Abstract: Example embodiments of the present invention includes systems and methods for implementing a scalable symmetric multiprocessing (shared memory) computer architecture using a network of homogeneous multi-core servers. The level of processor and memory performance achieved is suitable for running applications that currently require cache coherent shared memory mainframes and supercomputers. The architecture combines new operating system extensions with a high-speed network that supports remote direct memory access to achieve an effective global distributed shared memory. A distributed thread model allows a process running in a head node to fork threads in other (worker) nodes that run in the same global address space. Thread synchronization is supported by a distributed mutex implementation. A transactional memory model allows a multi-threaded program to maintain global memory page consistency across the distributed architecture.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: December 10, 2013
    Inventor: Richard S. Anderson
  • Patent number: 8601571
    Abstract: A multi-user computer system and a remote control method for the multi-user computer system includes a remote controller, with an input unit that receives a remote-control password to remotely operate the computer, information on an OS booted when the remote-control password is input, a key input setting the computer in a mode wherein the remote-control password and the OS information are set, and a key input operating the computer, a microprocessor, a wireless transmitter, and a computer, with a wireless receiver, a microprocessor, and a BIOS that automatically loads an OS corresponding to the remote-control password stored in the memory when the received remote-control password stored in the wireless receiver and the remote-control password in the memory are the same.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: December 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-woo Kim
  • Patent number: 8589937
    Abstract: Computer system, method and program for defining first and second virtual machines and a memory shared by the first and second virtual machines. A filesystem cache resides in the shared memory. A lock structure resides in the shared memory to record which virtual machine, if any, currently has an exclusive lock for writing to the cache. The first virtual machine includes a first program function to acquire the exclusive lock when available by manipulation of the lock structure, and a second program function active after the first virtual machine acquires the exclusive lock, to write to the cache. The lock structure is directly accessible by the first program function. The cache is directly accessible by the second program function. The second virtual machine includes a third program function to acquire the exclusive lock when available by manipulation of the lock structure, and a fourth program function active after the second virtual machine acquires the exclusive lock, to write to the cache.
    Type: Grant
    Filed: August 1, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Steven Shultz, Xenia Tkatschow
  • Publication number: 20130304997
    Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.
    Type: Application
    Filed: June 6, 2013
    Publication date: November 14, 2013
    Inventors: John Dodson, Karthick Rajamani, Eric Retter, Kenneth Wright
  • Publication number: 20130297891
    Abstract: The present invention is applicable to the field of computer technologies and provides a binary tree storage method and system. The method includes: dividing a binary tree into a root tree and a plurality of subtrees, where the plurality of subtrees is layered and stored in N levels of storages; partitioning the plurality of subtrees into M types according to a preset rule, so that the plurality of subtrees is partitioned into N×M data blocks; and adjusting storage positions of the N×M data blocks in the storages, so that a storage at each level occupies the same number of storage units. In the present invention, storage spaces for nodes at each level, which are spaces of non-uniform sizes, are normalized into spaces of the same size, thereby increasing a space utilization rate of storages.
    Type: Application
    Filed: April 17, 2013
    Publication date: November 7, 2013
    Inventors: Yi YI, Rongfeng HONG, Jian WANG
  • Patent number: 8578373
    Abstract: Techniques for improving performance of a shared storage environment are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for improving performance of a shared storage environment comprising determining a unit of shared storage utilized by an environment to be migrated, retrieving a storage management memory structure of a source computing platform for the unit of the shared storage, transferring the storage management memory structure to a target computing platform, and building a portion of storage management memory for the target computing platform utilizing the transferred storage management memory structure.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: November 5, 2013
    Assignee: Symantec Corporation
    Inventors: Sasidharan Krishnan, Suhas Girish Urkude
  • Patent number: 8578105
    Abstract: Various technologies and techniques are disclosed for providing type stability techniques to enhance contention management. A reference counting mechanism is provided that enables transactions to safely examine states of other transactions. Contention management is facilitated using the reference counting mechanism. When a conflict is detected between two transactions, owning transaction information is obtained. A reference count of the owning transaction is incremented. The system ensures that the correct transaction was incremented. If the owning transaction is still a conflicting transaction, then a contention management decision is made to determine proper resolution. When the decision is made, the reference count on the owning transaction is decremented by the conflicting transaction. When each transaction completes, the reference counts it holds to itself is decremented. Data structures cannot be deallocated until their reference count is zero.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: November 5, 2013
    Assignee: Microsoft Corporation
    Inventors: David Detlefs, Michael M. Magruder, John Joseph Duffy
  • Patent number: 8572626
    Abstract: The present invention relates generally to computer operating systems, and more specifically, to operating system calls in a symmetric multiprocessing (SMP) environment. Existing SMP strategies either use a single lock or multiple locks to limit access to critical areas of the operating system to one thread at a time. These strategies suffer from a number of performance problems including slow execution, large software and execution overheads and deadlocking problems. The invention applies a single lock strategy to a micro kernel operating system design which delegates functionality to external processes. The micro kernel has a single critical area, the micro kernel itself, which executes very quickly, while the external processes are protected by proper thread management. As a result, a single lock may be used, overcoming the performance problems of the existing strategies.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: October 29, 2013
    Assignee: QNX Software Systems Limited
    Inventor: Peter Van Der Veen
  • Patent number: 8566537
    Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: October 22, 2013
    Assignee: Intel Corporation
    Inventors: Yang Ni, Rajkishore Barik, Ali-Reza Adl-Tabatabai, Tatiana Shpeisman, Jayanth N. Rao, Ben J. Ashbaugh, Tomasz Janczak
  • Patent number: 8560782
    Abstract: In a data processing system having a plurality of resources and plurality of partitions, each partition including one or more resources of the plurality of resources, a method includes receiving an access request to a target resource of the plurality of resources; using a first set of transaction attributes of the access request to determine a partition identifier for the access request in which the partition identifier indicates a partition of the plurality of partitions which includes the target resource; using the partition identifier to determine access permissions for the partition indicated by the partition identifier; and based on the access permissions, determining whether or not the access request is permitted.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: October 15, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bryan D. Marietta, David B. Kramer, Gregory B. Shippen
  • Patent number: 8560801
    Abstract: Various systems and methods for performing tiering-aware data defragmentation. One method can involve receiving tiering information from a storage device that comprises multiple tiers. The information specifies a tiering attribute and tiering attribute value for the tiers. The method involves establishing zones that have zone attribute values corresponding to the received tiering attribute values. The method then involves storing a given block in a particular zone in response to detecting that a block attribute value of the block corresponds to a zone attribute value for the zone.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: October 15, 2013
    Assignee: Symantec Corporation
    Inventors: Niranjan Pendharkar, Ashish Karnik
  • Patent number: 8560787
    Abstract: A flashcopy of a source storage volume to a target storage volume is initiated. The content of the source storage volume is stored on the target storage volume in a space efficient manner. The space requirement of the stored content on the target storage volume is monitored. The flashcopy is terminated when the space requirement reaches a predetermined level. The stored content on the target storage volume is copied to a backup storage medium. A new flashcopy of the source storage volume is initiated.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gordon D. Hutchison, Cameron J. McAllister, Lucy Raw, Bruce J. Smith
  • Patent number: 8560790
    Abstract: A flashcopy of a source storage volume to a target storage volume is initiated. The content of the source storage volume is stored on the target storage volume in a space efficient manner. The space requirement of the stored content on the target storage volume is monitored. The flashcopy is terminated when the space requirement reaches a predetermined level. The stored content on the target storage volume is copied to a backup storage medium. A new flashcopy of the source storage volume is initiated.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gordon D. Hutchison, Cameron J. McAllister, Lucy Raw, Bruce J. Smith
  • Patent number: 8561076
    Abstract: Coordinating media requests from a plurality of sources that share a shared media resource is disclosed. One or more media requests requiring action by the shared media resource is received from one or more of the plurality of sources. Each received media request is placed in a queue of requests requiring action by the shared media resource. Media requests in the queue are serviced based at least in part on their relative importance.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 15, 2013
    Assignee: EMC Corporation
    Inventors: Ravindranath S. Desai, Grant Woodside, William C. Biester