Abstract: An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.

Abstract: A totaling device includes a first specification unit comprising a first storage unit for storing first dividing information and first interpolation value information, a second storage unit for storing second dividing information and second interpolation value dividing information and a third storage unit for storing information of a totaling information storage unit for storing totaling information; a second specification unit for specifying the third storage unit related to the second dividing information which coincides with second total dividing information or the third storage unit related to the second interpolation value dividing information which coincides with the second total dividing information; and a totaling unit for specifying a totaling information storage unit and storing the totaling information of the totaling target information in the totaling information storage unit.

Abstract: A method and system for allocating storage in a data storage system using one or more storage profiles. A set of storage profiles are provided that each has a set of parameters with values defined for the data storage system and for particular client applications. The method includes receiving a selection of one of the storage profiles, such as from an administrative user interface generated by a storage manager running in conjunction with the data storage system. The selected storage profile is then applied to the data storage system to allocate a portion of the data storage system to a storage pool which is defined by the values of the set of parameters in the selected storage profile. The method includes creating a user-defined storage profile by copying parameters from one of the provided storage profiles and allowing a user to modify or accept the parameters.

Abstract: Embodiments of the present invention enable dynamic repartitioning of data storage in response to one or more triggers. In embodiments, a trigger may be a user-initiated action, a system-generated action, and/or an inference based on storage usage parameters. Applications of the present invention are its use in embodiments of a storage management system comprising a file system manager and a volume manager, where the placement of data into a partition (data storage region) may be specified by matching one or more disk region placement data attributes assigned to data with corresponding disk region attributes. In embodiments, dynamic repartitioning comprises adjustment of the location of the boundary between adjacent disk partitions and, if necessary, rebalancing of the data stored within the partitions by identifying mismatched data and relocating it to the partition with which it is associated.

Abstract: A mechanism for the creation of a shared memory aperture between modes in a parent and child partition is described. The shared memory aperture can be created between any memory mode between the guest and any host. For example, a shared memory aperture can be created between the kernel mode on the child partition and the user mode on the parent partition.

Abstract: A data management method for network storage system that said network storage system includes a storage network, a cluster of storage servers that provide data storage services for application servers connecting to the storage network and storage space corresponding to each storage server, setting a core manager in storage server, said core manager centralizing the metadata of all storage servers in a common storage space; separating the metadata from said storage servers to make a storage server become a storage manager and the storage spaces corresponding to each storage server form the common storage space, allocating the storage space of metadata in said common storage space, and managing the corresponding relationship between metadata and said storage manager.

Abstract: The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked.

Abstract: Methods and systems for bandwidth adaptive computing device to computing device communication are described. Bandwidth adaptive communication includes receiving a communication from a first participant, storing the payload data of the communication in a channel memory element associated with the first participant, and transmitting the payload data to a second participant.

Abstract: Methods (100), systems (300) and computer program products are disclosed for uninterrupted execution of an application program (110). The method (100) comprises: receiving a write operation call to a native file system from an application program (110) being executed on an operating system; and dynamically allocating (120, 122) free data blocks to the native file system from at least one other file system in a group of file systems until completion of execution of the application program (110) thereby completing the write operation call. The group of file systems is configured to allow sharing of free data blocks amongst the group of file systems.

Abstract: A method of controlling a shared memory and a user terminal controlling the operation of the shared memory are disclosed. The portable terminal according to an embodiment of the present invention has a memory unit with a storage area partitioned to blocks in a quantity of n and a plurality of processors reading or writing data by accessing a partitioned block. At least one of the partitioned blocks is assigned as a common storage area, accessible by a processor having an access privilege, and the processor having the access privilege performs an operation of maintaining the data stored in the common storage area. With the present invention, the common storage area can be accessed by a plurality of processors, and thus the data transmission time between the processors can be minimized.

Abstract: Automated paging device management is provided for a shared memory partition data processing system. The automated approach includes managing a paging storage pool defined within one or more storage devices for holding logical memory pages external to physical memory managed by a hypervisor of the processing system. The managing includes: responsive to creation of a logical partition within the processing system, automatically defining a logical volume in the paging storage pool for use as a paging device for the new logical partition, the automatically defining occurring absent use of a filesystem, with the resultant paging device being other than a file in a filesystem; and automatically specifying the logical volume as a paging space device for the new logical partition and binding the paging space device to the new logical partition, wherein the logical volume is sized to accommodate a defined maximum memory size of the new logical partition.

Abstract: In one embodiment, a method is provided that may include encrypting, based least in part upon at least one key, one or more respective portions of input data to generate one or more respective portions of output data to be stored in one or more locations in storage. The method of this embodiment also may include generating, based at least in part upon the one or more respective portions of the output data, check data to be stored in the storage, and/or selecting the one or more locations in the storage so as to permit the one or more respective portions of the output data to be distributed among two or more storage devices comprised in the storage. Many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: Described are techniques for configuring resources of a data storage system. A definition for each of one or more tiers is provided. Each of the tiers corresponds to a different class of consumer of data storage system resources and has a different corresponding definition including a set of one or more clauses and a priority of each clause in said set relative to other clauses in said set. Each of the clauses in the set is one of a plurality of predefined types of clauses. One or more data storage consumers are associated with each tier. A first set of data storage system resources is associated with a first of said one or more tiers in accordance with a corresponding first definition for said first tier. The first set is used when processing storage provisioning requests and I/O requests for data storage consumers associated with the first tier.

Abstract: Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test.

Abstract: An ASCII-based processing system is disclosed. A memory is divided into a plurality of logical partitions. Each partition has a range of memory addresses and includes information associated with a particular task. Task information includes contents of task state register and one or more task data registers, with each task data register having an ASCII name. Each task data register is successively labeled with a unique alphabetic character label starting with the character ‘A.’ A dataflow unit within the processing system is configured to manage a mapping between registers with ASCII names and the memory addresses of a particular task. Task instructions can include ASCII characters that indicate a request for resources and indicate the ASCII-character designated names of task data registers on which the task instruction operates. A processing element receiving the task instruction performs the operation indicated by the ASCII operator code on the indicated task data registers.

Abstract: A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

Abstract: A method and device for performing switchover operations in a computer system having at least two execution units are provided, in which switchover units are included which are configured in such a way that they switch over between at least two operating modes, a first operating mode corresponding to a compare mode, and a second operating mode corresponding to a performance mode. An interrupt controller is provided and, furthermore, at least three memory areas are provided, and the access to the memory areas is implemented in such a way that one first memory area is assigned to at least one first execution unit, and one second memory area is assigned to the at least one second execution unit, and at least one third memory area is assignable to the at least two execution units.

Abstract: In an embodiment, a target number of discretionary pages for a first partition is calculated as a function of a number of physical page table faults, a number of sampled page faults, a number of shared physical page pool faults, a number of re-page-ins, and a ratio of pages. If the target number of discretionary pages for the first partition is less than a number of the discretionary pages that are allocated to the first partition, a result page is found that is allocated to the first partition and the result page is deallocated from the first partition. If the target number of discretionary pages for the first partition is greater than the number of the discretionary pages that are allocated to the first partition, a free page is allocated to the first partition.

Abstract: A system and method for allowing a user to have card transactions on-line and/or off-line with a non-rechargeable electronic money card are provided. The card transaction system includes a card issuing unit which allocates a unique card number to each card and sets a card account corresponding to the card number to issue a card; a card adjustment unit which receives transaction details corresponding to the card and adjusts the card account corresponding to the card according to the transaction details; a flag generator with generates a flag; which indicates whether the card can be used, according to the balance of the card account, on the basis of an off-line reference amount set for off-line transactions and an on-line reference amount set for on-line transactions; and a card information transmitter which transmits the flag corresponding to the card.

Abstract: To share a memory pool that includes at least one physical memory in at least one of plural computing nodes of a system, firmware in management infrastructure of the system is used to partition the memory pool into memory spaces allocated to corresponding ones of at least some of the computing nodes. The firmware maps portions of the at least one physical memory to the memory spaces, where at least one of the memory spaces includes a physical memory portion from another one of the computing nodes.

Abstract: Some aspects include reception of a command from one of a chassis management module and a BIOS specifying a data region to be updated and a locking policy, determination of whether the data region is locked, implementation of the locking policy and returning of a session lock handle if it is determined that the data region is not locked, reception, from the one of the chassis management module and the BIOS, of data for updating the data region, the session lock handle, and an offset, determination that the session lock handle is associated with the data region, writing of the data to the data region at the offset, reception of a request for data of the updated data region from the other one of the chassis management module and the BIOS, determination of whether the updated data region is locked, and if it is determined that the updated data region is not locked, providing of the data of the updated data region to the other one of the chassis management module and the BIOS.

Abstract: A system, method, and computer program for caching a plurality of file fragments to improve file transfer performance, comprising the steps of exposing at least one file fragment of a computer file as a primary object to an application; caching said at least one file fragment at a plurality of points in a network system, wherein said at least one file fragment remains unchanged; and managing said at least one non-changing file fragment throughout said network system at a plurality of cache points and appropriate means and computer-readable instructions.

Abstract: An apparatus, system, and method are disclosed for storage space recovery after reaching a read count limit. A read module reads data in a storage division of solid-state storage. A read counter module then increments a read counter corresponding to the storage division. A read counter limit module determines if the read count exceeds a maximum read threshold, and if so, a storage division selection module selects the corresponding storage division for recovery. A data recovery module reads valid data packets from the selected storage division, stores the valid data packets in another storage division of the solid-state storage, and updates a logical index with a new physical address of the valid data.

Abstract: An apparatus, system, and method are disclosed for managing storage space allocation. The apparatus includes a recognizing module, a reserving module, and a managing module. The recognizing module recognizes a trigger event at a client of the data storage system. The reserving module reserves logical units of space for data storage. The management module manages the logical units of space at the client. Such an arrangement provides for distributed management of storage space allocation within a storage area network (SAN). Facilitating client management of the logical units of space in this manner may reduce the number of required metadata transactions between the client and a metadata server and may increase performance of the SAN file system. Reducing metadata transactions effectively lowers network overhead, while increasing data throughput.

Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Abstract: An improved system and method for removing a storage server in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Storage servers may then be removed and column chunks may be redistributed among the remaining storage servers in the column chunk data store.

Abstract: A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.

Abstract: Mechanisms are disclosed for detecting protocols independently of the ports used by streams associated with the protocols or applications that may send out such streams. The detecting may entail using a content filter that is hosted on a networking stack, where the content filter may be composed of a stream buffer and handlers for detecting the protocols. The handlers may be further used to modify streams incoming to a port or streams outgoing from an application. The handlers can modify the streams in a variety of ways, including reading, inserting, replacing, deleting, and completing data in the streams according to some policy criteria, such as those set by parental controls. Individual handlers may be selected from a plurality or set of handlers so that they can be matched up to the appropriate streams.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Abstract: Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each information type.

Abstract: A method for detecting increasing memory consumption of an application program is provided. The method includes monitoring memory consumption at an allocation site and updating an allocation site threshold value each time the memory consumption increases. The method further includes increasing a growth period counter each time the allocation site threshold value increases in a current time period. The method yet also includes comparing the growth period counter to a growth threshold. The method yet further includes, if the growth period counter is greater or equal to the growth threshold, computing an elapse time, which is the time between the current time period and a previous growth period. The method moreover includes comparing the elapse time to a time threshold. The method in addition includes, if the elapse time is less than the time threshold, reporting the allocation site as a potential source of the increasing memory consumption.

Abstract: The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of byte-addressable per-thread entries, each including a per-thread reference counter and a per-thread counter lock. Slotted threads assigned to a given array entry may increment or decrement the per-thread reference counter in that entry in response to referencing or dereferencing the shared object. Unslotted threads may increment or decrement a shared unslotted reference counter. A thread may update the data structure and/or examine it to determine whether the number of references to the shared object is zero or non-zero using a blocking-optimistic or a non-blocking mechanism. A checking thread may acquire ownership of the data structure, obtain an instantaneous snapshot of all counters, and return a value indicating whether the number of references to the shared object is zero or non-zero.

Abstract: A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.

Abstract: A cache-aware Bloom filter system segments a bit vector of a cache-aware Bloom filter into fixed-size blocks. The system hashes an item to be inserted into the cache-aware Bloom filter to identify one of the fixed-size blocks as a selected block for receiving the item and hashes the item k times to generate k hashed values for encoding the item for insertion in the in the selected block. The system sets bits within the selected block with addresses corresponding to the k hashed values such that accessing the item in the cache-aware Bloom filter requires accessing only the selected block to check the k hashed values. The size of the fixed-size block corresponds to a cache-line size of an associated computer architecture on which the cache-aware Bloom filter is installed.

Abstract: A system for managing processor cycles. A set of uncapped partitions are identified that are ready-to-run in response to unused processor cycles being present in a dispatch window. A number of candidate partitions are identified from the identified set of uncapped partitions based on a history of usage where each identified partition used at least 100 percent of its entitlement in a predefined number of previous dispatch windows. Then, a partition is selected from the number of candidate partitions based on a lottery process of the candidate partitions.

Abstract: A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

Abstract: A method of enabling multiple different operating systems to run concurrently on the same computer, which is an Intel or similar Complex Instruction Set Computer architecture, comprising selecting a first operating system to have a relatively high priority (the realtime operating system, such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general purpose operating system, such as Linux); providing a common program (a hardware resource dispatcher similar to a nanokernel) arranged to switch between said operating systems under predetermined conditions; and providing modifications to said first and second operating systems to allow them to be controlled by said common program.

Abstract: The invention provides a system and method for storing a copy of data stored in an information store. In one embodiment, a data agent reads one or more blocks containing the data from the information store. The data agent maps the one or more blocks to provide a mapping of the blocks, and transmits the one or more blocks and mapping to a media agent for a storage device. The media agent stores the one or more blocks in the storage device according to the mapping.

Abstract: An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.

Abstract: Management of virtual memory allocated by a virtual machine control program to a plurality of virtual machines. Each of the virtual machines has an allocation of virtual private memory divided into working memory, cache memory and swap memory. The virtual machine control program determines that it needs additional virtual memory allocation, and in response, makes respective requests to the virtual machines to convert some of their respective working memory and/or cache memory to swap memory. At another time, the virtual machine control program determines that it needs less virtual memory allocation, and in response, makes respective requests to the virtual machines to convert some of their respective swap memory to working memory and/or cache memory.

Abstract: Access control to shared virtual address space within a single logical partition is provided. The access control includes: associating, by a hypervisor of the data processing system, a memory protection key with a portion of a single logical partition's virtual address space being shared by multiple entities, the key preventing access by one of the multiple entities to that portion of the virtual address space, and allowing access by another of the entities to that portion of the virtual address space; and locking by the hypervisor the memory protection key from modification by the one entity, wherein the locking prevents the one entity from modifying the key and thereby gaining access to the portion of the single logical partition's virtual address space with the associated memory protection key. In one embodiment, the one entity is the single logical partition itself, and the another entity is a partition adjunct.

Abstract: Safe and efficient passing of information from a forwarding-plane to a control-plane is provided. The information can be passed from a forwarding-plane process to a control-plane process without having to modify the control-plane process and without requiring the processes to pass information via shared memory. The information is encoded in the forwarding-plane process. The encoded information is passed to the operating system, wherein the operating system interprets the encoded information and reports the information to the control plane process. The present invention can be advantageously utilized in passing multicast events from a forwarding-plane process to a control-plane process. Multicast events can be passed from a forwarding-plane process to a control-plane process without having to modify the control-plane process and without requiring the processes to pass messages via shared memory.

Abstract: The present invention provides a data processing apparatus for processing data by causing a plurality of function blocks to share a single shared memory, the data processing apparatus including: a memory controller configured to cause the plurality of function blocks to write and read data to/and from the shared memory in response to requests from any one of the function blocks; a cache memory; and a companding section configured to compress the data to be written to the cache memory while expanding the data read therefrom.

Abstract: A method for operating a storage system, consisting of performing an allocation of respective partitions of a physical storage resource of the storage system to respective hosts of the storage system. The method also includes changing the allocation while permitting the respective hosts of the storage system to access the physical storage resource.

Abstract: A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.

Abstract: Various technologies and techniques are disclosed for providing type stability techniques to enhance contention management. A reference counting mechanism is provided that enables transactions to safely examine states of other transactions. Contention management is facilitated using the reference counting mechanism. When a conflict is detected between two transactions, owning transaction information is obtained. A reference count of the owning transaction is incremented. The system ensures that the correct transaction was incremented. If the owning transaction is still a conflicting transaction, then a contention management decision is made to determine proper resolution. When the decision is made, the reference count on the owning transaction is decremented by the conflicting transaction. When each transaction completes, the reference counts it holds to itself is decremented. Data structures cannot be deallocated until their reference count is zero.

Abstract: Embodiments of the present invention set forth a technique for optimizing the on-chip data path between a memory controller and a display controller within a graphics processing unit (GPU). A row selection field and a sector mask are included within a memory access command transmitted from the display controller to the memory controller indicating which row of data is being requested from memory. The memory controller responds to the memory access command by returning only the row of data corresponding to the requested row to the display controller over the on-chip data path. Any extraneous data received by the memory controller in the process of accessing the specifically requested row of data is stripped out and not transmitted back to the display controller.

Abstract: In some embodiments, the invention involves speeding boot up of a platform by initializing the video card early on in the boot process. In an embodiment, processor cache memory is to be used as cache as RAM (CAR). Video graphics adapter (VGA) card initialization uses the CAR instead of system RAM to perform initialization. A portion of the firmware code, interrupt vector tables and handlers are mirrored in the CAR, from flash memory to mimic the behavior of system RAM during the video initialization. VGA initialization may occur before system RAM has initialized to enable early visual feedback to a user. Other embodiments are described and claimed.

Abstract: System and method for interpreting ASCII code fetched from a code space of a task partition that is part of memory shared by a host processor and a multitask controller (MTC). The MTC includes a scheduler unit, a data flow unit, an executive unit, and a resource manager unit. The shared memory also includes a system partition containing a code space. The fetched code is monitored for adjacent ASCII alphabetic characters and if at least two are found and the fetched code is terminated by an ASCII space character, the code table in the code space of the system partition is scanned to find a command that matches the fetched code. The byte in the table immediately following the matched fetched code and having a bit set indicating that it is interpreted is obtained and written over the ASCII space character in the code space of the task partition.