Abstract: A memory mapping unit requests allocation of a remote memory to memory mapping units of other processor nodes via a second communication unit, and requests creation of a mapping connection to a memory-mapping managing unit of a first processor node via the second communication unit. The memory-mapping managing unit creates the mapping connection between a processor node and other processor nodes according to a connection creation request from the memory mapping unit, and then transmits a memory mapping instruction for instructing execution of a memory mapping to the memory mapping unit via a first communication unit of the first processor node.

Abstract: A semiconductor device comprises a nonvolatile memory device, a memory device that processes data according to a DRAM protocol, and an ASIC that converts data output from the memory device into a format compatible with a nonvolatile memory device or a hard disk and outputs the converted data to the nonvolatile memory device or the hard disk.

Abstract: A method includes generating a list of shared and private memory regions of a debuggee. A thread is injected into the debuggee for generating the list and communicating with the debugger. Associated shared memory region handles are added to the list. The handles are used to map the shared memory regions of the debuggee to a debugger. New shared memory regions corresponding to the private memory regions of the debuggee are created and mapped to the debugger. Handles for the new shared memory regions are provided to map the new shared memory regions to the debuggee. The debuggee private memory regions are freed. The new shared memory regions are mapped to respective virtual addresses of the debuggee corresponding to the respective freed private memory regions. In this manner, content of debuggee memory regions is directly accessible by the debugger, and computer processing resources are conserved.

Abstract: Plural guest operating systems run on a computer, where a security kernel enforces a policy of isolation among the guest operating systems. An exclusion vector defines a set of pages that cannot be accessed by direct memory access (DMA) devices. The security kernel enforces an isolation policy by causing certain pages to be excluded from direct access. Thus, device drivers in guest operating systems are permitted to control DMA devices directly without virtualization of those devices, while each guest is prevented from using DMA devices to access pages that the guest is not permitted to access under the policy.

Abstract: A method for operating a communication system is provided. The method includes receiving an arrival rate of a plurality of real-time packets, and receiving a real-time packet including a first plurality of identifiers, for transmission on a first link or a second link, where the first link has a first bandwidth. The method also includes processing the real-time packet to select a first selected link from the first link and the second link based on the first plurality of identifiers, the arrival rate of the plurality of real-time packets, and the first bandwidth, and transmitting the real-time packet on the first selected link.

Abstract: Multiple types of executable agents operating within a domain. The domain includes mutable shared state and immutable shared state, with agents internal to the domain only operating on the shared state. Writer agents are defined to be agents that have read access and write access to mutable shared state and read access only to immutable shared state. General reader agents have read access to both mutable shared state and immutable shared state and have no write access. Immutable reader agents have read access to only immutable shared state and have no write access. By appropriate scheduling of the different types of agents, data races may be reduced or eliminated.

Abstract: Provided are a system and article of manufacture for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the processing systems write data used by the processing system to a shared storage device in response to receiving the signal, wherein each processing system writes the data to the shared storage device.

Abstract: A method for repairing a neighborhood of rows in a memory array using a patch table is disclosed. First data to be stored in row N in a memory array of the memory device, second data, if any, stored in row N?1 in the memory array, and third data, if any, stored in row N+1 in the memory array are stored in a temporary storage area of a memory device. The first data is written in row N, and, in response to an error, the first data, the second data, if any, and the third data, if any, are written in respective rows in a repair area in the memory device. The addresses of rows N?1, N, and N+1 are added to a table stored in the memory device to indicate which rows in the repair area should be used instead of rows N?1, N, and N+1.

Abstract: Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.

Abstract: A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N?1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N?1, N, and N+1 to a table stored in the memory device.

Abstract: A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one packet includes an identifier relating to priority of the at least one packet. The network device can also include a buffer memory having at least one buffer configured to store the at least one packet, and a counter configured to modify a counter value therein when the buffer memory is accessed with respect to the at least one data packet, wherein the counter corresponds to the identifier with respect to the at least one packet.

Abstract: The transactional memory system described herein may apply a mix of read validation techniques to validate read operations (e.g., invisible reads and/or semi-visible reads) in different transactions, or to validate different read operations within a single transaction (including reads of the same location). The system may include mechanisms to dynamically determine that a read validation technique should be replaced by a different technique for reads of particular locations or for all subsequent reads, and/or to dynamically adjust the balance between different read validation techniques to manage costs. Some of the read validation techniques may be supported by hardware transactional memory (HTM). The system may delay acquisition of ownership records for reading, and may acquire two or more ownership records back-to-back (e.g., within a single hardware transaction). The user code of a software transaction may be divided into multiple segments, some of which may be executed within a hardware transaction.

Abstract: Example embodiments of the present invention includes systems and methods for implementing a scalable symmetric multiprocessing (shared memory) computer architecture using a network of homogeneous multi-core servers. The level of processor and memory performance achieved is suitable for running applications that currently require cache coherent shared memory mainframes and supercomputers. The architecture combines new operating system extensions with a high-speed network that supports remote direct memory access to achieve an effective global distributed shared memory. A distributed thread model allows a process running in a head node to fork threads in other (worker) nodes that run in the same global address space. Thread synchronization is supported by a distributed mutex implementation. A transactional memory model allows a multi-threaded program to maintain global memory page consistency across the distributed architecture.

Abstract: A thin provisioning storage system is able to present a thin provisioned volume to a computer, such that the computer stores data to the volume as if storage space on disk drives was already allocated for the volume. Upon receiving a write request from the computer, in which the write request is directed to an area of the volume for which storage space on the disk drives has not yet been allocated, the storage system allocates new space on the disk drives. When allocating the new space, the storage system obtains a designated performance level for the volume, and determines a number of storage extents to be allocated to the volume based upon the determined performance level. The storage system also is able to take into account performance metrics for the disk drives and/or array groups when selecting locations from which to allocate the storage extents.

Abstract: A write-protection module for a storage device and the method thereof are disclosed. The write-protection module includes a power supply circuit, a fingerprint sensor, a database, and a microprocessor. The microprocessor for receiving the working power produced by the power supply circuit to maintain operation is respectively coupled to the power supply circuit, the fingerprint sensor, and the database. The fingerprint sensor receives the fingerprint input of a user, and the microprocessor receives the output signal of the fingerprint sensor and converts the output signal into an input cryptograph. Finally, the microprocessor compares the input cryptograph with a predetermined cryptograph stored in the database to produce a comparison information, and determines whether or not the user may access data.

Abstract: A method includes determining that a driver load address is in a system service dispatch table (SSDT) addressable area. The method further includes determining whether the driver is authorized to be in the SSDT addressable area. If the driver is authorized to be in the SSDT addressable area, the driver is loaded in the SSDT addressable area and is able to hook operating system functions. Conversely, if the driver is not authorized to be in the SSDT addressable area, the driver is loaded outside the SSDT addressable area and is not able to hook operating system functions. In this manner, only authorized drivers are allowed to hook operating system functions.

Abstract: In a virtual computer system controlling a disk volume and a virtual server which is connected to the disk volume, to which the area of the disk volume is allocated as a virtual disk and which executes a process using the allocated virtual disk, the virtual computer system erases information stored in the virtual disk allocated to the virtual server to be deleted correspondingly with the deletion of the virtual server. According to another embodiment of the present invention, an administrative server is provided to select a server system which is low in load from among plural server systems controlling virtual servers as a server system for erasing information stored in the virtual disk allocated to the virtual server to be deleted.

Abstract: A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time.

Abstract: Techniques for optimizing configuration partitioning are disclosed. In one particular exemplary embodiment, the techniques may be realized as a system for configuration partitioning comprising a module for providing one or more policy managers, a module for providing one or more applications, the one or more applications assigned to one or more application groups, a module for associating related application groups with one or more blocks, and a module for assigning each of the one or more blocks to one of the one or more policy managers, wherein if one or more of the one or more blocks cannot be assigned to a policy manager, breaking the one or more blocks into the one or more application groups and assigning the one or more application groups to one of the one or more policy managers.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller. The memory is organized into a set of logical partitions. Task partitions describe a task and include task state information, task data registers and ASCII task instructions. The task state information includes a set of index registers that are accessible by the task instructions. The index registers typically have dedicated locations in the task partition and are referred to by lower case ASCII alphabetic characters. Index registers are used to refer to a task partition in some cases or to a location in the current task partition in other cases for purposes of branching. Index registers can be incremented or decremented and loaded with an immediate data value. In one embodiment, the data flow unit is used to interpret the branch code and fetch contents of a named index register used in the branch.

Abstract: A system and method for providing security for an Internet server. The system comprises: a logical security system for processing login and password data received from a client device during a server session in order to authenticate a user; and a physical security system for processing Internet protocol (IP) address information of the client device in order to authenticate the client device for the duration of the server session.

Abstract: In a data processing system having a plurality of resources and plurality of partitions, each partition including one or more resources of the plurality of resources, a method includes receiving an access request to a target resource of the plurality of resources; using a first set of transaction attributes of the access request to determine a partition identifier for the access request in which the partition identifier indicates a partition of the plurality of partitions which includes the target resource; using the partition identifier to determine access permissions for the partition indicated by the partition identifier; and based on the access permissions, determining whether or not the access request is permitted.

Abstract: A method for writing a logical block into a storage pool includes receiving a request to write the logical block, selecting a block allocation policy, by a file system associated with the storage pool, from a set of allocation policies, obtaining a list of free physical blocks in the storage pool, allocating a physical block from the list of free physical blocks, based on the block allocation policy, and writing the logical block to the physical block.

Abstract: A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of nodal memory is associated with each processor in the node. A processor may request additional memory, and the other processor(s) may grant or veto the request. If granted, the requested memory is added to the subdivision of the requesting processor. A processor can only access memory within its own subdivision. Preferably, each subdivision contains a daemon which monitors memory usage and generates requests for additional memory.

Abstract: Some embodiments of the present invention provide a system that manages a performance of a computer system. During operation, a current expert policy in a set of expert policies is executed, wherein the expert policy manages one or more aspects of the performance of the computer system. Next, a set of performance parameters of the computer system is monitored during execution of the current expert policy. Then, a next expert policy in the set of expert policies is dynamically selected to manage the performance of the computer system, wherein the next expert policy is selected based on the monitored set of performance parameters to improve an operational metric of the computer system.

Abstract: An apparatus and method are disclosed. The apparatus allows dynamic setting of access permissions to contents of a shared memory in a memory device controlled by an embedded controller and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory. Access, via an arbitration device, to separate parts of the shared memory is permitted by using an access control unit that enables/disables access to predetermined portions of the shared memory.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: A symmetric multiprocessing fault-tolerant computer system controls memory access in a symmetric multiprocessing computer system. To do so, virtual page structures are created, where the virtual page structures reflect physical page access privileges to shared memory for processors in a symmetric multiprocessing computer system. Access to shared memory is controlled based on physical page access privileges reflected in the virtual paging structures to coordinate deterministic shared memory access between processors in the symmetric multiprocessing computer system. A symmetric multiprocessing fault-tolerant computer system may use duplication or continuous replay.

Abstract: Electronic circuit chips which include cryptography functions are arranged in multichip configurations through the utilization of a shared external memory. Security of the chips is preserved via a handshaking protocol which permits each chip to access limited portions of the memory as defined in a way that preserves the same high security level as the tamper proof chips themselves. The chips may be operated to work on different tasks or to work on the same task thus providing a mechanism for trading off speed versus redundancy where desired.

Abstract: Systems and methods for addressing memory where data is interleaved across different banks using different interleaving granularities improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected to modify the number of sequential addresses mapped to each DRAM and change the interleaving granularity. A memory addressing scheme is used to allow different partition strides for each virtual memory page without causing memory aliasing problems in which physical memory locations in one virtual memory page are also mapped to another virtual memory page. When a physical memory address lies within a virtual memory page crossing region, the smallest partition stride is used to access the physical memory.

Abstract: A storage system stores multiple copies of data on physical storage implemented, for example, with multiple disk units. Input/output read requests are received from host systems and distributed in a manner that allows parallel read operations to be conducted over the multiple disk units of the physical storage.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The computing system operates on ASCII instructions which includes a set of ASCII operators. The operators include both ASCII data operators and ASCII system operators. The system operators include characters for specifying a request to obtain resources, to perform a task switch, to perform a task suspension, to execute a branch, to transfer results of an operation into a task data register, to transfer data into a processing element, to record the current location of instruction execution in the task code space, to treat a sequence of symbols as a group, and to perform an output function. Data operators include characters for specifying a request to perform arithmetic and logical operations on data.

Abstract: An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure.

Abstract: An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure.

Abstract: A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a “load intensive” device or as a “store intensive” device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the “outbound” and “inbound” buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either “load intensive” or “store intensive” mode. The invention is applicable for use with all types of communications network switches (i.e. “Bridges”, “Hubs”, “Routers” etc.).

Abstract: A method for dynamically managing memory to support one or more processes executing in a remote direct memory access (RDMA) environment is provided. The method includes inserting a descriptor in a shared descriptor table, the descriptor corresponding to a block of memory allocated to a heap by an operating system. The method further includes, in response to allocating a portion of the block of memory from the heap to a process, determining whether the process has an existing registration with an application program interface for the block of memory. If the process has no existing registration, registering the process the process is registered with the application program interface and a registration corresponding to the block of memory is stored in a private registration table of the process.

Abstract: The present invention is directed to a system and method for dynamically, segregating storage resources, pooling such resources into groups, assigning and associating security attributes with those groups. The present invention is further directed to protecting storage media within a shared mass storage device in a network computing environment by utilizing the security attributes. The system of the present invention incorporates a client/server and networked storage device infrastructure that allows dynamic and automatic support of access to storage devices from a plurality of client/server systems on a network.

Abstract: A solution for emulating a hardware device is provided. In particular, a communication device that includes a standard mode of operation and a mapping mode of operation is used together with a control program to emulate communication with the hardware device. The mapping mode of operation is used to implement communication functionality that requires hardware, while the control program emulates other communication functionality previously provided by the hardware device. As a result, a protocol, such as a channel protocol, that requires hardware functionality can be successfully emulated using both the control program and the communication device.

Abstract: Computer system, method and program for defining first and second virtual machines and a memory shared by the first and second virtual machines. A filesystem cache resides in the shared memory. A lock structure resides in the shared memory to record which virtual machine, if any, currently has an exclusive lock for writing to the cache. The first virtual machine includes a first program function to acquire the exclusive lock when available by manipulation of the lock structure, and a second program function active after the first virtual machine acquires the exclusive lock, to write to the cache. The lock structure is directly accessible by the first program function. The cache is directly accessible by the second program function. The second virtual machine includes a third program function to acquire the exclusive lock when available by manipulation of the lock structure, and a fourth program function active after the second virtual machine acquires the exclusive lock, to write to the cache.

Abstract: A logically-partitioned computer system provides support for multiple logical partitions to access a single file system, thereby allowing the logical partitions to share a file without the overhead of communicating over a VLAN. An area of shared memory is defined that multiple logical partitions may access. One or more file control blocks that control access to the files in the file system are then created in the shared memory. Existing mechanisms for locking a file system between processes may then be used across logical partitions to serialize access to the file system by all processes in all logical partitions that share the file system. In this manner the sharing of files in a file system is enabled by leveraging existing technology that is used within a single logical partition to extend across multiple logical partitions.

Abstract: A computing system contains and uses a partitioning microkernel (PMK) or equivalent means for imposing memory partitioning and isolation prior to exposing data to a target operating system or process, and conducts continuing memory management whereby data is validated by security checks before or between sequential processing steps. The PMK may be used in conjunction with an Object Request Broker.

Abstract: A communication link protocol is provided for communicating between nodes of an interconnect system via a communication link. In one embodiment, the communication link protocol includes a direct memory access (DMA) command for writing a block of data from a local node to a remote node via the communication link; an administrative write command for writing data from a local node to registers in a remote node via the communication link for administrative purposes; a memory copy write command for writing a line of memory from a local node to a remote node via the communication link when any data is written into that line of memory; and a built in self test (BIST) command for testing the functionality of the communication link.

Abstract: A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

Abstract: Provided is a storage system having a storage device including memory drives formed of the non-volatile memory, a group is constituted by the memory drives whose number is larger than the number of memory drives necessary to provide the memory capacity, the divided storage areas are managed in each of segments that includes at least one of the divided storage areas, the data storage area or the temporary storage area is allocated to the divided storage areas, upon receiving a data write request, the data storage area in which the write data is written and the segment are specified, the updated data is written in the temporary storage area included in the specified segment, the temporary storage area in which the data is written is set as a new data storage area, and data stored in the data storage area is erased and set as a new temporary storage area.

Abstract: A system and method for address space layout randomization (“ASLR”) for a Windows operating system is disclosed. The address space layout includes one or more memory regions that are identified and then a particular implementation of the system randomizes the identified memory region in order to prevent any software vulnerabilities.

Abstract: Computer system, method and program for defining first and second virtual machines and a memory shared by the first and second virtual machines. A filesystem cache resides in the shared memory. A lock structure resides in the shared memory to record which virtual machine, if any, currently has an exclusive lock for writing to the cache. The first virtual machine includes a first program function to acquire the exclusive lock when available by manipulation of the lock structure, and a second program function active after the first virtual machine acquires the exclusive lock, to write to the cache. The lock structure is directly accessible by the first program function. The cache is directly accessible by the second program function. The second virtual machine includes a third program function to acquire the exclusive lock when available by manipulation of the lock structure, and a fourth program function active after the second virtual machine acquires the exclusive lock, to write to the cache.

Abstract: A bridge capable of preventing data inconsistency is provided, in which a first master device outputs a flush request, a buffering unit buffers data or instructions, and a flush request control circuit records a buffer write pointer of the buffer according to the flush request and outputs a flush acknowledgement signal to the first master device in response of that a buffer read pointer of the buffering unit is identical to the recorded buffer write pointer.

Abstract: In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Abstract: Remote configuration and utilization of a virtual tape management system with creation and management options. At least one security administrator CPU is communicably attached to a virtual tape management CPU. A pair of disk drives is communicably attached to the virtual tape management CPU and to the security administrator. First software within the virtual tape management CPU validates authorized remote access to said disk drives and encrypts the data. Second software facilitates remote configuration and utilization of the virtual tape management CPU. Third software provides tape image file processing including inspecting each remote data storage to determine if a file is present, opening the file, reading tape related information thereon, and reading from or writing to the disk arrays. Fourth software provides checker support for tape image files for enumerating tape image files on the disk drives, opening the tape image files, and reading the tape related information.

Abstract: Apparatus, systems, methods, and articles may operate to store one or more parameters associated with a pseudo-device in a device configuration table associated with a first partition within a multi-partition computing platform. An inter-partition bridge (IPB) may be exposed to an operating system executing within the first partition. The IPB may be adapted to couple the first partition to a second partition sequestered from the first partition. The IPB may be configured by the parameter(s) associated with the pseudo-device. Other embodiments may be described and claimed.