Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.

Abstract: Reducing remote reads of memory in a hybrid computing environment by maintaining remote memory values locally, the hybrid computing environment including a host computer and a plurality of accelerators, the host computer and the accelerators each having local memory shared remotely with the other, including writing to the shared memory of the host computer packets of data representing changes in accelerator memory values, incrementing, in local memory and in remote shared memory on the host computer, a counter value representing the total number of packets written to the host computer, reading by the host computer from the shared memory in the host computer the written data packets, moving the read data to application memory, and incrementing, in both local memory and in remote shared memory on the accelerator, a counter value representing the total number of packets read by the host computer.

Abstract: The invention relates to a cache memory and method for controlling access to data. According to the invention, a control area which is advantageously formed separate from a data area is provided for controlling the access to data stored in the cache and to be read by applicative processes. The control area includes at least one release area with offsets and data version definition sections. Application to shared memories for client server architectures.

Abstract: A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed.

Abstract: Since only one golden image (GI) of a snapshot can exist and is shared among a plurality of storage apparatuses, there was a problem that migration or copy thereof deteriorates the capacity efficiency and increases the cost for managing consistency. The present invention solves the above-mentioned problem by either (1) a direct sharing method of generating a parent-child relationship of snapshots among different storage apparatuses at the time of creating differential LUs from the GI or (2) a virtual sharing method of creating virtual LUs of the GI in the respective storage apparatuses and creating differential LUs of the snapshots from the created virtual LUs, using a storage virtualization function among a plurality of storage apparatuses.

Abstract: Methods and systems for direct device access are disclosed. Aspects of one method may include a plurality of GOSs directly accessing a first network interface device, where the first network interface device may provide access to a network. One or more of the GOSs may be migrated to directly access a second network interface device, based on state information for each of the GOSs, where the state information may be maintained by the host. The GOSs may communicate data to a device coupled to the network by direct accessing the first and/or second network interface device. Similarly, the first and/or second network interface device may communicate data received from a device coupled to the network to one or more of the plurality of GOSs via direct access of the first and/or second network interface device.

Abstract: For the transmission of a telegram from the control device to the peripheral element an intermediate device receives the telegram from the control device and forwards it without amendment to the peripheral element. For the transmission of a telegram from the peripheral element to the control device the intermediate device receives the telegram from the peripheral element and forwards it without amendment to the control device. The telegrams are safety telegrams, so that telegrams forwarded to the control device or to the peripheral element from the respective receiving unit can be checked for freedom from errors.

Abstract: A method for maintaining data coherency in a shared-memory computer system having a plurality of nodes divides the local memory of a given node into one or more blocks and stores a data record for each block indicating a plurality of node groups and a selection of the node groups. Each selected node group represents a number of nodes, and selected node groups represent at least one node that has requested access to the block. In response to receiving an access request from a requesting node that may or may not be in a selected node group, the method and system update the data record to indicate the correct selection. If the requesting node is not in any node group, the data record is adjusted to have new node groups, one of which represents the requesting node.

Abstract: For betterment, by putting a virtual storage device into a suspend mode, physical resources are turned OFF on a virtual storage device basis. Moreover, control information and volume data of the virtual storage device are stored in any external volume, for example, and the resources that have been used by the virtual storage device are deallocated. At the time of resumption of operation, using any resources not in use, the virtual storage device is restored based on the control information in storage. When a change is made to a WWN on the side of a host, the storage device receives a WWN change notification from a management server, and makes settings again to a WWN table, thereby making it accessible from the host.

Abstract: A technique for providing network access in accordance with at least one layered network access technology comprising layer 1 processes and layer 2 processes is described. In a device implementation, the technique comprises a shared memory adapted to store at least layer 1 data and layer 2 data as well as a memory access component coupled to the shared memory and comprising a first client port adapted to receive memory access requests from a layer 1 processing client and a second client port adapted to receive memory access requests from a layer 2 processing client. The memory access component is configured to serve a memory access request from the layer 1 processing client with a lower priority than a memory access request from the layer 2 processing client. In particular, the memory access component may be adapted to prioritize reading of layer 1 data by the layer 2 processing client over writing of layer 2 data by the layer 1 processing client.

Abstract: A method is provided for sending and receiving data between a first processor including a first cache memory and a second processor including a second cache memory via a shared memory. The method includes classifying, by the first processor, a transfer data area that stores data transferred between the first and second processors in the shared memory as a first area filling one cache line and a second area not filling one cache line, copying, by the first processor, data in the second area into a divided data area in the shared memory, the divided data area being aligned with a cache line in the first cache memory, and processing, by the second processor, the data in the first area and the data in the divided data area as data from the first processor.

Abstract: In an embodiment, a target number of discretionary pages is calculated for a first partition. If the target number of discretionary pages for the first partition is less than a number of the discretionary pages that are allocated to the first partition, a result page is found that is allocated to the first partition and the result page is deallocated from the first partition. If the target number of discretionary pages for the first partition is greater than the number of the discretionary pages that are allocated to the first partition, a free page is allocated to the first partition.

Abstract: Data communications through a host Fibre Channel adapter (‘HFCA’) implemented with a computer that includes two or more logical partitions, each logical partition including a separate instance of an operating system, each instance of an operating system including an instance of a low-level, switched fabric input/output (‘I/O’) library, including establishing, in the HFCA by instances of the I/O library in two or more logical partitions and by the hypervisor, separate logical Fibre Channel adapters (‘LFCAs’) for at least two of the logical partitions, each LFCA including an association of an LFCA identifier with at least one range of I/O memory addresses in the address space of a logical partition and transferring, at the behest of application programs in the two or more logical partitions, data between the RAM of the logical partitions and the data storage devices through the LFCAs, the HFCA, and the Fibre Channel fabric.

Abstract: A storage integrity system in a dispersed storage network scans an address range of data slices to identify errors in one of a plurality of encoded data slices, wherein the plurality of encoded data slices are generated from a data segment using an error encoding dispersal function. When the storage integrity system detects an error, it identifies one of the encoded data slices for rebuilding. The identified data slice is rebuilt in response to the type of error. For example, when the type of the error includes a temporary error, the storage integrity system waits a predetermined time period to determine whether the error still exists prior to rebuilding the identified data slice.

Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.

Abstract: Methods, systems, and apparatus, including computer program products, featuring generating a plurality of error-correcting code chunks from a plurality of data chunks. The error-correcting code chunks can be used to reconstruct one or more of the data chunks. The data chunks are allocated to a local group of storage nodes. The error correcting code chunks are allocated between the local group of storage nodes and one or more remote groups of storage nodes. Each remote group of storage nodes is allocated one or more unique error-correcting code chunks from the error-correcting code chunks. Any of the error-correcting code chunks not allocated to a remote group of storage nodes are allocated to the local group of storage nodes.

Abstract: A method for operating a communication system is provided. The method includes receiving an arrival rate of a plurality of real-time packets, and receiving a real-time packet including a first plurality of identifiers, for transmission on a first link or a second link, where the first link has a first bandwidth. The method also includes processing the real-time packet to select a first selected link from the first link and the second link based on the first plurality of identifiers, the arrival rate of the plurality of real-time packets, and the first bandwidth, and transmitting the real-time packet on the first selected link.

Abstract: Techniques are disclosed for managing memory within a virtualized system that includes a memory compression cache. Generally, the virtualized system may include a hypervisor configured to use a compression cache to temporarily store memory pages that have been compressed to conserve memory space. A “first-in touch-out” (FITO) list may be used to manage the size of the compression cache by monitoring the compressed memory pages in the compression cache. Each element in the FITO list corresponds to a compressed page in the compression cache. Each element in the FITO list records a time at which the corresponding compressed page was stored in the compression cache (i.e. an age). A size of the compression cache may be adjusted based on the ages of the pages in the compression cache.

Abstract: The data path in a network storage system is streamlined by sharing a memory among multiple functional modules (e.g., N-module and D-module) of a storage server that facilitates symmetric access to data from multiple clients. The shared memory stores data from clients or storage devices to facilitate communication of data between clients and storage devices and/or between functional modules, and reduces redundant copies necessary for data transport. It reduces latency and improves throughput efficiencies by minimizing data copies and using hardware assisted mechanisms such as DMA directly from host bus adapters over an interconnection, e.g. switched PCI-e “network”. This scheme is well suited for a “SAN array” architecture, but also can be applied to NAS protocols or in a unified protocol-agnostic storage system. The storage system can provide a range of configurations ranging from dual module to many modules with redundant switched fabrics for I/O, CPU, memory, and disk connectivity.

Abstract: Method and system for managing storage units are provided. A free space module scans a storage unit data structure and a reference data structure to generate an intermediate data structure that identifies storage units that are not referenced by any storage unit client. A lookup module is initiated and the storage unit clients are notified that all new references to any storage unit should be verified with the lookup module. The free space module then verifies if any of the storage units in the intermediate data structure have been referenced since the intermediate data structure was created. Any referenced storage units are removed from the intermediate data structure and a data structure identifying unreferenced storage units is generated. The data structure is then used to allocate the identified storage units.

Abstract: In a data processing system including multiple logical partitions (LPARs), an application executes on a first logical partition (LPAR) of the multiple LPARs, where the application uses a first operation system stored in a first memory partition of a shared pool memory of the data processing system. A virtualization management component (a) initiates an update process that quiesces operations of the first LPAR, (b) pages in, via a virtual input/output server coupled to a first paging device, a first image of a second operating system from the first paging device to the shared pool memory; (c) changes one or more pointers associated with the application to point to one or more portions of the second operating system, such that the application uses the second operating system, when resumed; and (b) resumes execution the application.

Abstract: A mechanism for the creation of a shared memory aperture between modes in a parent and child partition is described. The shared memory aperture can be created between any memory mode between the guest and any host. For example, a shared memory aperture can be created between the kernel mode on the child partition and the user mode on the parent partition.

Abstract: A method, system, and computer program product provide a shared virtual memory space via a cluster-aware virtual input/output (I/O) server (VIOS). The VIOS receives a paging file request from a first LPAR and thin-provisions a logical unit (LU) within the virtual memory space as a shared paging file of the same storage amount as the minimum required capacity. The VIOS also autonomously maintains a logical redundancy LU (redundant LU) as a real-time copy of the provisioned/allocated LU, where the redundant LU is a dynamic copy of the allocated LU that is autonomously updated responsive to any changes within the allocated LU. Responsive to a second VIOS attempting to read a LU currently utilized by a first VIOS, the read request is autonomously redirected to the logical redundancy LU. The redundant LU can be utilized to facilitate migration of a client LPAR to a different computing electronic complex (CEC).

Abstract: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses of the surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained.

Abstract: A method for managing software modules of at least two operating systems sharing physical resources of a computing environment, but running in different partitions separated by a virtualization boundary comprises accumulating module information in a virtualization subsystem that directs the creation and management of the partitions. The accumulated module information is used across the virtualization boundary to manage the use of the software modules. Also, a method for managing software modules comprises making at least two operating systems aware that they are being hosted in a virtualized computing environment.

Abstract: Management of a data cache having a compressed portion and an uncompressed portion by adaptively and dynamically allocating the relative amount space each portion receives. The relative sizes are defined based on one or more cost metrics and benefit metrics. The metrics are selected based on the performance of an application utilizing the cache. An optimized benefit relative to the cost is defined. Application operations on the cache are sampled and the relative cost and benefit is determined for different ratios of uncompressed to compressed cache sizes. The size of the uncompressed portion relative to the compressed portion is then re-adjusted based on an optimal cost-to-benefit ratio for the application.

Abstract: Described are techniques for automatically provisioning storage for an application. A request to provision object-based storage for the application in a data storage system is received The request identifies the application and is received from a user interface interacting with the data storage system at a specified one of a plurality of user levels, each of said plurality of user levels being associated with a different level of abstraction with respect to first processing performed in implementing the request. The first processing is performed to provision object-based storage for the request. The first processing is determined in accordance with the application and includes a level of automation varying in accordance with the specified user level at which the user interface interacts with the data storage system. The automation includes selecting one or more default options in accordance with best practices of the application.

Abstract: Provided is a method for managing a memory storage region used by a processor. The processor is connected to the memory that stores data accessed while a task is being executed. The memory management method including the steps of: dividing the memory area of the memory into blocks having a plurality of different sizes; selecting a block having a size matching a size of the data accessed while the task is being executed; and storing the data accessed while the task is being executed in the selected block.

Abstract: System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner.

Abstract: A method is provided for protecting a computer system, comprising: attaching a security descriptor to a process running on a processor of the computer system; associating with the security descriptor an isolation indicator that indicates the process runs in an isolation mode; calling a system routine by the isolated process that is also callable by a process that is not running in isolation mode; attempting to write to an object of a disk or a registry by the system routine called by the isolated process; determining whether the system routine is requesting the write on behalf of the isolated process or not; if the write is requested on behalf of the isolated process, then performing the write in a pseudo storage area; and if the write is requested on behalf of the non-isolated process, then performing the write in an actual storage area in which the disk or registry resides.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: Proposed is a secure real-time inter-process data exchange mechanism based on memory mapped files (MMF). A modified FIFO access to the data (“one head, multiple tails”) is provided by pointers residing in a MMF buffer. A process writes to a data area of the buffer using “head” pointer, and data are read by processes using “tail” pointers. Only one shared data block is accessible at any given time, thus achieving secure high-performance real-time data sharing data between processes without using OS-dependent thread-synchronization techniques. The invention is implemented as OS-specific dynamic libraries that form a platform-independent software layer which hides the implementation details from the programmer. Access to the libraries is provided by a simple and easy to use API, via a limited number of high-level functions, with syntax consistent across languages (C, C++, Pascal, MATLAB) and OS platforms (Windows, Linux, MacOSX).

Abstract: A tamper resistant servicing Agent for providing various services (e.g., data delete, firewall protection, data encryption, location tracking, message notification, and updating software) comprises multiple functional modules, including a loader module (CLM) that loads and gains control during POST, independent of the OS, an Adaptive Installer Module (AIM), and a Communications Driver Agent (CDA). Once control is handed to the CLM, it loads the AIM, which in turn locates, validates, decompresses and adapts the CDA for the detected OS environment. The CDA exists in two forms, a mini CDA that determines whether a full or current CDA is located somewhere on the device, and if not, to load the full-function CDA from a network; and a full-function CDA that is responsible for all communications between the device and the monitoring server. The servicing functions can be controlled by a remote server.

Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.

Abstract: An intermediate symbol buffer (ISB) configuration and method is provided such that the ISB memory comprises 15 portions, one for each HSDPA spreading code. Symbols associated with a spreading code are written to the memory portion associated with the same spreading code. When a covariance calculation is performed to obtain a more accurate channel estimate, only the symbols associated with spreading codes determined to be needed for the covariance calculation are written to the ISB by a buffer block and red from the ISB by a correlation core. The symbols associated with spreading codes that are not necessary for a covariance calculation may be masked from being written or read from the ISB. In some embodiments each memory portion is an individual memory block. In other embodiments a plurality of memory blocks may contain a plurality of memory portions, one memory partition designated, at least temporarily, for each spreading code.

Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: Methods (100), systems (300) and computer program products are disclosed for uninterrupted execution of an application program (110). The method (100) comprises: receiving a write operation call to a native file system from an application program (110) being executed on an operating system; and dynamically allocating (120, 122) free data blocks to the native file system from at least one other file system in a group of file systems until completion of execution of the application program (110) thereby completing the write operation call. The group of file systems is configured to allow sharing of free data blocks amongst the group of file systems.

Abstract: An access control system (10) is disclosed for controlling access to data stored on at least one data storage medium (14) of a computing system. The access control system (10) comprises authentication means (25) to authenticate users permitted to access data stored in the at least one data storage medium (14) and database means (29) arranged to store data access profiles. Each data access profile is associated with a user permitted to access data stored in the at least one data storage medium (14), each data access profile includes information indicative of the degree of access permitted by a user to data stored in the at least one data storage medium (14), and each data access profile includes a master data access profile (M) and a current data access profile (C). The current data access profile (C) is modifiable within parameters defined by the master data access profile (M).

Abstract: Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to execute data transfer is controlled appropriately based on the transfer conditions of data transfer. To accomplish this, the apparatus has first and second control circuits, a request for data transfer performed between the first and second control circuits is acquired, the transfer conditions of the acquired data transfer are analyzed and which of the first and second control circuits is to execute the data transfer is selected.

Abstract: A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a data input/output request; file control memories which store translation control data; groups of disk drives; disk control processors; disk interface units which connect the groups of disk drives and the disk control processors; cache memories; and inter-processor communication units. The storage logically partitions these devices to cause the partitioned devices to operate as two or more virtual NASs.

Abstract: For improving the drawback of brightness decay of a display due to aging, a memory can be used to store the usage time of each pixel of the display, then based upon the usage time the brightness decay of each pixel of the display can be compensated and accordingly the value for the compensation can be stored in a volatile memory and a non-volatile memory. However, the usage of the non-volatile memory is limited. Hence, the present invention discloses a new approach for storing the data so as to decrease write-in sequence per unit area for the non-volatile memory rather than increasing its storing capacity proportionally.

Abstract: A database system, which updates data by an application program, includes data storage for storing a master data and a shared memory area. The shared memory area includes: a first area, which loads the master data and to which an application program is allowed only to refer; and a second area, which stores a difference data generated when the application program updates the master data in the first area, and which the application program is allowed to refer to and update. The database system is robust against variation of application programs and environments.

Abstract: Described are techniques for partitioning memory. A plurality of boards is provided. Each of the plurality of boards includes a physical memory portion and a set of one or more processor. The physical memory portion in each of said plurality of boards is partitioned into a plurality of logical partitions including a global memory partition accessible by any processor on any of the plurality of boards and one or more other memory partitions configured for use by one or more processors of said each board. Each of the one or more other memory partitions not being accessible to a processor on a board other than said each board.

Abstract: A data processing system is provided. The data processing system includes a plurality of processors, a cache memory shared by the plurality of processors, in which memory a cache line is divided into a plurality of partial writable regions. The plurality of processors are given exclusive access rights to the partial writable region waits.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Abstract: A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.

Abstract: Methods and systems are provided that may be utilized for spilling in query processing environments.

Abstract: A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

Abstract: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.