Entry Replacement Strategy Patents (Class 711/159)
  • Patent number: 9514838
    Abstract: Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 6, 2016
    Assignee: Micron Technology, Inc.
    Inventor: A. Kent Porterfield
  • Patent number: 9501314
    Abstract: A system and method for reducing the number of aborts caused by a runtime helper being called during the execution of a transaction block. When a runtime helper is called during the execution of a transaction block while a program using hardware transactional memory is running, the runtime helper passes ID information indicating the type of runtime helper to an abort handler. When there is an abort caused by a call to a runtime helper, the abort handler responds by acquiring the ID information of the runtime helper that caused the abort, disables the transaction block with respect to a specific type of runtime helper, executes the non-transactional path corresponding to the transaction block, and re-enables the transaction block when predetermined conditions are satisfied.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jose G. Castanos, Takuya Nakaike, Rei Odaira, Peng Wu
  • Patent number: 9495191
    Abstract: Systems and methods for implementing lazy disk I/O in virtual machine live migration. An example method may comprise: determining, by a first computer system, that contents of a memory page mapped into an address space of a virtual machine undergoing live migration from a second computer system to the first computer system is stored on a network-accessible virtual disk; storing, in a memory data structure, a mapping of an address of the memory page to an identifier of a location of the memory page on the virtual disk; and responsive to detecting an access to the memory page by the virtual machine, storing in a memory mapped into the address space of the virtual machine the memory page retrieved from the location of the memory page on the virtual disk.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: November 15, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 9471507
    Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: October 18, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
  • Patent number: 9448871
    Abstract: An information processing device includes a memory, and a plurality of processors coupled to the memory and including cache memories, and configured to select a processor where a capacity of the cache memory is the smallest among the plurality of processors, the selected processor executes memory dump processing for the memory.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: September 20, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Yasuo Suzuki
  • Patent number: 9449032
    Abstract: Embodiments provide a multi-buffering system in an application layer to support unified read/write access to different data source types of an underlying database layer. In a particular embodiment, the database layer comprises both a multi-dimensional data source (e.g. a cube), and another data source type (e.g. a Data Store Object—DSO). An abstract buffer component of the multi-buffering system is specialized into a delta buffer configured to read/write data of the cube, and into an after image buffer configured to read/write data of the DSO. A storage mechanism component of the multi-buffering system is specialized into a cache store configured to read/write data of the cube, and a calculation scenario store configured to read/write data of the DSO. The after image buffer may support certain aggregation rules during a DSO read/write operation. The calculation scenario store may leverage capabilities of an in memory database during a DSO read/write operation.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: September 20, 2016
    Assignee: SAP SE
    Inventors: Martin Friedt, Hans-Georg Beuter, Helidon Dollani, Michael Wilking, Gregor Dieckmann, Ingo Raasch, Stefan Dipper
  • Patent number: 9424114
    Abstract: Systems and methods are disclosed for processing an input/output (I/O) operation. An example system includes a kernel interface that receives a notification of a page fault. The page fault is responsive to an application attempting to perform an operation on a memory region that is set to a first access mode. When the memory region is set to the first access mode, the application does not have permission to perform the operation on the memory region. The system also includes a handler that responsive to the notification (i) sets the memory region to a second access mode and (ii) spawns a kernel thread to drain data from the memory region. When the memory region is set to the second access mode, the application has permission to perform the operation on the memory region. The system further includes an I/O module that stores the data in the memory region for processing.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: August 23, 2016
    Assignee: Red Hat, Inc.
    Inventor: Neil Horman
  • Patent number: 9418003
    Abstract: In accordance with embodiments, there are provided mechanisms and methods for conditionally performing garbage collection. These mechanisms and methods for conditionally performing garbage collection include identifying a predetermined portion of memory within a system, comparing one or more aspects of the predetermined portion of memory to a threshold, and conditionally performing garbage collection on the predetermined portion of memory, based on the comparison.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: August 16, 2016
    Assignee: salesforce.com, inc.
    Inventors: Charles J. Hunt, Kiran Paul
  • Patent number: 9417977
    Abstract: In one embodiment the present invention includes a system for transaction recovery in a distributed computing environment. The system includes a transaction log server, application servers, and resource servers. The transaction log server stores a shared transaction log. The application servers implement a distributed transaction application and accesses the shared transaction log when performing a transaction using the distributed transaction application. The resource servers store data and that operate with the application servers to access the data according to the transaction. If one of the application servers fails, another application server assumes responsibility for a portion of the shared transaction log that was previously accessed by the failed application server.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 16, 2016
    Assignee: SAP SE
    Inventors: Thomas H. Walter, Ralf Kuersch, Nikolai D. Tankov, Peter H. Peshev
  • Patent number: 9405561
    Abstract: A system and method for implementing memory overlays for portable pointer variables. The method includes providing a program executable by a heterogeneous processing system comprising a plurality of a processors running a plurality of instruction set architectures (ISAs). The method also includes providing a plurality of processor specific functions associated with a function pointer in the program. The method includes executing the program by a first processor. The method includes dereferencing the function pointer by mapping the function pointer to a corresponding processor specific feature based on which processor in the plurality of processors is executing the program.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 2, 2016
    Assignee: NVIDIA Corporation
    Inventor: Olivier Giroux
  • Patent number: 9401212
    Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: July 26, 2016
    Assignee: Apple Inc.
    Inventors: Avraham Poza Meir, Eyal Gurgi, Naftali Sommer, Yoav Kasorla
  • Patent number: 9400605
    Abstract: Various embodiments for managing a virtual tape library cluster are provided. A virtual tape library system is enhanced by representing virtual tape resources in cluster nodes with a unique serial number. A least utilized cluster node is determined. One of the virtual tape resources represented within the least utilized cluster node is selected.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nils Haustein, Thorsten Krause, Ulf Troppens, Daniel James Winarski
  • Patent number: 9396513
    Abstract: Methods and systems may provide for detecting an end of execution of a process on a graphics processor and providing a group page fault descriptor to a page miss handler of an operating system (OS) in response to the end of execution of the process, wherein the group page fault descriptor may indicate to the page miss handler that no further page fault requests will be generated by the graphics processor until one or more outstanding page fault requests are satisfied. Additionally, a response to the group page fault descriptor may be received from the page miss handler. In one example, a process identifier is incorporated into the group page fault descriptor, wherein the process identifier is shared by the group page fault descriptor and the one or more outstanding page fault requests.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventor: Altug Koker
  • Patent number: 9390025
    Abstract: Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: July 12, 2016
    Assignee: Rambus Inc.
    Inventors: Trung Diep, Eric Linstadt
  • Patent number: 9384158
    Abstract: Embodiments include a system for dynamic universal port mode assignment for a general purpose computer system. A host bridge with a mixed mode request router receives requests over a universal peripheral component interconnect express (PCIe) port from PCIe adapters utilizing different operating modes. An aspect includes a general purpose host computer with one or more PCIe universal ports allowing the computer to connect to a wide range of external peripheral devices, such as a local area networks, storage area networks, printers, scanners, graphics controllers, game systems, and so forth. PCIe is a modern universal port protocol for parallel ports that allows peripherals utilizing different operating modes to connect to a standard PCIe parallel port. The mixed mode request router supports converged PCIe adapters, which support multiple functions utilizing different PCIe modes converged onto the same mixed mode adapter.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: July 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Thomas A. Gregg, Eric N. Lais
  • Patent number: 9372880
    Abstract: Provided are techniques for reclamation of empty pages in database tables. In response to receiving a plurality of records for insertion into a database table, the plurality of records are inserted into one or more contiguous pages. In response to at least some of the plurality of records being deleted from the database table, the one or more contiguous pages are reclaimed by: relocating any records from the plurality of records remaining in the one or more contiguous pages and releasing the one or more contiguous pages.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: June 21, 2016
    Assignee: International Business Machines Corporation
    Inventors: Frank-Martin Haas, Nelson Hop Hing, Matthew A. Huras, Catherine S. McArthur, Sean W. McKeough, Keriley K. Romanufa, Torsten W. E. Ziegler
  • Patent number: 9361254
    Abstract: A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the semiconductor interposer. The first memory stack and the second memory stack each include multiple memory chips that are configured as a single stack. The buffer chip is electrically coupled to the first memory stack via a first data bus, electrically coupled to the second memory stack via a second data bus, and electrically coupled to a processor data bus that is configured for transmitting signals between the buffer chip and a processor chip. Such a memory device can have high data capacity and still operate at a high data transfer rate in an energy efficient manner.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: June 7, 2016
    Assignee: NVIDIA Corporation
    Inventor: Alok Gupta
  • Patent number: 9348752
    Abstract: Processes are disclosed for embodiments of a caching system to utilize a snapshot file or other limited size data structure to store a portion of the data stored in a cache. The snapshot file can be stored on persistent or otherwise non-transitory storage so that, even in case of a restart, crash or power loss event, the data stored in the snapshot file persists and can be used by the caching system after starting up. The snapshot file can then be used to restore at least some data into the cache in cases where the cached data in the cache is lost. For example, in cases of a cold-start or restart, the caching system can load data from the snapshot file into the empty cache. This can increase the number of cache hits since the cache is repopulated with useful data at startup.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 24, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Vishal Parakh, Antoun Joubran Kanawati
  • Patent number: 9344273
    Abstract: Provided is a cryptographic device implementing an S-Box of an encryption algorithm using a many-to-one binary function. The cryptographic device includes: arrays of first logic gates including I first logic gates which each receive 2 bits of an input signal; 2N second logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2N bits output from the second logic gates, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers. Because a signal output from each array includes only one active bit, current is always consumed constantly to prevent internal data from leaking out to a hacker.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: May 17, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-Mook Choi, Xingguang Feng
  • Patent number: 9336066
    Abstract: A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
  • Patent number: 9317224
    Abstract: The contributions of a virtual storage unit to the utilization of a data storage system may be quantified. A utilization score may be determined for each virtual storage unit for one or more functional components of the data storage system, for example, a front-end adapter, back-end adapter or interface physical storage unit. A utilization score may be determined for the data storage system as a whole by combining the component utilization scores of the virtual storage unit. Component and/or system utilization scores may be visually presented to a user in a manner that enables the user to assess the relative contributions of the virtual storage units to utilization of the component or overall system, respectively. What-if scenarios may be considered using the utilization scores to determine the consequences of moving one or more virtual storage units from one data storage system to another, and a live migration may result.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 19, 2016
    Assignee: EMC Corporation
    Inventors: Dan Aharoni, Hui Wang, Marik Marshak, Amnon Naamad, John A. Adams
  • Patent number: 9311085
    Abstract: A method and apparatus for handling low power and high performance loads is herein described. Software, such as a compiler, is utilized to identify producer loads, consumer reuse loads, and consumer forwarded loads. Based on the identification by software, hardware is able to direct performance of the load directly to a load value buffer, a store buffer, or a data cache. As a result, accesses to cache are reduced, through direct loading from load and store buffers, without sacrificing load performance.
    Type: Grant
    Filed: December 30, 2007
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventors: Tingting Sha, Chris Wilkerson, Herbert Hum, Alaa R. Alameldeen
  • Patent number: 9298724
    Abstract: A computer-implemented method for preserving deduplication efforts after backup-job failures may include (1) identifying a deduplicated data system that reduces redundant data storage by storing and referencing a plurality of deduplicated data segments and reclaims storage space by deleting unreferenced data segments from the deduplicated data system, (2) identifying a backup job that backs up data to the deduplicated data system, causes the deduplicated data system to store at least one new data segment available to be referenced within the deduplicated data system, and fails after the deduplicated data system stores the new data segment within the deduplicated data system causing the new data segment to be unreferenced within the deduplicated data system, and (3) causing the deduplicated data system to retain the new data segment until the backup job is retried despite the new data segment being unreferenced. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: March 29, 2016
    Assignee: Symantec Corporation
    Inventors: Deepak Patil, Vishal Bajpai
  • Patent number: 9274951
    Abstract: A cache memory controller in a computer system, such as a multicore processing system, provides compression for writes to memory, such as an off-chip memory, and decompression after reads from memory. Application accelerator processors in the system generate application data and requests to read/write the data from/to memory. The cache memory controller uses information relating location parameters of buffers allocated for application data and sets parameters to configure compression and decompression operations. The cache memory controller monitors memory addresses specified in read requests and write requests from/to the first memory. The requested memory address is compared to the location parameters for the allocated buffers to select the set of parameters for the particular application data. Compression or decompression is applied to the application data in accordance with the selected set of parameters. The data size of the data transferred to/from memory is reduced.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 1, 2016
    Assignee: Altera Corporation
    Inventors: Allan M Evans, Curtis M Williams
  • Patent number: 9250991
    Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
  • Patent number: 9207882
    Abstract: A method is provided in one example embodiment and includes instantiating a virtual adapter on a network device connected to a storage array, the virtual adapter capable of communicating with the storage array; determining storage configuration properties for the network device; and provisioning a portion of the storage array to the network device in accordance with the determined storage configuration properties. The method may further comprise associating the network device with a service profile, where the storage configuration properties are specified in the service profile. Still further, the method may comprise configuring the network device in accordance with the associated service profile, where the instantiating is also performed in accordance with the associated service profile.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 8, 2015
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sebastien T. Rosset, Brian Y. Uchino, Sesidhar Baddela
  • Patent number: 9189533
    Abstract: Embodiments described herein may involve enabling applications to cooperate with a system-level sync framework. The sync framework may provide system synchronization of files between user devices and a cloud storage service. Arbitrary applications on a user computing device can communicate with the sync framework to temporarily suspend synchronization of a specified file by the sync framework. The application can register functions with the sync framework that the sync framework can invoke in relation to suspending synchronization, continuing to provide system-level access to the file for arbitrary applications, and resuming synchronization.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: November 17, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Marc Wautier, Daniel Fiordalis, Miko Arnab S. Bose, Scott Hoogerwerf, Oded Shekel, Simon Clarke, Chris Guzak, Balaji Balasubramanyan, Michael Novak
  • Patent number: 9189640
    Abstract: In a computer-implemented method for re-provisioning a server of a data center, and while the server is provisioned to a first virtual network of the data center, the server is provided 1) a pseudo-random data stream, and 2) instructions on how to overwrite substantially all of its data storage volumes using the pseudo-random data stream. Upon completion of the overwrite, the server is powered down, then moved to a second virtual network of the data center, and then caused to initiate a network boot from within the second virtual network. After the network boot of the server, one or more indications of the data stored at a number of addresses of the server's data storage volumes are requested from the server via the second virtual network. It is then determined whether the server is in a compromised state by, remotely from the server, comparing the provided indication(s) to one or more expected indications.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: November 17, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Timothy G. Barry
  • Patent number: 9183130
    Abstract: A data control system comprises a communication interface, a processing system, and a storage system. The communication interface is configured to receive a request to retrieve data from a primary storage volume that includes a secondary storage volume. The storage system is configured to store the primary storage volume that includes the secondary storage volume. The processing system is configured to identify changed segments of a plurality of segments in the primary storage volume and identify allocated segments of the changed segments. The communication interface is further configured to transfer the allocated segments in response to the request.
    Type: Grant
    Filed: April 19, 2014
    Date of Patent: November 10, 2015
    Assignee: Quantum Corporation
    Inventors: Gregory L. Wade, J. Mitchell Haile
  • Patent number: 9176804
    Abstract: Reducing memory dump data size by: (i) receiving a memory dump data including a set of stack(s), including at least a first stack which includes a current stack portion; (ii) removing from the memory dump data a first removed data portion that comes from a portion of the first stack to yield an optimized memory dump data; (iii) determining respective ranking values for a plurality of ranked data portions from the set of stacks; and (iv) selecting a ranked data portion from the current stack portion of the first stack to be a first removed data portion based, at least in part, upon the ranking values.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Franziska Geisert, Jakob C. Lang, Angel Nunez Mencias, Jochen Schweflinghaus
  • Patent number: 9177352
    Abstract: Systems and methods for processing user-interface animations are disclosed. The method may include processing a first frame of a user-interface animation with a first processing core, monitoring a processing time of the first frame of the user-interface animation relative to a first synchronization pulse, and processing, if the elapsed processing time exceeds a threshold, a first portion of the user-interface animation with the first processing core and a second portion of the user-interface animation with a second processing core. Processing of a next frame of the user-interface animation may be initiated with the first processing core while the second processing core is processing the second portion of the user-interface animation.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: November 3, 2015
    Assignee: Qualcomm Innovation Center, Inc.
    Inventors: Premal Shah, Omprakash Dhyade
  • Patent number: 9176805
    Abstract: Reducing memory dump data size by: (i) receiving a memory dump data including a set of stack(s), including at least a first stack which includes a current stack portion; (ii) removing from the memory dump data a first removed data portion that comes from a portion of the first stack to yield an optimized memory dump data; (iii) determining respective ranking values for a plurality of ranked data portions from the set of stacks; and (iv) selecting a ranked data portion from the current stack portion of the first stack to be a first removed data portion based, at least in part, upon the ranking values.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Franziska Geisert, Jakob C. Lang, Angel Nunez Mencias, Jochen Schweflinghaus
  • Patent number: 9146803
    Abstract: In a storage apparatus a control section writes, at the time of updating at least a part of first data stored in a first storage area by at least a part of second data, the second data to a second storage area other than the first storage area. In addition, the control section determines whether or not a write error occurs. When the write error does not occur, the control section combines the first data and the second data.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: September 29, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Yuichi Ogawa
  • Patent number: 9111254
    Abstract: A method includes receiving input at an online electronic data discovery system from a source device via a private network. The input indicates that data related to a legal matter is to be preserved, and identifies a custodian associated with the data. The method includes automatically accessing a directory via the private network and receiving information from the directory indicating a location of the identified custodian. The method includes sending a preservation notice to the identified custodian when the information received from the directory indicates that the custodian is accessible via the private network. The preservation notice indicates that data related to the legal matter is not to be discarded. The method includes sending the preservation notice to another custodian when the information received from the directory indicates that the identified custodian is not accessible.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: August 18, 2015
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Richard Smith, Jill A. Rubio
  • Patent number: 9104567
    Abstract: A memory-leak source in a data structure can be identified by counting insertions into the data structure and deletions from the data structure for locations in the execution path of a computer program. These insertion and deletion values can be used to identify at least one location as a memory-leak source that corresponds to an imbalance between insertions and deletions during the execution of the computer program.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 11, 2015
    Assignee: SAP SE
    Inventor: Martin Moser
  • Patent number: 9092359
    Abstract: A system for accessing memory locations includes translating, by a processor, a virtual address to locate a first page table entry (PTE) in a page table. The first PTE includes a marker and an address of a page of main storage. It is determined whether a marker is set in the first PTE. The system identifies a large page size of a large page associated with the first PTE based on determining that the marker is set in the first PTE. The large page consists of contiguous pages of main storage. An origin address of the large page is determined based on determining that the marker is set in the first PTE. The virtual address is used to index into the large page at the origin address to access main storage.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Bybell, Michael K. Gschwind
  • Patent number: 9087011
    Abstract: In one aspect of the present description, in connection with storing a first deduplicated data object in a primary storage pool, described operations include determining the duration of time that the first data object has resided in the primary storage pool, and comparing the determined duration of time to a predetermined time interval. In addition, described operations include, after the determined duration of time meets or exceeds the predetermined time interval, determining if the first data object has an extent referenced by another data object, and determining whether to move the first data object from the primary storage pool to a secondary storage pool as a function of whether the first data object has an extent referenced by another data object after the determined duration of time meets or exceeds the predetermined time interval. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Anglin, David M. Cannon, Colin S. Dawson, Robert S. Elder
  • Patent number: 9086988
    Abstract: A method for accessing memory locations includes translating, by a processor, a virtual address to locate a first page table entry (PTE) in a page table. The first PTE includes a marker and an address of a page of main storage. It is determined, by the processor, whether a marker is set in the first PTE. A large page size of a large page associated with the first PTE is identified based on determining that the marker is set in the first PTE. The large page is made up of contiguous pages of main storage. An origin address of the large page is determined based on determining that the marker is set in the first PTE. The virtual address is used to index into the large page at the origin address to access main storage.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Bybell, Michael K. Gschwind
  • Patent number: 9081693
    Abstract: A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: July 14, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, William C. Moyer, Andrew C. Russell
  • Patent number: 9081702
    Abstract: Techniques described enable efficient swapping of memory pages to and from a working set of pages for a process through the use of large writes and reads of pages to and from sequentially ordered locations in secondary storage. When writing pages from a working set of a process into secondary storage, the pages may be written into reserved, contiguous locations in a dedicated swap file according to a virtual address order or other order. Such writing into sequentially ordered locations enables reading in of clusters of pages in large, sequential blocks of memory, providing for more efficient read operations to return pages to physical memory.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: July 14, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mehmet Iyigun, Yevgeniy (Eugene) Bak, Landy Wang, Arun U. Kishan
  • Patent number: 9081719
    Abstract: A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: July 14, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, William C. Moyer, Andrew C. Russell
  • Patent number: 9070451
    Abstract: Flash memory stored data modification is described. In embodiments, a flash memory system includes flash memory and a memory controller that manages data write and erase operations to the flash memory. The flash memory includes a first flash memory region of single-write flash memory cells that are each configured for a data write operation and a corresponding erase operation before a subsequent data write operation. The flash memory also includes a second flash memory region of multiple-write flash memory cells that are each configured for multiple data write operations before an erase operation.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: June 30, 2015
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Patent number: 9063732
    Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: June 23, 2015
    Assignee: APPLE INC.
    Inventors: Matthew J. Byom, Vadim Khmelnitsky, Hugo B. Fiennes, Arjun Kapoor
  • Patent number: 9063866
    Abstract: Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The method includes the steps of scanning page table entries of hypervisor-managed page tables continuously over repeating scan periods to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page. The activity level of the memory page may be represented by one or more bits of its page table entry and may be classified as having at least two states ranging from hot to cold.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: June 23, 2015
    Assignee: VMware, Inc.
    Inventors: Kiran Tati, Irfan Ahmad
  • Patent number: 9043565
    Abstract: A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Tanaka, Takeyuki Minamimoto
  • Patent number: 9038044
    Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: May 19, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Massimiliano Mollichelli, Andrea Martinelli, Stefan Schippers
  • Publication number: 20150134922
    Abstract: Methods, systems, and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 14, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Duane M. BALDWIN, Sandeep R. PATIL, Riyazahamad M. SHIRAGUPPI, Prashant SODHIYA
  • Patent number: 9026733
    Abstract: Described are techniques for data processing and caching. In response to a client failing to retrieve contents of a data element from a cache location specified by a first data element identifier including a first content-based identifier, the contents of the data element are obtained and stored at a cache location specified by the first data element identifier. The contents of the data element are updated at a second point in time and stored as second contents in the data element source. The data element at the second point in time has a second content-based identifier. In response to the client failing to retrieve the second contents of the data element from a cache location specified by a second data element identifier including the second content-based identifier, the second contents of the data element are obtained and stored at a cache location specified by the second data element identifier.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Pegasystems Inc.
    Inventors: John Clinton, Timothy Joseph Martel, Bachir Mohamed Berrachedi
  • Publication number: 20150121021
    Abstract: Write commands for a storage device specify write data with either a first data step size or a second data step size. In the former case, the storage device performs a read-modify-write (RMW) cycle which includes reading data with the second data step size. In the latter case, the storage device executes the command in a single write cycle. A command sorting unit sorts received commands into two groups, first commands and second commands, when storing them in a memory. First commands are write commands whose data boundaries do not match with the second data step size. Second commands include write commands whose data boundaries match with the second data step size. A command issuing unit converts first commands into a second command upon predetermined conditions. The command issuing unit issues the second commands to the storage device, in preference to the first commands.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 30, 2015
    Inventors: Masatoshi Nakamura, Koutarou Nimura, Marie Abe, Yoshihito Konta, Hidefumi Kobayashi, Mihoko Tojo, Yasuhiro Ogasawara, Shigeru Akiyama
  • Patent number: 9021185
    Abstract: A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: April 28, 2015
    Inventor: Amir Ban