Entry Replacement Strategy Patents (Class 711/159)
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Patent number: 9111254Abstract: A method includes receiving input at an online electronic data discovery system from a source device via a private network. The input indicates that data related to a legal matter is to be preserved, and identifies a custodian associated with the data. The method includes automatically accessing a directory via the private network and receiving information from the directory indicating a location of the identified custodian. The method includes sending a preservation notice to the identified custodian when the information received from the directory indicates that the custodian is accessible via the private network. The preservation notice indicates that data related to the legal matter is not to be discarded. The method includes sending the preservation notice to another custodian when the information received from the directory indicates that the identified custodian is not accessible.Type: GrantFiled: November 2, 2009Date of Patent: August 18, 2015Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.Inventors: Richard Smith, Jill A. Rubio
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Patent number: 9104567Abstract: A memory-leak source in a data structure can be identified by counting insertions into the data structure and deletions from the data structure for locations in the execution path of a computer program. These insertion and deletion values can be used to identify at least one location as a memory-leak source that corresponds to an imbalance between insertions and deletions during the execution of the computer program.Type: GrantFiled: December 28, 2011Date of Patent: August 11, 2015Assignee: SAP SEInventor: Martin Moser
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Patent number: 9092359Abstract: A system for accessing memory locations includes translating, by a processor, a virtual address to locate a first page table entry (PTE) in a page table. The first PTE includes a marker and an address of a page of main storage. It is determined whether a marker is set in the first PTE. The system identifies a large page size of a large page associated with the first PTE based on determining that the marker is set in the first PTE. The large page consists of contiguous pages of main storage. An origin address of the large page is determined based on determining that the marker is set in the first PTE. The virtual address is used to index into the large page at the origin address to access main storage.Type: GrantFiled: June 14, 2012Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Anthony J. Bybell, Michael K. Gschwind
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Patent number: 9087011Abstract: In one aspect of the present description, in connection with storing a first deduplicated data object in a primary storage pool, described operations include determining the duration of time that the first data object has resided in the primary storage pool, and comparing the determined duration of time to a predetermined time interval. In addition, described operations include, after the determined duration of time meets or exceeds the predetermined time interval, determining if the first data object has an extent referenced by another data object, and determining whether to move the first data object from the primary storage pool to a secondary storage pool as a function of whether the first data object has an extent referenced by another data object after the determined duration of time meets or exceeds the predetermined time interval. Other features and aspects may be realized, depending upon the particular application.Type: GrantFiled: May 30, 2012Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Matthew J. Anglin, David M. Cannon, Colin S. Dawson, Robert S. Elder
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Patent number: 9086988Abstract: A method for accessing memory locations includes translating, by a processor, a virtual address to locate a first page table entry (PTE) in a page table. The first PTE includes a marker and an address of a page of main storage. It is determined, by the processor, whether a marker is set in the first PTE. A large page size of a large page associated with the first PTE is identified based on determining that the marker is set in the first PTE. The large page is made up of contiguous pages of main storage. An origin address of the large page is determined based on determining that the marker is set in the first PTE. The virtual address is used to index into the large page at the origin address to access main storage.Type: GrantFiled: March 7, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Anthony J. Bybell, Michael K. Gschwind
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Patent number: 9081719Abstract: A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).Type: GrantFiled: August 17, 2012Date of Patent: July 14, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, William C. Moyer, Andrew C. Russell
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Patent number: 9081702Abstract: Techniques described enable efficient swapping of memory pages to and from a working set of pages for a process through the use of large writes and reads of pages to and from sequentially ordered locations in secondary storage. When writing pages from a working set of a process into secondary storage, the pages may be written into reserved, contiguous locations in a dedicated swap file according to a virtual address order or other order. Such writing into sequentially ordered locations enables reading in of clusters of pages in large, sequential blocks of memory, providing for more efficient read operations to return pages to physical memory.Type: GrantFiled: August 11, 2014Date of Patent: July 14, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Mehmet Iyigun, Yevgeniy (Eugene) Bak, Landy Wang, Arun U. Kishan
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Patent number: 9081693Abstract: A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.Type: GrantFiled: August 17, 2012Date of Patent: July 14, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, William C. Moyer, Andrew C. Russell
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Patent number: 9070451Abstract: Flash memory stored data modification is described. In embodiments, a flash memory system includes flash memory and a memory controller that manages data write and erase operations to the flash memory. The flash memory includes a first flash memory region of single-write flash memory cells that are each configured for a data write operation and a corresponding erase operation before a subsequent data write operation. The flash memory also includes a second flash memory region of multiple-write flash memory cells that are each configured for multiple data write operations before an erase operation.Type: GrantFiled: September 9, 2013Date of Patent: June 30, 2015Assignee: Marvell International Ltd.Inventor: Xueshi Yang
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Patent number: 9063732Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.Type: GrantFiled: November 11, 2013Date of Patent: June 23, 2015Assignee: APPLE INC.Inventors: Matthew J. Byom, Vadim Khmelnitsky, Hugo B. Fiennes, Arjun Kapoor
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Patent number: 9063866Abstract: Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. The method includes the steps of scanning page table entries of hypervisor-managed page tables continuously over repeating scan periods to determine whether memory pages have been accessed or not, and for each memory page, determining an activity level of the memory page based on whether the memory page has been accessed or not since a prior scan and storing the activity level of the memory page. The activity level of the memory page may be represented by one or more bits of its page table entry and may be classified as having at least two states ranging from hot to cold.Type: GrantFiled: July 12, 2010Date of Patent: June 23, 2015Assignee: VMware, Inc.Inventors: Kiran Tati, Irfan Ahmad
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Patent number: 9043565Abstract: A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range.Type: GrantFiled: November 19, 2012Date of Patent: May 26, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroaki Tanaka, Takeyuki Minamimoto
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Patent number: 9038044Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.Type: GrantFiled: December 5, 2013Date of Patent: May 19, 2015Assignee: MICRON TECHNOLOGY, INC.Inventors: Massimiliano Mollichelli, Andrea Martinelli, Stefan Schippers
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Publication number: 20150134922Abstract: Methods, systems, and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool.Type: ApplicationFiled: January 19, 2015Publication date: May 14, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Duane M. BALDWIN, Sandeep R. PATIL, Riyazahamad M. SHIRAGUPPI, Prashant SODHIYA
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Patent number: 9026733Abstract: Described are techniques for data processing and caching. In response to a client failing to retrieve contents of a data element from a cache location specified by a first data element identifier including a first content-based identifier, the contents of the data element are obtained and stored at a cache location specified by the first data element identifier. The contents of the data element are updated at a second point in time and stored as second contents in the data element source. The data element at the second point in time has a second content-based identifier. In response to the client failing to retrieve the second contents of the data element from a cache location specified by a second data element identifier including the second content-based identifier, the second contents of the data element are obtained and stored at a cache location specified by the second data element identifier.Type: GrantFiled: May 13, 2013Date of Patent: May 5, 2015Assignee: Pegasystems Inc.Inventors: John Clinton, Timothy Joseph Martel, Bachir Mohamed Berrachedi
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Publication number: 20150121021Abstract: Write commands for a storage device specify write data with either a first data step size or a second data step size. In the former case, the storage device performs a read-modify-write (RMW) cycle which includes reading data with the second data step size. In the latter case, the storage device executes the command in a single write cycle. A command sorting unit sorts received commands into two groups, first commands and second commands, when storing them in a memory. First commands are write commands whose data boundaries do not match with the second data step size. Second commands include write commands whose data boundaries match with the second data step size. A command issuing unit converts first commands into a second command upon predetermined conditions. The command issuing unit issues the second commands to the storage device, in preference to the first commands.Type: ApplicationFiled: October 9, 2014Publication date: April 30, 2015Inventors: Masatoshi Nakamura, Koutarou Nimura, Marie Abe, Yoshihito Konta, Hidefumi Kobayashi, Mihoko Tojo, Yasuhiro Ogasawara, Shigeru Akiyama
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Patent number: 9021185Abstract: A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.Type: GrantFiled: November 23, 2010Date of Patent: April 28, 2015Inventor: Amir Ban
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Patent number: 9021220Abstract: A method, system and computer readable medium that identify orphan storage and release the orphaned storage before application or system outages can result. More specifically, in certain embodiments, a method, system and computer readable medium periodically scan through common memory storage and identifies those areas that are no longer associated with a running task or have been allocated for longer than a running task with a matching task address. These areas are then identified as potentially orphaned storage locations.Type: GrantFiled: August 1, 2012Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: David B. LeGendre, David C. Reed, Esteban Rios, Max D. Smith
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Patent number: 9021205Abstract: A mechanism for page replacement for cache memory is disclosed. A method of the disclosure includes referencing an entry of a data structure of a cache in memory to identify a stored value of an eviction counter, the stored value of the eviction counter placed in the entry when a page of a file previously stored in the cache was evicted from the cache, determining a refault distance of the page of the file based on a difference between the stored value of the eviction counter and a current value of the eviction counter, and adjusting a ratio of cache lists maintained by the processing device to track pages in the cache, the adjusting based on the determined refault distance.Type: GrantFiled: November 30, 2012Date of Patent: April 28, 2015Assignee: Red Hat, Inc.Inventor: Johannes Weiner
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Patent number: 9021210Abstract: A mechanism is provided in a cache subsystem for cache prefetching based on non-sequential access. The mechanism determines frequently accessed non-sequential cache records in the cache subsystem. The mechanism collects trailing record statistics for the frequently accessed non-sequential cache records. The mechanism determines a caching strategy. The caching strategy comprises prefetching a set of trailing records responsive to a read of a given frequently accessed non-sequential cache record. The mechanism applies the caching strategy to the cache subsystem.Type: GrantFiled: February 12, 2013Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Bruce McNutt, Vernon W. Miller
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Patent number: 9015420Abstract: A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: GrantFiled: May 5, 2014Date of Patent: April 21, 2015Assignee: Spansion LLCInventor: Tzungren Tzeng
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Patent number: 9015441Abstract: A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.Type: GrantFiled: April 30, 2010Date of Patent: April 21, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Bruce L. Worthington, Vishal Sharda, Qi Zhang, Mehmet Iyigun, Yevgeniy Bak
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Patent number: 9015419Abstract: Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.Type: GrantFiled: June 15, 2012Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi
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Publication number: 20150106579Abstract: Computer-implemented methods and systems for managing data in one or more data storage media are provided. An example method may comprise creating a data structure within the data storage media. The data structure includes a plurality of memory pages, each page comprising a plurality of sessions, and each session comprising a header and a plurality of data objects. The method also comprises enabling writing data to the data storage medium, in response to routine requests, such that the data is recorded to the one or more data objects nearest the current location of a virtual cursor. When a data management operation is performed, the virtual cursor is moved within a single page in a single direction.Type: ApplicationFiled: October 16, 2013Publication date: April 16, 2015Applicant: Exablox CorporationInventor: Frank E. Barrus
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Patent number: 9009409Abstract: A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application. The object is stored in a cache region of the memory cache based on an identification that the object has no potential for storage in a shared memory cache and a determination that the cache region is associated with a storage policy that specifies that objects to be stored in the cache region are to be stored in a local memory cache and that a garbage collector is not to remove objects stored in the cache region from the local memory cache.Type: GrantFiled: July 12, 2011Date of Patent: April 14, 2015Assignee: SAP SEInventors: Galin Galchev, Frank Kilian, Oliver Luik, Dirk Marwinski, Petio G. Petev
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Patent number: 9009412Abstract: An information processing apparatus includes a first arithmetic processing unit, a second arithmetic processing unit that is connected to a main storage, and a third arithmetic processing unit. The first arithmetic processing unit includes a cache memory that retains therein data. The second arithmetic processing unit includes a processing unit that notifies, when a read request for the data from the third arithmetic processing unit is not being executed when the replacement request is received, the first arithmetic processing unit of a completion notification indicating that the data has been written back to the main storage and the replacement process is completed and that notifies, when the read request is being executed when the replacement request is received, the first arithmetic processing unit of the completion notification after the read request has ended.Type: GrantFiled: December 11, 2012Date of Patent: April 14, 2015Assignee: Fujitsu LimitedInventors: Go Sugizaki, Naoya Ishimura
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Publication number: 20150100730Abstract: Freeing memory safely with low performance overhead in a concurrent environment is described. An example method includes creating a reference count for each sub block in a global memory block, and each global memory block includes a plurality of sub blocks aged based on respective allocation time. A reference count for a first sub block is incremented when a thread operates a collection of data items and accesses the first sub block for a first time. Reference counts for the first sub block and a second sub block are lazily updated. Subsequently, the sub blocks are scanned through in the order of their age until a sub block with a non-zero reference count is encountered. Accordingly, one or more sub blocks whose corresponding reference counts are equal to zero are freed safely and with low performance overhead.Type: ApplicationFiled: October 4, 2013Publication date: April 9, 2015Applicant: Sybase, Inc.Inventor: Vivek Kandiyanallur
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Patent number: 9003103Abstract: A storage set (e.g., an array of hard disk drives) may experience a failure, such as a loss of power, a software crash, or a disconnection of a storage device, while writes to the storage set are in progress. Recover from the failure may involve scanning the storage set to detect and correct inconsistencies (e.g., comparing mirrors of a data set or testing checksums). However, lacking information about the locations of pending writes to the storage set during the failure, this “cleaning” process may involve scanning the entire storage set, resulting in protracted recovery processes. Presented herein are techniques for tracking writes to the storage set by apportioning the storage set into regions of a region size (e.g., one gigabyte), and storing on the nonvolatile storage medium descriptors of “dirty” regions comprising in-progress writes. The post-failure recovery process may then be limited to the regions identified as dirty.Type: GrantFiled: September 12, 2011Date of Patent: April 7, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Emanuel Paleologu, Karan Mehra, Darren Moss
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Publication number: 20150095559Abstract: A system for storing data comprises a performance storage unit and a performance segment storage unit. The system further comprises a determiner. The determiner determines whether a requested data is stored in the performance storage unit. The determiner determines whether the requested data is stored in the performance segment storage unit in the event that the requested data is not stored in the performance storage unit.Type: ApplicationFiled: October 6, 2014Publication date: April 2, 2015Inventor: R. Hugo Patterson
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Patent number: 8996796Abstract: A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.Type: GrantFiled: March 15, 2013Date of Patent: March 31, 2015Assignee: Virident Systems Inc.Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Swamy Gowda
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Patent number: 8996814Abstract: The described implementations relate to computer memory. One implementation provides a technique that can include providing stealth memory to an application. The stealth memory can have an associated physical address on a memory device. The technique can also include identifying a cache line of a cache that is mapped to the physical address associated with the stealth page, and locking one or more other physical addresses on the memory device that also map to the cache line.Type: GrantFiled: December 21, 2010Date of Patent: March 31, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Marcus Peinado, Taesoo Kim
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Publication number: 20150089169Abstract: A method according to one embodiment includes selecting, by a processor, one of a WORM logical data object and a read-write logical data object for reuse as a new WORM logical data object, said processor maintaining data attributes bound to said selected logical data object until it is determined that said selected logical data object is available for reuse. At least one temporary data attribute is assigned to said selected logical data object while maintaining said data attributes bound to said selected logical data object The selected logical data object is mounted and a write command to beginning of logical data object is received to bind at least one data attribute to said selected logical data object to replace data attributes and data associated with said selected logical data object to reuse said selected logical data object as said new WORM logical data object.Type: ApplicationFiled: November 26, 2014Publication date: March 26, 2015Inventors: Thomas W. Bish, Erika M. Dawson, Jonathan W. Peake, Joseph M. Swingler, Michael W. Wood
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Patent number: 8990531Abstract: Activity level of memory pages is classified in virtual machine environment, so that processes such as live VM migration and checkpointing, among others, can be carried out more efficiently. Because each such hypervisor-based service may desire classification of activity levels of memory pages at different frequencies and different time granularities, the hypervisor supports methods to classify activity levels of memory pages for a plurality of time intervals.Type: GrantFiled: July 8, 2011Date of Patent: March 24, 2015Assignee: VMware, Inc.Inventor: Irfan Ahmad
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Patent number: 8990504Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.Type: GrantFiled: July 11, 2011Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Tara Astigarraga, Michael E. Browne, Joseph Demczar, Eric C. Wieder
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Patent number: 8990510Abstract: A method, system and computer program product for managing requests for deferred updates to shared data elements while minimizing grace period detection overhead associated with determining whether pre-existing references to the data elements have been removed. Plural update requests that are eligible for grace period detection are buffered without performing grace period detection processing. One or more conditions that could warrant commencement of grace period detection processing are monitored while the update requests are buffered. If warranted by such a condition, grace period detection is performed relative to the update requests so that they can be processed. In this way, grace period detection overhead can be amortized over plural update requests while being sensitive to conditions warranting prompt grace period detection.Type: GrantFiled: August 15, 2008Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Paul E. McKenney, Orran Y. Krieger, Jonathan Appavoo, Dipankar Sarma
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Publication number: 20150081991Abstract: Upon receipt of an instruction to access a logical address of a storage medium, an information processing apparatus controls access to its corresponding physical address of the storage medium. A management unit manages mapping between a continuous series of logical addresses and discrete physical addresses skipping a predetermined number of replacement areas. A controller identifies to which physical address the received logical address is mapped, and controls access to the storage medium using the identified physical address. When a defect occurs in a storage area indicated by a physical address, the information processing apparatus remaps its corresponding logical address to a replacement area adjacent to the defective physical address.Type: ApplicationFiled: November 20, 2014Publication date: March 19, 2015Inventor: Akihito HIDAKA
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Publication number: 20150081992Abstract: The disclosure involves a method for saving data from webpages. The method can be realized through the following steps: when the request of saving data from a target webpage is received, whether assigned saving space is big enough for storing all the data from a target webpage is judged in the beginning; if the assigned saving space is not big enough to store all the data from the target webpage, estimate the number of page views of the current collection of webpages in the next pre-set circle and the current collection of webpages is correspondent to webpage data saved in the saving space; based on the estimated amount of page view, eliminate webpage data saved in the saving space in order to make the saving space have the ability to save all the webpage data of the collection of the webpages mentioned above; and then all the webpage data of the collection of the webpages mentioned above is saved in the space. The disclosure also provides a device for storing webpage data.Type: ApplicationFiled: November 25, 2014Publication date: March 19, 2015Applicant: Tencent Technology (Shenzhen) Company LimitedInventor: Bing CAI
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Patent number: 8984240Abstract: Page faults during partition migration from a source computing system to a destination computing system are reduced by assigning each page used by a process as being hot or cold according to their frequency of use by the process. During a live partition migration, the cold or coldest (least frequently used) pages are copied to the destination server first, followed copying the warmer (less frequently used) and concluded by copying the hottest (most frequently used) pages. After all dirtied pages have been refreshed, cutover from the instance on the source server to the destination server is made. By transferring the warm and hot pages last (or later) in the migration process, the number of dirtied pages is reduced, thereby reducing page faults subsequent to the cutover.Type: GrantFiled: August 30, 2012Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Vishal C. Aslot, Adekunle Bello, Brian W. Hart
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Publication number: 20150074361Abstract: Systems and methods for identification of data stored in memory are provided. A data packet is received and a first packet byte within the data packet is compared to a first memory byte within a memory. A mismatch is determined between the first packet byte and the first memory byte. A memory location is accessed that contains a second memory byte that is non-consecutive with the first memory byte. A packet location accessed that contains a second packet byte that is non-consecutive with the first packet byte. The second packet byte is compared to the second memory byte. A retrieval instruction is generated based at least in part on a result of the comparison between the second packet byte and the second memory byte. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance.Type: ApplicationFiled: November 19, 2014Publication date: March 12, 2015Inventors: David Anthony Hughes, Zhigang Yin, John Burns
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Patent number: 8977826Abstract: A method, system, and computer program product for ordering a plurality of data IO captured at a primary site to be applied at a secondary site, comprising removing the one or more extent level portions from the captured data IO, determining if the one or more extent level portions are time sequenced to overwrite a portion of data of the data IO, based on a determination that the portion data is to be overwritten, removing the overwritten portion of data from the plurality of the data IO and ordering the one or more extent level portions to be applied at the secondary site before the captured data IO.Type: GrantFiled: December 28, 2011Date of Patent: March 10, 2015Assignee: EMC CorporationInventors: David Meiri, Dan Arnon, Benjamin W. Yoder, Mark J. Halstead, Assaf Natanzon
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Patent number: 8966195Abstract: A system and method is illustrated for identifying an Input/Output (I/O) driver module, using a hypervisor, to receive a read command to read a virtual memory page from a remote memory location. Further, the system and method includes reading the remote virtual memory page, using the I/O driver module, into a memory buffer managed by the I/O driver module. Additionally, the system and method includes storing the virtual memory page in the memory buffer to a persistent storage device. The system and method also includes identifying a remote super page, using a hypervisor, the remote super page including a remote sub page. Additionally, the system and method includes identifying a local super page, using the hypervisor, the local super page including a local sub page. Further, the system and method includes swapping the local sub page for the remote sub page, using the hypervisor, the swapping occurring over a network.Type: GrantFiled: June 26, 2009Date of Patent: February 24, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jichuan Chang, Kevin Lim, Partha Ranganathan
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Patent number: 8966213Abstract: Provided are a computer program product, system, and method for granting and revoking supplemental memory allocation requests. Supplemental memory allocations of memory resources are granted to applications following initial memory allocations of the memory resources to the applications. In response to determining that available memory resources have fallen below an availability threshold, determining a weighting factor for each supplemental memory allocation based on at least one of an amount of the memory resources allocated to the supplemental memory allocation and a measured duration during which the memory resources have been allocated. At least one of the supplemental memory allocations is selected to revoke based on the determined weighting factors of the supplemental memory allocations.Type: GrantFiled: July 12, 2012Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Derek Logan Erdmann, David C. Reed, Thomas C. Reed, Max D. Smith
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Patent number: 8966196Abstract: A method for managing memory of a device is disclosed. A computer system collects information about use, by the device, of data in the memory of the device. The information collected by the computer system includes a time and a location for which each portion of the data is used by the device. The computer system identifies patterns of use, by the device, of each portion of the data based on the information collected. The computer system then selects one or more portions of the data that are not needed in the memory of the device based on the patterns of use by the device.Type: GrantFiled: February 25, 2013Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Al Chakra, John A. Feller, Trudy L. Hewitt, Francesco C. Schembari
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Publication number: 20150046666Abstract: A memory system includes: a memory controller configured to change data to be stored in memory cells according to an address of a weak cell in order to store changed data having a lower program level than a highest program level among a plurality of program levels in peripheral cells adjacent to the weak cell; and a memory device configured to execute a program loop in order to store the changed data in a selected page.Type: ApplicationFiled: October 25, 2013Publication date: February 12, 2015Applicant: SK hynix Inc.Inventors: Yun Kyoung LEE, Jung Ryul AHN
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Publication number: 20150046667Abstract: A method includes computing, in a local storage system having a local volume with a plurality of local regions, respective local checksum signatures over the local regions, and computing, in a remote storage system having a remote volume with remote regions in a one-to-one correspondence with the local regions, respective remote checksum signatures over the remote regions. A given remote region is identified, the given remote region having a given remote signature and a corresponding local region with a given local signature that does not match the given remote signature. The data in the given remote region is then replaced with data from the corresponding local region.Type: ApplicationFiled: October 24, 2014Publication date: February 12, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ram ELRON, Ehood GARMIZA, Haim HELMAN, Assaf NITZAN
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Patent number: 8954789Abstract: Method and system for performing recovery for a replicated copy of a storage space presented as a logical object is provided. An attribute associated with the logical object for enabling the recovery is set and when the storage space is replicated the attribute is stored as metadata for the replicated copy of the storage space. Based on the attribute, a clone of the logical object is presented as a writable option to write to the first replicated copy. After the write operation where information is written to the clone, a second replicated copy with the clone information is created. The clone is deleted after the second copy is generated.Type: GrantFiled: June 7, 2013Date of Patent: February 10, 2015Assignee: NetApp, Inc.Inventors: Muralidharan Rangachari, Anagha Barve, Vineeth Karinta
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Patent number: 8954692Abstract: A file protecting method and system and a memory controller and a memory storage apparatus using the same are provided. The file protecting method includes performing a file protection enabling procedure for a file to generate an entry value backup according to at least one entry value corresponding to at least one cluster storing the file, which is recorded in a file allocation document, store the entry value backup in a secure storage area and change the entry value corresponding to the cluster storing the file in the file allocation document, wherein the file cannot be read according to the changed entry value. Accordingly, the file stored in the memory storage apparatus the can be effectively protected from being accessed by an un-authorized person.Type: GrantFiled: July 17, 2012Date of Patent: February 10, 2015Assignee: Phison Electronics Corp.Inventor: Chien-Fu Lee
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Patent number: 8949556Abstract: An apparatus and computer program product for managing memory of a device is disclosed. A computer system collects information about use, by the device, of data in the memory of the device. The information collected by the computer system includes a time and a location for which each portion of the data is used by the device. The computer system identifies patterns of use, by the device, of each portion of the data based on the information collected. The computer system then selects one or more portions of the data that are not needed in the memory of the device based on the patterns of use by the device.Type: GrantFiled: December 10, 2012Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Al Chakra, John A. Feller, Trudy L. Hewitt, Francesco C. Schembari
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Patent number: 8943269Abstract: A data block storage management capability is presented. A file system includes a plurality of data blocks which are managed using a first storage service and a second storage service, where the first storage service has a lower storage cost and a higher input-output cost than the second storage service. The data blocks stored using the second storage service have associated therewith respective expected storage durations indicative of respective lengths of time for which the data blocks are to be stored using the second storage service (which may be the same or different across the ones of the data blocks stored using the second storage service). The expected storage durations of the data blocks are modified based on a comparison of an expected hit rate of the second storage service and a current hit rate of the second storage service or current hit rates of the data blocks.Type: GrantFiled: April 13, 2012Date of Patent: January 27, 2015Assignee: Alcatel LucentInventors: Krishna P. Puttaswamy Naga, Murali Kodialam
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Patent number: 8943276Abstract: A plurality of tracks is examined for meeting criteria for a discard scan. In lieu of waiting for a completion of a track access operation, at least one of the plurality of tracks is marked for demotion. An additional discard scan may be subsequently performed for tracks not previously demoted. The discard and additional discard scans may proceed in two phases.Type: GrantFiled: March 14, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Michael T. Benhase, Lokesh M. Gupta, Carol S. Mellgren, Kenneth W. Todd