Entry Replacement Strategy Patents (Class 711/159)
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Patent number: 8898404Abstract: A memory management method is provided to manage a memory in which areas of a garbage collected Java heap memory and a non-garbage collected external heap memory can be secured, by using a program executed by a processor in a computer. If it is judged that there is no reference to all data arranged in the external heap memory or starting point data of reference relations included in the all data, from data arranged outside the external heap memory, then the external heap memory is judged to be capable of being deallocated. As a result, it becomes possible to implement memory management in which garbage collection needing a long time program stop is not conducted and an additional API is not used.Type: GrantFiled: October 28, 2009Date of Patent: November 25, 2014Assignee: Hitachi, Ltd.Inventors: Motoki Obata, Hiroyasu Nishiyama, Masahiko Adachi
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Publication number: 20140344536Abstract: A storage system may include a queue included in a memory and a controller configured to store commands received from a host in the queue. The queue may have a linked-list configuration. In response to a triggering event, the controller may take a snapshot of the queue, creating a snapshot queue. The snapshot queue may have a linear configuration. Subsequent analysis or parsing of queued information may be performed on the linear snapshot queue instead of the linked-list queue. Modifications to the linear snapshot queue may be corresponding made to the linked-list queue.Type: ApplicationFiled: May 15, 2013Publication date: November 20, 2014Inventors: Shay Benisty, Yan Dumchin, Yair Baram, Tal Sharifie
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Publication number: 20140344535Abstract: Various embodiments of accidental shared volume erasure prevention include systems, methods, and/or computer program products for receiving a request to access a volume from a requesting system, determining whether the volume is associated with any system other than the requesting system, and preventing accidental erasure of the volume based on the determination.Type: ApplicationFiled: May 14, 2013Publication date: November 20, 2014Applicant: International Business Machines CorporationInventors: Gavin S. Johnson, Michael J. Koester, John R. Paveza
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Publication number: 20140331015Abstract: A method for recovering from uncorrected memory errors may include receiving, at an operating system, a correctable error (CE) associated with a first memory page. The correctable error is marked in a page table entry describing the first memory page. The first memory page is then migrated, by the operating system, to a second memory page based on the received correctable error.Type: ApplicationFiled: May 6, 2013Publication date: November 6, 2014Applicant: International Business Machines CorporationInventor: ARAVINDA PRASAD
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Patent number: 8880814Abstract: The present invention overcomes the disadvantages of the prior art by providing a technique that stripes data containers across volumes of a striped volume set (SVS) using one of a plurality of different data placement patterns to thereby reduce the possibility of hotspots arising due to each data container using the same data placement pattern within the SVS. The technique is illustratively implemented by calculating a first index value, an intermediate index value and calculating a hash value of an inode associated with a data container to be accessed within the SVS. A final index value is calculated by multiplying the intermediate index value by the hash value, modulo the number of volumes of the SVS. Further, a Locate( ) function may be used to compute the location of data container content in the SVS to which a data access request is directed to ensure consistency of such content.Type: GrantFiled: October 15, 2013Date of Patent: November 4, 2014Assignee: NetApp, Inc.Inventors: Robert W. Hyer, Richard Jernigan, Bryan Schmersal
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Patent number: 8880963Abstract: There are provided a message processing device and a method improved to store a plenty of messages used for processing. When a message is transmitted to another node for providing a service, a message processing unit (26) monitors the message transferred and stores it in a storage region whose allocation is released when the remaining memory amount has become little. When an error has occurred in the processing of a service providing unit (200), the message processing unit (26) stores the error type and a session identifier associated with it. When a message transmission is requested from outside and the error type, the session identifier, and a message associated with them are stored, the message processing unit (26) transmits them. If the storage region which was containing a message is released and no message exists, the message processing unit (26) transmits the other two items.Type: GrantFiled: September 6, 2005Date of Patent: November 4, 2014Assignee: Hewlett-Packard Development Company, L. P.Inventor: Hideaki Nobata
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Patent number: 8880775Abstract: In a particular embodiment, a controller is adapted to perform a garbage collection operation to remove redundant data, to predict a performance parameter associated with performance of the garbage collection operation, and to abort the garbage collection operation when the predicted performance parameter exceeds a threshold.Type: GrantFiled: June 20, 2008Date of Patent: November 4, 2014Assignee: Seagate Technology LLCInventors: Stefanus Stefanus, Feng Shen, Wei Loon Ng
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Patent number: 8880824Abstract: Redundant data is globally de-duplicated across a shared architecture that includes a plurality of storage systems. The storage systems implement copy-on-write or WAFL to generate snapshots of original data. Each storage system includes a de-duplication client to identify and reduce redundant original and/or snapshot data on the storage system. Each de-duplication client can de-duplicate a digital sequence by breaking the sequence into blocks and identifying redundant blocks already stored in the shared architecture. Identifying redundant blocks may include hashing each block and comparing the hash to a local and/or master hash table containing hashes of existing data. Once identified, redundant data previously stored is deleted (e.g., post-process de-duplication), or redundant data is not stored to begin with (e.g., inline de-duplication). In both cases, pointers to shared data blocks can be used to reassemble the digital sequence where one or more blocks were deleted or not stored on the storage system.Type: GrantFiled: April 12, 2013Date of Patent: November 4, 2014Assignee: EMC CorporationInventor: Jedidiah Yueh
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Patent number: 8880494Abstract: A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.Type: GrantFiled: October 28, 2011Date of Patent: November 4, 2014Assignee: Brocade Communications Systems, Inc.Inventors: Jian Liu, Philip Lynn Leichty, How Tung Lim, John Michael Terry, Mahesh Srinivasa Maddury, Wing Cheung, Kung Ling Ko
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Publication number: 20140324782Abstract: A data portion is evicted from a buffer, where the evicted data portion is modified from a corresponding data portion in a persistent storage. Write elision is applied to suppress writing the evicted data portion to the persistent storage. Subsequent to applying the write elision and in response to reading a version of the data portion, a redo of a modification of the read data portion is applied.Type: ApplicationFiled: April 26, 2013Publication date: October 30, 2014Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventor: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
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Publication number: 20140325168Abstract: A data storage device receives data and corresponding attribute data, stores the received data and the corresponding attribute data in a storage region of the data storage device, and automatically processes invalid data among the received data stored in the storage region based on the corresponding attribute data.Type: ApplicationFiled: April 28, 2014Publication date: October 30, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Eun Jin Yun
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Publication number: 20140325167Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.Type: ApplicationFiled: April 30, 2013Publication date: October 30, 2014Applicant: International Business Machines CorporationInventors: Timothy J. Slegel, Lisa C. Heller, Erwin F. Pfeffer, Kenneth E. Plambeck
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Patent number: 8874859Abstract: A virtualized computer system employs a virtual disk with a space efficient (SE) format to store data for virtual machines running therein. The SE format allows for defragmentation at a fine-grained level, where unused, stale, and zero blocks are moved to the end of the virtual disk so that the virtual disk may be truncated and space reclaimed by the underlying storage system as part of a special defragmentation process.Type: GrantFiled: December 22, 2010Date of Patent: October 28, 2014Assignee: VMware, Inc.Inventors: Murali Vilayannur, Krishna Yadappanavar, Faraz Shaikh, Manjunath Rajashekhar, Satyam B. Vaghani
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Patent number: 8874860Abstract: A method for logical buffer pool extension identifies a page in a memory for eviction, and analyzes characteristics of the page to form a differentiated page. The characteristics of the page include descriptors that include a workload type, a page weight, a page type, frequency of access and timing of most recent access. The method also identifies a target location for the differentiated page from a set of locations including a fastcache storage and a hard disk storage to form an identified target location. The method further selects an eviction operation from a set of eviction operations using the characteristics of the differentiated page and the identified target location. The differentiated page is written to the identified target location using the selected eviction operation, where the differentiated page is written only to the fastcache storage.Type: GrantFiled: December 7, 2012Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Matthew A. Huras, Aamer Sachedina
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Publication number: 20140317363Abstract: A method for optimizing memory usage in a device having a universal controlling application includes receiving into the device data for use in configuring the universal controlling application wherein the data is used to identify from within a library of command code sets stored in a memory of the device a command code set that is appropriate for use in commanding functional operations of the appliance and causing a non-identified one or more of the command code sets of the library of command code sets stored in the memory of the device to be discarded to thereby create freed space in the memory of the device.Type: ApplicationFiled: March 13, 2014Publication date: October 23, 2014Applicant: UNIVERSAL ELECTRONICS INC.Inventors: Arsham Hatambeiki, Jan VanEe, Christopher Lee Somerville, Daniel Morrionne
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Patent number: 8868842Abstract: A WC resource usage is compared with an auto flush (AU) threshold Caf that is smaller than an upper limit Clmt, and when the WC resource usage exceeds the AF threshold Caf, the organizing state of a NAND memory 10 is checked. When the organizing of the NAND memory 10 has proceeded sufficiently, data is flushed from a write cache (WC) 21 to the NAND memory 10 early, so that the response to the subsequent write command is improved.Type: GrantFiled: December 28, 2009Date of Patent: October 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Ryoichi Kato, Toshikatsu Hida
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Publication number: 20140310486Abstract: A unified request queue includes multiple entries for servicing multiple types of requests. Each of the entries of the unified request queue is generally allocable to requests of any of the multiple request types. A number of entries in the unified request queue is reserved for a first request type among the multiple types of requests. The number of entries reserved for the first request type is dynamically varied based on a number of requests of the first request type rejected by the unified request queue due to allocation of entries in the unified request queue to other requests.Type: ApplicationFiled: April 12, 2013Publication date: October 16, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: BENJIMAN L. GOODMAN, HARRISON M. McCREARY, ERIC E. RETTER, STEVEN L. ROBERTS, JEFFREY A. STUECHELI
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Publication number: 20140310487Abstract: A unified request queue includes multiple entries for servicing multiple types of requests. Each of the entries of the unified request queue is generally allocable to requests of any of the multiple request types. A number of entries in the unified request queue is reserved for a first request type among the multiple types of requests. The number of entries reserved for the first request type is dynamically varied based on a number of requests of the first request type rejected by the unified request queue due to allocation of entries in the unified request queue to other requests.Type: ApplicationFiled: September 25, 2013Publication date: October 16, 2014Inventors: BENJIMAN L. GOODMAN, HARRISON M. McCREARY, ERIC E. RETTER, STEVEN L. ROBERTS, JEFFREY A. STUECHELI
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Patent number: 8862848Abstract: A data storage system comprises a controller, a first lower performance storage medium and a second higher performance storage medium. The controller is connected to the storage mediums and is arranged to control I/O access to the storage mediums. The controller is further arranged to store an image on the first storage medium, initiate a copy function from the first storage medium to the second storage medium, direct all I/O access for the image to the second storage medium, periodically age data from the second storage medium to the first storage medium, create a new empty bitmap for each period, and in response to an I/O access for data in the image, update the latest bitmap to indicate that the data has been accessed and update the previous bitmaps to indicate that the data has not been accessed.Type: GrantFiled: August 25, 2010Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Carlos Francisco Fuente, William James Scales, Barry Douglas Whyte
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Publication number: 20140297976Abstract: An electronic device may include a memory, and a processor coupled to the memory for storing and accessing data in the memory. The processor may arrange the data in a stack data container including values extending from a stack top to a stack bottom, operate the stack data container in first and second modes of operation, and while in the first mode of operation, push and pop a respective value from the stack top of the stack data container. The processor may also while in the second mode, reverse an orientation of the stack data container and the values therein, and push and pop a respective value from the stack bottom of the reversed stack data container.Type: ApplicationFiled: June 13, 2014Publication date: October 2, 2014Inventor: Laurie Dean PERRIN
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Patent number: 8849351Abstract: The present invention provides a method involving at least one mobile unit having at least one first session with a base station router. The method includes vacating at least one first session associated with the at least one mobile unit.Type: GrantFiled: December 29, 2006Date of Patent: September 30, 2014Assignee: Alcatel LucentInventors: John K. Burgess, Ken Del Signore, David Vollman, David Welch
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Patent number: 8850138Abstract: Embodiments disclosed herein provide a high performance content delivery system in which versions of content are cached for servicing web site requests containing the same uniform resource locator (URL). When a page is cached, certain metadata is also stored along with the page. That metadata includes a description of what extra attributes, if any, must be consulted to determine what version of content to serve in response to a request. When a request is fielded, a cache reader consults this metadata at a primary cache address, then extracts the values of attributes, if any are specified, and uses them in conjunction with the URL to search for an appropriate response at a secondary cache address. These attributes may include HTTP request headers, cookies, query string, and session variables. If no entry exists at the secondary address, the request is forwarded to a page generator at the back-end.Type: GrantFiled: September 14, 2012Date of Patent: September 30, 2014Assignee: Open Text, S.A.Inventor: Mark R. Scheevel
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Patent number: 8849875Abstract: At least one region of a heap that includes memory allocations is analyzed, using age and occupancy criteria, across a number of local garbage collection cycles using a processor executing a region-based garbage collector. Based upon the analyzed age and occupancy criteria of the at least one region, at least one stable region in age and occupancy is identified among the at least one region of the heap across the number of local garbage collection cycles. Maintenance of a remembered set (RS) of external references into the at least one stable region is temporarily stopped for each identified stable region during at least one additional local garbage collection cycle.Type: GrantFiled: October 15, 2013Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Peter W. Burka, Aleksandar Micic, Ryan A. Sciampacone
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Patent number: 8843721Abstract: A data storage system comprises a controller, a first lower performance storage medium and a second higher performance storage medium. The controller is connected to the storage mediums and is arranged to control I/O access to the storage mediums. The controller is further arranged to store an image on the first storage medium, initiate a copy function from the first storage medium to the second storage medium, direct all I/O access for the image to the second storage medium, periodically age data from the second storage medium to the first storage medium, create a new empty bitmap for each period, and in response to an I/O access for data in the image, update the latest bitmap to indicate that the data has been accessed and update the previous bitmaps to indicate that the data has not been accessed.Type: GrantFiled: March 14, 2013Date of Patent: September 23, 2014Assignee: International Business Machines CorporationInventors: Carlos Francisco Fuente, William James Scales, Barry Douglas Whyte
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Patent number: 8843712Abstract: A method and system for performing sensed garbage collection in a memory is disclosed. In one embodiment, a method includes measuring arrival times of read/write commands received from a processor executing an application; transforming the arrival times from a time domain to frequency domain data; locking onto a phase of the read/write commands; determining predicted arrival times of future read/write commands; creating a real-time schedule of memory requests using the arrival times of the read/write commands and the predicted arrival times of the future read/write commands; using the real-time schedule to sense idle periods where the application will not make a request of the memory; and performing garbage collection in the memory during at least one of the idle periods.Type: GrantFiled: January 28, 2013Date of Patent: September 23, 2014Assignee: Marvell International Ltd.Inventor: Ronald D. Smith
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Publication number: 20140281296Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.Type: ApplicationFiled: October 16, 2013Publication date: September 18, 2014Applicant: NVIDIA CORPORATIONInventors: Jerome F. DULUK, JR., Cameron BUSCHARDT, Sherry CHEUNG, James Leroy DEMING, Samuel H. DUNCAN, Lucien DUNNING, Robert GEORGE, Arvind GOPALAKRISHNAN, Mark HAIRGROVE, Chenghuan JIA, John MASHEY
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Publication number: 20140281295Abstract: A technique for supporting user mode specification of RCU grace period latency to an operating system kernel-level RCU implementation. Non-expedited and expedited RCU grace period mechanisms are provided for invocation by RCU updaters performing RCU update operations to respectively initiate non-expedited and expedited grace periods. An expedited grace period indicator in a kernel memory space is provided for indicating whether a non-expedited RCU grace period or an expedited RCU grace period should be invoked. The non-expedited RCU grace period mechanism is adapted to check the expedited grace period indicator, and if an expedited RCU grace period is indicated, to invoke the expedited grace period mechanism. A communication mechanism is provided for use by a user mode application executing in a user memory space to manipulate the expedited grace period indicator in the kernel memory space, and thereby control whether an expedited or non-expedited RCU grace period should be used.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Paul E. McKenney
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Publication number: 20140281298Abstract: An approach is provided for suggesting data for deletion from an electronic data storage medium. An external device detects initiation of transfer of data from first storage medium to second storage medium. Next, the external device determines an available storage in the second storage medium for the data. Then, the external device generates a list to suggest content for deletion within the second storage medium to accommodate the data.Type: ApplicationFiled: May 31, 2014Publication date: September 18, 2014Applicant: Core Wireless Licensing, S.a.r.l.Inventors: Craig PUGSLEY, Jesmond Allen
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Publication number: 20140281297Abstract: Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.Type: ApplicationFiled: December 19, 2013Publication date: September 18, 2014Applicant: NVIDIA CORPORATIONInventors: Jerome F. DULUK, JR., John MASHEY, Mark HAIRGROVE, Chenghuan JIA, Cameron BUSCHARDT, Lucien DUNNING, Brian FAHS
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Patent number: 8838903Abstract: A hierarchical data-storage system has a volatile storage medium, a first non-volatile storage medium, and a controller including a ranking engine tracking data writes to each of the memory mediums. Each medium is associated with a pre-set capacity threshold, and the controller, upon the volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the volatile medium, copies the data in those blocks to the non-volatile medium, and marks those blocks as available for new data writes, and the controller, upon the non-volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the non-volatile medium, and marks those blocks as available for new data writes from the volatile medium.Type: GrantFiled: February 4, 2010Date of Patent: September 16, 2014Assignee: Dataram, Inc.Inventor: Jason Caulkins
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Publication number: 20140258650Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform two or more operations with respect to data units. The operations include: a second read operation, different from the first read operation, that retrieves a data unit to be read based at least in part on an address of a data block containing the data unit to be read, and a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Inventors: Ephraim Meriwether Vishniac, Stephen J. Schmidt
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Publication number: 20140258655Abstract: Disclosed are a method for data de-duplication and an apparatus for the same. The method may comprise obtaining access property of data based on input request or output request for the data, determining de-duplication unit of the data based on the access property, and performing de-duplication on the data based on the de-duplication unit. Thus, data de-duplication rate may be determined adaptively based on input/output characteristics of data. Also, data de-duplication may be performed based on the determined data de-duplication rate so as to provide low input/output latency.Type: ApplicationFiled: March 7, 2014Publication date: September 11, 2014Applicant: POSTECH ACADEMY - INDUSTRY FOUNDATIONInventors: Chan Ik Park, Se Jin Park
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Publication number: 20140258651Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, and configured to store, for at least some of the data blocks, corresponding historical information about prior removal of one or more data units from that data block, the removal affecting at least some addresses of data units in that data block. The system is configured to perform at least one operation that accesses at least a first data unit stored in a first data block according to address information interpreted based on any stored historical information corresponding to the first data block.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: Ab Initio Technology LLCInventors: Ephraim Meriwether Vishniac, Stephen J. Schmidt
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Publication number: 20140258653Abstract: Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.Type: ApplicationFiled: October 7, 2013Publication date: September 11, 2014Applicant: Virident Systems Inc.Inventors: Vijay Karamcheti, Kenneth A. Okin, Kumar Ganapathy, Ashish Singhai, Rajesh Parekh
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Publication number: 20140258652Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform one or more operations with respect to data units, the operations including a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit, with the second data block having the same size as the first data block.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: Ab Initio Technology LLCInventors: Ephraim Meriwether Vishniac, Stephen J. Schmidt
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Publication number: 20140258769Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: LSI CORPORATIONInventors: Leonid Baryudin, Alex G. Tang, Earl T. Cohen
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Publication number: 20140258656Abstract: Methods, program products, and systems for lock-free object recycling are described. In some implementations, a system can provide a type-neutral wrapper for a first data object. Upon receiving an indicator that the first data object is no longer used, the system can store the first data object and the type-neutral wrapper in a lock-free data structure. Upon receiving a request to create a second data object, the system can fetch the type-neutral wrapper and the first data object from the lock-free data structure without using a lock. The system can then return the first data object as a response to the request.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: Apple Inc.Inventor: Wei-De Ju
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Publication number: 20140258654Abstract: For the purpose of suppressing decrease of a deduplication rate in a storage system, a storage system according to the present invention includes: a data buffer; a dividing unit configured to generate divided data by dividing data inputted into the data buffer; and a storage processing unit configured to store the divided data into a storage device while eliminating duplicate storage. The dividing unit is configured to generate the divided data by dividing the data inputted into the data buffer by a preset division standard based on the content of the data and also divide, by the division standard, connected data that residual data being left without being divided by the division standard and continuing data continuing to the residual data and being inputted in the data buffer are connected.Type: ApplicationFiled: March 6, 2014Publication date: September 11, 2014Applicant: NEC CorporationInventor: Kenji Mori
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Patent number: 8831409Abstract: Storage management technology, in which a system determines a first amount of storage space on a downloader device of a user that is available for download of new content made available on channels subscribed to by the user. The system also determines a second amount of storage space needed to download new content that has been made available on channels subscribed to by the user. The system further compares the second amount of storage space to the first amount of storage space and determines whether the second amount of storage space exceeds the first amount of storage space. Based on a determination that the second amount of storage space exceeds the first amount of storage space, the system controls downloading of the new content to the downloader device and deletion of previously-stored content on the downloader device based on a content allocation policy.Type: GrantFiled: June 7, 2010Date of Patent: September 9, 2014Assignee: PurpleComm Inc.Inventors: Jack H. Chang, William H. Sheu, Sherman Tuan
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Patent number: 8832381Abstract: A processor is provided. The processor including a cache, the cache having a plurality of entries, each of the plurality of entries having a tag array and a data array, and a remapper configured to create at least one identifier, each identifier being unique to a process of the processor, and to assign a respective identifier to the tag array for the entries related to a respective process, the remapper further configured to determine a replacement value for the entries related to each identifier.Type: GrantFiled: February 21, 2011Date of Patent: September 9, 2014Assignee: Advanced Micro Devices, Inc.Inventor: Douglas B. Hunt
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Patent number: 8832393Abstract: In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels.Type: GrantFiled: April 18, 2012Date of Patent: September 9, 2014Assignee: LSI CorporationInventors: Jung Ho Cho, Vladimir Sindalovsky, Lane A. Smith
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Patent number: 8825969Abstract: A hardware and/or software facility to enable emulated storage devices to share data stored on physical storage resources of a storage system. The facility may be implemented on a virtual tape library (VTL) system configured to back up data sets that have a high level of redundancy on multiple virtual tapes. The facility organizes all or a portion of the physical storage resources according to a common store data layout. By enabling emulated storage devices to share data stored on physical storage resources, the facility enables deduplication across the emulated storage devices irrespective of the emulated storage device to which the data is or was originally written, thereby eliminating duplicate data on the physical storage resources and improving the storage consumption of the emulated storage devices on the physical storage resources.Type: GrantFiled: November 29, 2010Date of Patent: September 2, 2014Assignee: NetApp, Inc.Inventors: Vivek Gupta, Ameet Pyati, Satish Singhal, Pawan Saxena
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Patent number: 8825951Abstract: A mechanism is provided for managing a high speed memory. An index entry indicates a storage unit in the high speed memory. A corresponding non-free index is set for a different type of low speed memory. The indicated storage unit in the high speed memory is assigned to a corresponding low speed memory by including the index entry in the non-free index. The storage unit in the high speed memory is recovered by demoting the index entry from the non-free index. The mechanism acquires a margin performance loss corresponding to a respective non-free index in response to receipt of a demotion request. The margin performance loss represents a change in a processor read operation time caused by performing a demotion operation in a corresponding non-free index. The mechanism compares the margin performance losses of the respective non-free indexes and selecting a non-free index whose margin performance loss satisfies a demotion condition as a demotion index.Type: GrantFiled: March 27, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Xue D. Gao, Chao Guang Li, Yang Liu, Yi Yang
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Publication number: 20140237199Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.Type: ApplicationFiled: April 25, 2014Publication date: August 21, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Simon Murray, Geraint M. North
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Patent number: 8812804Abstract: A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.Type: GrantFiled: January 6, 2012Date of Patent: August 19, 2014Assignee: Texas Instruments IncorporatedInventors: Steven C. Goss, Gregory R. Conti, Narendar Shankar, Mehdi-Laurent Akkar, Aymeric Vial
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Patent number: 8812791Abstract: A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache.Type: GrantFiled: October 8, 2013Date of Patent: August 19, 2014Assignee: Google Inc.Inventors: Timo Burkard, David Presotto
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Patent number: 8812773Abstract: In a method of merging blocks in a semiconductor memory device according to example embodiments, a plurality of data are written into one or more first blocks using a first program method. One or more merge target blocks that are required to be merged are selected among the one or more first blocks. A merge-performing block for a block merge operation is selected among the one or more first blocks and one or more second blocks. A plurality of merge target data are written from the merge target blocks into the merge-performing block using a second program method that is different from the first program method.Type: GrantFiled: May 24, 2011Date of Patent: August 19, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Min-Seok Kim, Ki-Tae Park
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Patent number: 8812767Abstract: A method of controlling a memory including a first storage area and a second storage area. The method includes determining, in response to a request for writing a write data string, whether the write data string changes a logical value stored in the memory from a first logical value to a second logical value, writing, to the first storage area, a logical value that is located in a position of the write data string and does not change an existing logical value of the memory from the first logical value to the second logical value, and writing the second logical value that is located in a position of the write data string and changes an existing logical value of the memory from the first logical value to the second logical value to the second storage area which is different from the first storage area.Type: GrantFiled: January 18, 2012Date of Patent: August 19, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kazuya Sawa
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Publication number: 20140229691Abstract: A data control system comprises a communication interface, a processing system, and a storage system. The communication interface is configured to receive a request to retrieve data from a primary storage volume that includes a secondary storage volume. The storage system is configured to store the primary storage volume that includes the secondary storage volume. The processing system is configured to identify changed segments of a plurality of segments in the primary storage volume and identify allocated segments of the changed segments. The communication interface is further configured to transfer the allocated segments in response to the request.Type: ApplicationFiled: April 19, 2014Publication date: August 14, 2014Applicant: Quantum CorporationInventors: Gregory L. Wade, J. Mitchell Haile
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Patent number: RE45222Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.Type: GrantFiled: June 2, 2011Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-soo Kim, Gui-young Lee, Jong-Min Kim, Ji-hyun In, Je-sung Kim, Sam-hyuk Noh, Sang-Iyul Min, Dong-hee Lee, Jae-yong Jeong, Yoo-kun Cho, Jong-moo Choi