Abstract: Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.

Abstract: A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a first type and a signal presence detect unit configured to provide configuration data associated with a memory package of a second type to the memory controller. The configuration data may be used to configure the memory controller to interface with the memory package of a first type.

Abstract: According to one embodiment, a method for preemptively migrating a failing extent includes receiving information of one or more failure conditions associated with an extent stored in a first storage portion of a first storage tier; predicting a failure of the extent based on the information; selecting a second storage portion located in one of a plurality of storage tiers; and migrating the extent to the selected second storage portion.

Abstract: Various embodiments are directed to group-based data storage systems configured for maintaining data exchanged between client devices within channel-specific shards each corresponding with one or more group-identifiers to provide group-based access to those channel-specific shards and for applying group-specific policies for data stored within those channel-specific shards. Membership of particular users within particular groups and within particular channels may be monitored such that access to particular channel shards may be controlled based on group-memberships of the users, and access to data stored within particular channel shards may be controlled based on channel-memberships of the users.

Abstract: A data storage device includes: a plurality of nonvolatile memory devices; and a controller suitable for receiving a command and executing the command for the plurality of nonvolatile memory devices. The controller includes: a first queue suitable for storing the command; and a command manager suitable for managing the command in the first queue, based on a first attribute of the command and queue information of the first queue.

Abstract: A method of controlling one or more data services in a computing environment includes the following steps. A request to one of read data from and write data to one or more storage devices in a computing environment is obtained from an application executing on a host device in the computing environment. One or more application-aware parameters associated with the data of the request are obtained. Operation of the one or more data services is controlled based on the one or more application-aware parameters.

Abstract: A method of operating a memory device, a first setting signal is received by a first memory device among a plurality of memory devices. The first memory device has a first storage capacity, and the memory devices may be connected to one another by a single channel. A second setting signal is received by a second memory device among the plurality of memory devices. The second memory device has a second storage capacity different from the first storage capacity. N refresh operations are performed by the first memory device based on a first refresh command and the first setting signal during a first refresh period. M refresh operations are performed by the second memory device based on a second refresh command and the second setting signal during a second refresh period. A duration of the second refresh period is substantially the same as a duration of the first refresh period.

Abstract: A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.

Abstract: A bufferless ring network including at least two nodes and at least two timeslots, the at least two timeslots include a dedicated timeslot, and a first node in the bufferless ring network has use permission for the dedicated timeslot. The first node is configured to, in a state of having the use permission for the dedicated timeslot, detect whether all dedicated timeslots that pass through the first node are available, set a permission switch signal, and cancel the use permission for the dedicated timeslot according to the permission switch signal after detecting that all the dedicated timeslots that pass through the first node are available. A remaining node in the bufferless ring network is configured to obtain the use permission for the dedicated timeslot according to the permission switch signal. The remaining node is a node that needs to use the dedicated timeslot.

Abstract: In general, embodiments of the technology relate to a method for managing data. The method includes, in response to initiating garbage collection on a storage appliance, selecting a first block from the plurality of blocks based, at least in part, on a selection frequency; and performing a garbage collection operation on the first block to generate a first erased block in the storage appliance.

Abstract: An integrated circuit may include memory interface circuitry for communicating with an external or in-package memory module. The integrated circuit may also include out-of-order (OOO) clients and in-order (IO) clients that issue read and write commands to the memory interface circuitry. The memory interface circuitry may include a memory controller having an OOO command scheduler, a write data buffer, and a simple read data pipeline. The memory interface circuitry may also include a multiport arbitration circuit for interfacing with the multiple clients and also OOO adaptor circuits interposed between the multiport arbitration circuit and the IO clients. Each of the OOO adaptor circuits may include an ID generator and a local reordering buffer and may allow the memory controller to return data to the various clients without throttling.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for managing a journal. A method may include reordering storage commands based on different storage volumes associated with the storage commands. A method may include reordering storage commands based on different snapshots associated with the storage commands. A method may include adjusting a frequency of writing data from a write buffer based on a rate of write requests. A method may include adjusting a ratio of storage capacity for storing mirrored write data to storage capacity for storing non-mirrored read data.

Abstract: A semiconductor device includes a latch circuit and a first command generation circuit. The latch circuit generates a first internal control signal and a first internal chip selection signal in synchronization with an internal clock signal. The first command generation circuit generates a first normal command if the first internal chip selection signal having an enabled state is inputted in synchronization with an inverted internal clock signal. The first command generation circuit also generates a first control command if the first internal control signal having a second predetermined state is inputted in synchronization with the inverted internal clock signal.

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

Abstract: An apparatus may include a graphics processing unit (GPU) and a hypervisor. The hypervisor may include a command parser to parse graphics memory addresses associated with a workload of a virtual machine of the apparatus, and generate a first shadow global graphics translation table (SGGT) for translating the graphics memory addresses. The hypervisor may further include a GPU scheduler to check conflict between the first SGGTT and a second SGGTT containing graphics memory addresses used by working sets being-executed or to-be-executed by the render engines of the GPU, and schedule the workload of the virtual machine to a render engine when there is no conflict between the first SGGTT and the second SGGTT. Other embodiments may be described and/or claimed.

Abstract: The examples described herein discuss various systems, software, devices, and methods for managing a primary command queue by ordering and/or reordering and distributing incoming commands based, at least in part, on positional information of one or more components of data storage devices. More specifically, in some embodiments, the examples discussed herein describe ordering and distributing incoming commands from a primary command queue in a position-aware manner that takes into account disk rotation (e.g., rotational position) and/or actuator head location for the various data storage devices of a data storage system enclosure. Among other benefits, ordering incoming commands at the primary command queue and distributing the ordered commands to individual device queues improves overall command execution latency.

Abstract: A first request may be received to write a first set of data to a first storage device of a first storage node. The first storage device may be capable of transferring or receiving data directly to or from a second storage device without transferring the data to or from a host device mapped to the first storage node. It may be determined that a first token clash check does not need to occur for the first request. The first token clash check may include determining whether the first request is requesting to write to one or more addresses that are associated with one or more tokens owned by one or more transactions. The one or more tokens may be a proxy for a set of data within one or more particular address ranges of the first storage device.

Abstract: An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.

Abstract: An electronic system includes a memory controller and a memory. The memory controller generates a plurality of controller clocks having different phases from one another based on a reference clock signal. The memory generates a plurality of internal clocks having different phases from one another by receiving first and second clocks having a phase difference from each other, and outputs one of odd-ordered data and even-ordered data in synchronization with the plurality of internal clocks.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: According to one embodiment, a storage system includes a controller. The controller receives, from a host, a write command including a block address indicating a first block in a plurality of blocks, and a page address indicating a first page of the first block. The controller writes data designated by the write command to the first page of the first block. The controller notifies the host 2 of a page address indicating a latest readable page which is included in pages of the first block, the pages containing data which was written by the host before the designated data was written to the first page, the latest readable page having become readable by writing the designated data to the first page.

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract: Techniques are described for injecting noise in a timer value provided to an instruction requesting the timer value. A plurality of tasks may execute on a processor, wherein the processor may comprise one or more processing cores and each task may include a plurality of computer executable instructions. In accordance with one technique for injecting noise in the timer value, a request for a first timer value is received by one or more computer executable instructions belonging to a first task from the plurality of tasks, and in response, a second timer value is provided to the first task instead of the first timer value, wherein the second timer value is derived from the first timer value and a random number.

Abstract: Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.

Abstract: An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.

Abstract: Supply of power to a plurality of circuits is controlled efficiently depending on usage conditions and the like of the circuits. An address monitoring circuit monitors whether a cache memory and an input/output interface are in an access state or not, and performs power gating in accordance with the state of the cache memory and the input/output interface. The address monitoring circuit acquires and monitors an address signal between a signal processing circuit and the cache memory or the input/output interface periodically. When one of the cache memory and the input/output interface is in a standby state and the other is in the access state, power gating is performed on the circuit that is in the standby state.

Abstract: A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialization instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialization instruction SSI added to a second issue queue 10. The master serialization instruction MSI manages serialization relative to the instructions within the first issue queue 8. The slave serialization instruction SSI manages serialization relative to the instructions within the second issue queue 10. The master serialization instruction MSI and the slave serialization instruction SSI are removed when both have met their serialization conditions and are respectively the oldest instructions within their issue queues.

Abstract: Methods and systems are described herein for determining if bit cell read or write rates require a refresh of the accessed or neighboring bit cells. The refresh of VLT memory bit cells that undergo a high frequency of page address read operations and write operations helps to maintain integrity of data stored in the VLT memory bit cells. The methods and systems determine, during each RAS cycle, if a rate of Page Address read operations or write operations exceeds a maximum rate across an interval, and conditionally cause a refresh operation if the rate exceeds the maximum rate. The methods and systems output a write back signal to cause a refresh of the associated VLT memory bit cells to prevent corruption of data stored in the associated VLT memory bit cells.

Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.

Abstract: An electronic device able to re-initialize following a failed initialization has a processor, a first storage device, and a second storage device. The processor receives storage information stored at the first storage device and sets a plurality of storage parameters of the first storage device, according to the storage information, and re-initializing the first storage device based on the storage parameters. When the initialization fails, the processor adjusts the storage parameters of the first storage device and re-initializes the first storage device based on the adjusted storage parameters.

Abstract: An article of apparel with grasp-resistant panels includes a multilayer textile having a first fabric layer possessing a first elongation value bonded to a second fabric layer possessing a second elongation value, where the second elongation value is less than the first elongation value. In an embodiment, the first fabric layer is a stretch knit and the second fabric layer is a non-stretch woven. The second fabric layer is discontinuous, defining a plurality of panels spaced along the first fabric layer. The article of apparel selectively stretches, expanding along non-paneled areas. With this configuration, the article of apparel fits onto multiple body types, providing full range of motion while inhibiting the grasping and holding of the apparel by a non-wearer.

Abstract: A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.

Abstract: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions; reordering the instructions in accordance with processor resources for dispatch and execution; ensuring a closest earlier store in machine order for to a corresponding load, by determining if said store has an actual age but said corresponding load does not have an actual age, then said store is earlier than said corresponding load; if said corresponding load has an actual age but said store does not have an actual age, then said corresponding load is earlier than said store; if neither said corresponding load or said store have an actual age, then a virtual identifier table is used to determine which is earlier; and if both said corresponding load and said store have actual ages, then the actual ages are used to determine which is earlier.

Abstract: Provided is a method and apparatus of selecting a preemption technique for a computation unit included in a processor to execute a second task before the at least one computation unit finishes executing a first task. The method includes receiving a preemption request, predicting a cost of preemption techniques based on a progress of the first task until receipt of the preemption request, and selecting one of the preemption techniques based on the predicted cost.

Abstract: A storage system includes a memory unit group that includes a first memory unit and a plurality of second memory units, and the first memory unit is connected to the plurality of second memory units so that data can be transmitted between the first memory unit and the second memory units. The plurality of second memory units is mounted on a same first substrate. One second memory unit of the plurality of second memory units cooperates with the first memory unit and does not cooperate with the other second memory units of the plurality of second memory units.

Abstract: A pseudo-dual-port (PDP) memory system includes a memory array, timing and control logic, and multiplexer-latch (MUX-latch). The MUX-latch comprises integrated address selection logic and latching logic, such that the combination multiplexes and latches an address in a single change in response to a state change in the read select or write select signals. The multiplexing and latching defines a single operation or state change in the MUX-latch. Since the multiplexing delay and the latching delay for a read operation are coincident with each other rather than being incurred one after the other, memory read operations are fast.

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Abstract: A scan driving circuit and a driving method thereof, an array substrate, and a display apparatus are disclosed.

Abstract: A storage system monitors the first access frequency of occurrence which is the access frequency of occurrence from a host device during a first period, and the second access frequency of occurrence which is the access frequency of occurrence from a host device during a second period shorter than the first period. Along with performing data relocation among the tiers (levels) in the first period cycle based on the first access frequency of occurrence, the storage system performs a decision whether or not to perform a second relocation based on the first access frequency of occurrence and the second access frequency of occurrence, synchronously with access from a host device. Here the threshold value utilized in a decision on whether or not to perform the first relocation is different from the threshold value utilized in a decision on whether or not to perform the second relocation.

Abstract: A Serial Peripheral Interface (SPI) controller is provided for use within a computer system. The SPI controller includes a clock that generates system clock signals that synchronize a data transfer operation, and a dynamic clock delay element that phase shifts the clock signals with a delay offset and outputs read data that was received during a read operation from an SPI slave device with the clock signals that were phase shifted.

Abstract: A system and method for the collection, capture, processing, storage, and tracking of data for both electronic clinical trial and electronic heath records based upon a single data collection instance, and including data collected by electronic medical devices. Devices and methods for creating certified digital image copies of original documents, including paper source documents for a clinical trial. Devices and methods for ensuring the secure archiving of original electronic documents, including electronic clinical trial source documents, in a secure document storage server.

Abstract: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device.

Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.

Abstract: An electronic system includes: a storage interface configured to receive system information; a storage control unit, coupled to the storage interface, configured to implement a preprocessing block for partitioning data based on the system information; and a learning block for processing partial data of the data for distributing machine learning processes.

Abstract: Nodes of a database service may receive a read request to perform a read of a record stored by the database service and a transaction request to perform a transaction to the record. First and second indications of time may be associated with the read and transaction, respectively. A potential read anomaly (e.g., fuzzy read, read skew, etc.) may be detected based, at least in part, on a determination that the first indication of time is within a threshold value of the second indication of time. In response to detecting the potential read anomaly, the read may be performed after the transaction specified by the transaction request, regardless of whether the first indication of time is indicative of an earlier point in time than the second indication of time.

Abstract: A method, system and memory controller are provided for implementing signal integrity fail recovery and mainline calibration for Dynamic Random Access Memory (DRAM). After identifying a failed DRAM, the DRAM is marked as bad and taken out of mainline operation. Characterization tests and periodic calibrations are run to evaluate optimal settings and to determine if the marked DRAM is recoverable. If recoverable, the marked DRAM chip is redeployed. If unrecoverable, error reporting is provided to the user.

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Abstract: Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating is used to adaptively turn individual interleaved switched-capacitor stages of a voltage converter on and off based on workload information to improve voltage conversion efficiency. Further, as a countermeasure against machine learning based differential power analysis attacks, for example, control signals provided to a number of the interleaved switched-capacitor stages are delayed to reduce the risk of low power trace entropy (PTE). A higher PTE value is maintained regardless of the phase difference between an attacker's sampling rate and the operating frequency, providing an additional layer of security.

Abstract: A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die satisfies a background maintenance criterion. Upon identifying a layer satisfying the background maintenance criterion, the valid data from reclaim blocks in the layer is relocated into a relocation block in the same layer until the relocation block is filled and the background maintenance cycle ends.

Abstract: Techniques are disclosed relating to enabling virtual machines to access data on a physical recording medium. In one embodiment, a computing system provides a logical address space for a storage device to an allocation agent that is executable to allocate the logical address space to a plurality of virtual machines having access to the storage device. In such an embodiment, the logical address space is larger than a physical address space of the storage device. The computing system may then process a storage request from one of the plurality of virtual machines. In some embodiments, the allocation agent is a hypervisor executing on the computing system. In some embodiments, the computing system tracks utilizations of the storage device by the plurality of virtual machines, and based on the utilizations, enforces a quality of service level associated with one or more of the plurality of virtual machines.