Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

Abstract: Techniques described and suggested herein include systems and methods for storing, indexing, and retrieving original data of data archives on data storage systems using redundancy coding techniques. For example, redundancy codes, such as erasure codes, may be applied to archives (such as those received from a customer of a computing resource service provider) so as allow the storage of original data of the individual archives available on a minimum of volumes, such as those of a data storage system, while retaining availability, durability, and other guarantees imparted by the application of the redundancy code. Sparse indexing techniques may be implemented so as to reduce the footprint of indexes used to locate the original data, once stored. The volumes may be apportioned into failure-decorrelated subsets, and archives stored thereto may be apportioned to such subsets.

Abstract: A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.

Abstract: According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.

Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Abstract: An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave that directs one or more commands to two or more queues, where the one or more commands are separated by command type into the queues. Each bank includes a set of queues in the bank interleave controller. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank.

Abstract: Techniques related to a processing accelerator with queue threads are described herein.

Abstract: A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.

Abstract: Methods and structure for selective cache mirroring. One embodiment includes a control unit and a memory. The memory is able to store indexing information for a multi-device cache for a logical volume. The control unit is able to receive an Input/Output (I/O) request from a host directed to a Logical Block Address (LBA) of the logical volume, to consult the indexing information to identify a cache line for storing the I/O request, and to store the I/O request at the cache line on a first device of the cache. The control unit is further able to mirror the I/O request to another device of the cache if the I/O request is a write request, and to complete the I/O request without mirroring the I/O request to another device of the cache if the I/O request is a read request.

Abstract: In a memory scheduling method, a memory controller writes a first group of first row strobe commands (ACTs) into a first memory. The first group of first ACTs includes multiple first ACTs and a periodic interval exists between two adjacent first ACTs written by the memory controller into the first memory. The memory controller writes operation commands that correspond to the first group of first ACTs into the first memory after writing the first group of first ACTs into the first memory. The memory controller writes second ACTs into a second memory in periodic intervals for writing the first group of first ACTs into the first memory and/or in periodic intervals for writing the operation commands that correspond to the first group of first ACTs. The memory controller writes operation commands that correspond to the second ACTs into the second memory.

Abstract: In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

Abstract: A method and system are disclosed for allowing access to processing resources of one or more idle memory devices to an active memory device is disclosed, where the idle and active memory devices are associated with a common host. The resources shared may be processing power, for example in the form of using a processor of an idle memory to handle some of the logical-to-physical mapping associated with a host command, or may be other resources such as RAM sharing so that a first memory has expanded RAM capacity. The method may include exchanging tokens with resource sharing abilities, operation codes and associated data relevant to the requested resources.

Abstract: Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

Abstract: A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.

Abstract: Provided is a primary memory module including a counter for providing a count indicative of the numbers of times the primary memory module has ever been read/written by a processor. With the count, an operating situation of the primary memory module is evaluated so as to optimize memory allocation performed by the operation system, adjust the operating mode of the primary memory module, and send a warning message to a user, for example.

Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.

Abstract: A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.

Abstract: A write leveling control method which includes registering data-related signal (DRS) reference delay values corresponding to types of memory modules in a leveling reference table; transmitting write leveling-related signals to a first type of memory module mounted on a target board; detecting timing skews between a clock signal and data-related signals received from memory devices on the mounted memory module; and adjusting a delay of a data-related signal transmitted to a memory device of the mounted memory module if a corresponding timing skew is outside of a first range, based on the DRS reference delay value corresponding to the mounted memory module.

Abstract: Embodiments include systems and methods for enabling a physical layer (PHY) link signaling channel between a network termination modem and a cable modem in a cable network. The PHY link signaling channel is embedded within the same multi-carrier channel as the data and enables PHY link up between the network termination modem and cable modern without involvement of higher layers (e.g., MAC). The PHY link signaling channel can be implemented in the downstream (from the network termination modem to the cable modem(s)) or in the upstream from a cable modem to the network termination modem. Embodiments are applicable to any known cable network, and particularly to cable networks implementing the DOCSIS and EPoC standards.

Abstract: A memory system having a plurality of memory devices includes a controller for separately accessing the memory devices. The memory system includes a data bus for transferring data, a control bus for transferring a command and address CAL, and first and second memory devices coupled to the data bus and the control bus. The controller controls the first and second memory devices through the data bus and the control bus, wherein the first and second memory devices have different values of the CAL, and wherein a difference of the CAL values is greater than or equal to a RAS to CAS delay time tRCD.

Abstract: Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation.

Abstract: A data processing system includes a memory controller which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs data, a data strobe signal, an external command, and a clock signal. The second semiconductor device aligns the data in synchronization with the data strobe signal to generate first and second alignment data and latches the first and second alignment data to generate first and second latch data in response to a latch signal which is generated by dividing the data strobe signal.

Abstract: An aspect includes a method of interface clock frequency switching control that includes determining a first clock delay adjustment of a clock signal for an interface at a first clock frequency. A controller determines a second clock delay adjustment for the interface operated at a second clock frequency. The controller computes an insertion delay between the clock signal and a data signal of the interface based on the first clock delay adjustment and frequency and the second clock delay adjustment and frequency. The controller also computes a third clock delay adjustment to operate the interface at a third clock frequency based on the insertion delay and a relative difference between the third clock frequency and the second clock frequency. The clock signal is adjusted based on the third clock delay adjustment to align timing of the clock signal with the data signal at the third clock frequency.

Abstract: In one embodiment, a request is received from a requesting node in a network to assist in distributing a task of the requesting node. Upon receiving the message, a capability to perform the task of one or more helping nodes in the network is evaluated, and a helping node of the one or more helping nodes is selected to perform the task based on the evaluated capability of the selected helping node. The distribution of the task is then authorized from the requesting node to the selected helping node.

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

Abstract: Techniques and mechanisms handle transactions between various components of a memory controller. For example, a memory controller may include a component implemented in configurable logic and another component implemented in hard logic.

Abstract: A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.

Abstract: A semiconductor device includes a memory cell array including a plurality of memory array basic units. A first bus for transfer of address/control signals, includes a first buffer circuit operating as a pipeline register. A second bus for bidirectional transfer of write/read data, includes a second buffer circuit operating as a pipeline register. A first control circuit sequentially sends the address/control signals on the first bus, and a second control circuit sequentially sends/receives write/read data on the second bus.

Abstract: According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access request to a memory controller associated with the memory access request. The memory controller is coupled to memory and to the crossbar interconnect. The memory controller includes a queue and is configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request.

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

Abstract: Each of a plurality of circuit blocks includes a plurality of arithmetic elements. A power supply controller individually controls power supply to each circuit block. A resource management unit acquires first information, regarding an arithmetic element necessary for an arithmetic process, and second information, regarding an arithmetic element included in a circuit block which is currently being supplied with power. Based on the first information and the second information, the resource management unit preferentially assigns, to an arithmetic element included in a circuit block which is being supplied with power, a process for implementing the arithmetic process.

Abstract: This disclosure describes systems, methods, and computer-readable media related to testing tools for devices. In some embodiments, input may be received by a user device from a user. The input may include semantic inputs and analysis parameters. The semantic inputs may be converted to test events. The test events may be transmitted to a device for testing. The user device may receive a first set of data from the device and a second set of data from a camera. The second set of data may be processed. Test results may be generated based at least in part on the analyzed first set of data and the processed second set of data. The generated test results may be presented to the user.

Abstract: A technique for managing failover from a first data storage system to a second data storage system includes configuring replication settings for data objects associated with VSPs (Virtualized Storage Processors) on a per-VSP basis, such that all of the data objects associated with each VSP share common replication settings. As the first data storage system operates a VSP, operations replicate data written to any of the data objects of the VSP to the second data storage system such that the second data storage system acquires and stores a replica of the VSP. In the event of a failure at the first data storage system, operations fail over the entire VSP, including all of its data objects, to the second data storage system, to restore host access to the data objects from the VSP replicas. A metro-cluster may be formed from multiple data storage systems that use this failover approach.

Abstract: Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

Abstract: A method and system for authenticating computer nodes on a network, including providing a synchronized clock system, at a predetermined clock frequency, for use with an electronic system with a plurality of system nodes. Matching counters are connected to each of the plurality of system nodes, each of the counters being incremented in accordance with the clock frequency experienced by the system nodes to which the counters are connected. A difference is calculated between a count number at the end of a certain interval and the count number for the same counter at the beginning of the interval, to arrive at a count difference for each counter. The count difference of a particular counter is compared with the count difference of at least two other counters and, in the event that the count difference of the particular counter does not match, that node is noticed as an imposter.

Abstract: A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a memory write burst command having a first frame that includes a corresponding opcode positioned in one of a first command slot or a second command slot. The memory write burst command may also include a number of subsequent frames for conveying a data payload, as specified for example, by the opcode. The control unit may be configured to generate a number of concurrent sequential memory write operations to the memory in response to receiving the memory write burst command.

Abstract: A method of handling multicast command packets in a ring topology includes transmitting a multicast indication packet indicating that at least one command packet following the multicast indication packet is intended for at least two of a plurality of storage devices connected in the ring topology, determining whether the at least one command packet following the multicast indication packet is intended for each storage device from among the plurality of storage devices based on the multicast indication packet, and operating at least one storage device from among the plurality of storage devices that the at least one command packet is not intended for in a packet bypass mode until the at least one command packet has been processed by the at least two storage devices that the at least one command packet is intended for.

Abstract: A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.

Abstract: A memory control circuit is configured to take a priority for each transfer instruction into account but not the priority in a memory access unit, and thus processing of a high-priority transfer instruction received during a memory access needs to wait for a long time. The memory control apparatus divides the received transfer instruction into a memory access unit and, when the transfer instruction having a higher priority is received during the memory access, the memory access based on a low-priority transfer instruction is interrupted and starts the memory access based on the high-priority transfer instruction.

Abstract: Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined.

Abstract: A system manages the allocation and storage of media content instance files in a storage device of a media client device. In one embodiment among others, the system includes logic for processing successive portions of received media content instances and storing received media content instances in the storage device as respective media content instance files; and a processor configured with the logic to track the size of media content instance files to provide an indication of available free space, such that the indication is independent of a first buffer space in the storage device.

Abstract: A strobed signaling interface generates a reduced-frequency replica of an incoming strobe signal and applies the replica to extend the interval over which strobe-sampled write data values remain available for transfer to a clocked timing domain. Quadrature instances of the reduced-frequency strobe replicas may be generated and occasionally sampled by skew control logic within the memory component to obtain a coarse measure of the skew between the strobed and clocked timing domains. When the strobe-to-clock domain skew is outside a predetermined boundary, the skew control logic selects an alternative clock signal edge (i.e., earlier or later edge) to sample strobed data, thereby reducing the effective skew between the two timing domains.

Abstract: A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein the memory device interface comprises an address output configured to transmit address values, a write data output configured to transmit write data on rising and falling edges of a periodic signal, and a read data input configured to receive read data at the same rate as the write data.

Abstract: A method, including receiving a sequence of events to be counted. The method further includes, in response to each event, setting a respective bit in a memory that consists of multiple words organized in tiers, such that a number of set bits in the memory is indicative of a count of the received events, and such that each set bit in a first tier corresponds to a respective word in a second tier and is indicative of whether the corresponding word is fully populated with set bits.

Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

Abstract: A first indicator of a first number of cache misses to a cache memory of a multicore processor for a first application over a first time period is received. The first application executes on a first core of the processor and a second application simultaneously executes on a second core of the processor during the first time period. The first and second cores share the cache memory. A second indicator of a second number of cache misses to the cache memory for the first application over a second time period is received. During the second time period, the first application executes on the first core and the second application does not execute on the second core. A degree of contention among the first and second applications is determined based on the first and second indicators, and execution of the second application is adjusted based on the determined degree of contention.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For write commands, the memory controller does not need to issue a completion interrupt to the host system upon completion of the command because the host system considers the write command completed at the time that the write command is pushed into the queue of the memory controller. The combination of all of these features results in a large reduction in overall latency.