Abstract: A media information distribution and recording system for distributing media information from a central apparatus to terminal apparatus through a network and for recording the media information on a detachable recording medium in the terminal apparatus, wherein the terminal apparatus serves not only as a transmitting terminal apparatus, but also as a receiving terminal apparatus, is proposed, together with the terminal apparatus, a media information recording apparatus for use in this system, and a recording medium which stores a program that controls the operation of a computer for use in this system as well as in the media information recording apparatus.

Abstract: In the method of generating an interleaved address, each 2^i mod (p?1) value for i=0 to x?1 is stored. Here, p is a prime number dependent on a block size K of a data block being processed and x is greater than one. An inter-row sequence number is multiplied with a column index number to obtain a binary product. Both the inter-row sequence number and the column index number are for the block size K and the prime number p. Then, each binary component of the binary product is multiplied with a respective one of the stored 2^i mod (p?1) values to obtain a plurality of intermediate mod value. An intra-row permutation address is generated based on the plurality of intermediate mod values, and an interleaved address is generated based on the intra-row permutation address.

Abstract: A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in response to N−1 number of the align control signals for receiving N-bit data and outputting the N-bit data in a parallel fashion; and a outputting block in response to the remaining align control signal for receiving the N-bit data in the parallel fashion and synchronizing the N-bit data with the remaining align control signal having a N/2 external clock period to thereby generating the synchronized N-bit data as a prefetched data.

Abstract: A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.

Abstract: A method for accelerating storage access in a network. The method comprises receiving a data record having a plurality of data segments. The data segments are stored in a local memory of a network controller (NC). A virtual write buffer (VWB) entry is assigned for the incoming data record in the NC local memory. The data segments of said data record are reassemble using the VWB. The data record is sent from the network controller directly to an I/O controller of a storage device.

Abstract: A first array of disk drives overlaps with a second array of disk drives in a Redundant Array of Inexpensive Drives (RAID) system, in which the first and second arrays share at least one disk drive. A first stripe of data from a first client is stored in the first array, and a second stripe of data from a second client is stored in the second array. The shared disk drives are less than the number of drives needed to reconstruct a full stripe. Thus, in the event of a drive failure in the first array, the first client can reconstruct the first data stripe, but is never able to reconstruct the second stripe. Likewise, in the event of a drive failure in the second array, the second client can reconstruct the second data stripe, but is never able to reconstruct the first stripe.

Abstract: A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

Abstract: Systems, methods, and devices for real-time searching are disclosed. A method comprises receiving a real-time data stream comprised of a plurality of characters and placing the characters in shift registers, the shift registers holding a current term. During each clock cycle of the data stream, the current term is evaluated to determine whether it matches any terms in a dictionary of terms, including indexing a plurality of look-up tables with the characters in each of the shift registers. A match data is output based on the evaluating. The method may be implemented in hardware in a computer forensic device, a controller, a computing device, and in other devices.

Abstract: A data storage circuit having a plurality of memory cells (S1), a plurality of bit lines (BL, /BL) and a precharge circuit further comprises a discharge circuit. In an operating mode of the data storage circuit, the bit lines (BL, /BL) are precharged by the precharge circuit under the control on the basis of a chip enable signal (CE) before write or read of data into/from the memory cells (S1) and in a standby state, the bit lines (BL, /BL) are discharged by the discharge circuit. Further, also in a sleep mode, the bit lines (BL, /BL) are discharged by the discharge circuit. With this circuit configuration and operation, it is possible to provide the data storage circuit which allows reduction in standby power consumption by suppressing standby currents in the standby state.

Abstract: A memory system includes a memory array for storing a plurality of data elements, the memory array comprising a plurality of memory blocks. In one embodiment, the data element are tag string data. The memory system may also include a comparator unit coupled to receive a memory block output and an input signal, wherein when the memory block output matches the input signal, the memory system transmits a match signal and a code word on a result bus. In one embodiment, data elements are stored as fragments in different portions of the memory array. The input signal may be received as fragments and compared to the data elements over different time periods. In one embodiment, the present invention provides a memory lookup system and method that supports multiple protocols.

Abstract: In a microcontroller (100) the command decoder (15) has access to at least one memory (14). The command decoder may thus be adapted to decode at least one conditional command, while the result of decoding the conditional command is dependent on the contents of said memory (14). The microcontroller according to the invention thus provides the possibility of considerably reducing the programming effort so that both the system performance and the code density can be significantly increased with a small additional number of hardware components.

Abstract: A memory system having a memory controller, interface device and plurality of memory elements. The interface device is coupled to the memory controller via a first high-speed signal path. The plurality of memory elements are removably coupled to the interface device via respective second signal paths, each of the second signal paths having a lower signaling bandwidth than the first signaling path.

Abstract: A voltage generation circuit includes a voltage pump that receives a supply voltage and develops an output voltage responsive to a pump activation signal. A level detection circuit receives a pump-boost signal and is coupled to the voltage pump to receive the output voltage. The level detection circuit operates in a normal mode responsive to the pump-boost signal being inactive to develop the pump activation signal to activate the voltage pump responsive to the output voltage being less than or equal to a first low threshold value. The level detection circuit operates in a demand-controlled mode responsive to the pump-boost signal being active to develop the pump activation signal to activate the voltage pump responsive to the output voltage being less than or equal to a second low threshold value.

Abstract: An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.

Abstract: The present invention provides an information processing system that can have the optimum number of FIFO stages dynamically at any given time so that the system makes it possible to omit analyzing of the number of FIFO stages from data characteristics so as to improve the performance. The information processing system includes a data FIFO 22 for storing data sets and a next pointer 29 having the same number of storage positions as that of the data FIFO 22. A preceding data set is stored in the storage position “1” of the data FIFO 22 and a subsequent data set is stored in the storage position “7” of the data FIFO 22. At this time, the storage position “1” of the next pointer 29 stores “7” as information on a storage position for the subsequent data set. According to this information “7”, the subsequent data set is read from the storage position “7” of the data FIFO 22.

Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Abstract: Information regarding the quality of performance of a plurality of suppliers that each supply goods to a vendor is generated by initially gathering data regarding the quality of performance of the plurality of suppliers in a plurality of different computer databases, some of all of which may be incompatible. The gathered data from the plurality of different computer databases is stored in a central controller. Then, the stored data in the central controller converted into a compatible format and stored in a single database. From that single database, information regarding the quality of performance of a plurality of suppliers can be generated.

Abstract: A method for capturing and grouping digital images using a digital camera includes the steps of capturing a first group of digital images using the digital camera; storing the first group of digital images in corresponding digital image files in a memory in the digital camera; and designating, in response to a user input, that subsequent captured digital images are to form a second group of digital images. The method further includes the steps of capturing the second group of digital images using the digital camera; storing the second group of digital images in corresponding digital image files in the memory; and storing a single control file in the memory separate from the stored digital image files, the single control file containing data identifying the first and second groups of digital images.

Abstract: A pluggable tablespace is enabled by logically partitioning a database into a set of tablespaces and storing all of the tablespaces disk pointers in tablespace-relative format. A pluggable set of tablespaces is unplugged by generating the associated metadata, and making a binary copy of the tablespaces. The pluggable set of tablespaces is plugged into a target database by making the pluggable set accessible to the target database and incorporating the associated metadata, without patching any of the disk pointers.

Abstract: An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and applies the stored compensation voltage to a compensation input of the compensation circuit of the amplifier during a measurement phase. Feedback from a source of the transistor controls the output of the differential amplifier to maintain a standard voltage across a resistive memory element connected to the source during measurement of the resistance of the resistive memory element, and the compensation circuit improves the accuracy of the voltage across the resistive memory element by compensating for an offset voltage of the differential amplifier.

Abstract: Method for dynamically allocating/de-allocating memory pools (0, 1, 2, 3) in a physical memory of a computer comprising the steps of: allocating a memory area (4) for said memory pools (0, 1, 2, 3) within said physical memory, allocating said at least one memory block (2a, 2b) within each of said at least one memory pool (0, 1, 2, 3), and writing data in said at least one memory block (2a). To enable dynamic memory allocation, and to reduce memory fragmentation it is proposed that said at least one memory block (2a) is de-allocated after said at least one memory block (2a) is marked empty, and that at least one memory block (2a) is re-allocated within said memory area (4), whereby said memory block (2a) is moved within said memory area (4) during said de-allocation/re-allocation of said at least one memory block (2a, 2b).

Abstract: In a flush memory system according to the present invention, a merge control section (3f) reads data on an enabled page from a predetermined physical block using a read section (3b), and writes the data onto a blank page using a write section (3c), thereby copying the data on the enabled page onto the blank page. Then, the merge control section disables the source, enabled page using a page-disabling section (3e). When finishing the copying of data on all the enabled pages in the predetermined physical block, the merge control section collectively erases all the data in the physical block using an erase section (3d).

Abstract: In each embodiment of this invention, a pairing apparatus has a random pairing module which generates pairings from the first to (r1)-th rounds by the random system, and a modified Swiss pairing module which generates pairings from the (r1+1)-th to r-th rounds by the modified Swiss system. When first several matches are paired by the random system, win points are distributed to respective participating teams in accordance with their merits. For this reason, by subsequent pairings of the modified Swiss system, participating teams can be successively paired within a close merit range. Hence, the total win points (ranks) can reflect the merits. For this reason, the reverse phenomenon of merits and ranks can be suppressed without using the round-robin system.

Abstract: The invention includes a system and method for logging network server data such as data relating to client requests. In accordance with the invention, end users of a server program can create one or more logging modules, each having a predefined interface that is defined by the server program. In response to client requests, the server program calls logging modules that have been designated by a system administrator, and passes potential log data to the logging modules. In response to receiving the potential log data, each logging module makes its own decision regarding (a) whether to make a log entry, (b) which data should be included in the log entry, and (c) the format that is used for recording the log data. In this way, end users are not constrained to any given logging format or set of logging criteria.

Abstract: Methods and apparatus for constructing objects within a cache system thereby allowing the cache system to respond to requested objects that are not initially available within the cache system. One embodiment of the invention caches image files, where the images are divided into components and stored in a format that allows identification and access to the components. The cache system determines that an object, such as an image file, is missing from the cache memory, locates sufficient components from the cache memory and/or external storage, and constructs the object from the located components.

Abstract: The present invention is directed to a loadable virtual memory manager, and generally to a computer operating system capable of supporting application programs running in a computer having a working memory, the computer operating system including a kernel resident in the working memory at run time, and a loadable virtual memory manager resident at link time outside of the working memory and dynamically loadable into the working memory at run time upon demand of one of the application programs. The kernel includes a loader for loading the virtual memory manager into the working memory in response to a demand from one of the application programs. The computer is able to access a storage memory separate from the working memory, the loadable virtual memory manager residing at link time in the storage memory. The loader loads the virtual memory manager from the storage memory to the working memory.

Abstract: A method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit. Some embodiments provide a method for accessing memory-mapped registers that are distributed across a first integrated circuit, the first integrated circuit including a plurality of logic subset modules, wherein each of the plurality of logic subset modules includes one or more memory-mapped registers. This method includes receiving a memory-mapped register access request into the first integrated circuit, serially transmitting, through each of the plurality of logic subset modules, a first plurality of data packets based on the memory-mapped register access request, wherein the first plurality of data packets includes an address specification for a memory-mapped register associated with a first one of the logic subset modules, and within the first logic subset module, accessing the memory-mapped register associated with the first logic subset module.

Abstract: File system cells are linked together to form a meta file system that appears to a user or application program to be a single file system. Each file system cell may have a conventional file system format, and can be indistinguishable from a conventional file system except for information, such as directory entry attributes, indicating one or more links to other file system cells. These external links may include direct links that are hidden from the user or application program and define a hierarchy of the meta file system cells, and indirect links that appear in the user-visible file system. The meta file system substantially reduces crash recovery time because each file system cell functions as a consistency unit that can be repaired only if needed. The meta file system also permits the file system cells to be accessed concurrently by multiple processors in a file server.

Abstract: A portable device includes a data file storage device, a camera section with an image pickup function and a schedule management section that manages a user's schedule. The data file storage device includes a picture file storage region for storing picture files and a schedule storage region for storing schedule data. When storing a picture file of a picture picked up by the camera section in the picture file storage region, schedule data that matches the file creation date and time of the picture file is searched among the entire schedule data stored in advance in the schedule storage region. When there is schedule data that matches the file creation date and time, schedule character data that represents the content of the schedule is obtained and a filename and/or a folder name is created based on the schedule character data obtained, or the schedule character data is embedded in EXIF data and stored.

Abstract: Method of managing access of a plurality of data processing circuits (4, 7) to a common memory (1) comprising several banks (A-D), the memory being connected to one or several circuits (7) for processing ordinary data and to a circuit (4) for processing priority data, the method comprising the steps of:—producing an access demand of the or one of the circuits for processing ordinary data to a bank of the memory;—starting the realization of the demanded access;—subsequently producing an access demand of the circuit for processing priority data to another bank of the memory;—preparing (PRE, ACT), during the realization of the access demanded by the or one of the ordinary data processing circuits, said other bank of the memory;—interrupting the access in the course of realization as soon as said preparation is completed.

Abstract: A vehicular electronic control apparatus is provided with a program memory, a data memory, a RAM, a microprocesser, a reference data storage memory, a data memory abnormality judging section, and at least two transfer sections for a RAM. The reference data storage memory stores reference data corresponding to variable control data stored in the data memory. The data memory abnormality judging section judges whether the variable control data stored in the data memory are normal or abnormal. The first transfer section transfers and writes the variable control data from the data memory to the RAM. The second transfer section writes estimated variable control data based on the reference data from the reference data storage memory to the RAM.

Abstract: A system is formed with a controller connected to devices and a tool. The controller controls the devices by a control program which specifies the devices by their object names. Correlation data correlating their communication addresses, assigned memory address and device names are stored in an object database. Data are transmitted and received by referencing the correlation data to specify an access address from a device name used as a key. In the case of a reuse, only the addresses need to be updated without modifying the control program.

Abstract: A multi-ported register comprises a Global Bit Line (GBL) to couple a gate to a data output line via an output transistor. A Local bit Line (LBL) couples the gate to a first register file cell and a second register file cell, said second register file cell disposed closer to the data output line than the first register file cell. At least one transistor in the first register file cell having a stronger drive current than the at least one transistor in the second register file cell. At least one of, the output transistor, the gate, and the first register file cell of a first bank have a stronger drive current than the corresponding output transistor, the gate and the first register file cell of a second bank said second bank being closer to the data output line.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

Abstract: A memory system includes a memory controller and a plurality of memory devices located on a power plane and coupled to the memory controller. The memory system further includes a sense resistor coupled to the power plane and a power source coupled to the sense resistor.

Abstract: A synchronous Flash memory device is described that enhances initialization and boot memory device identification in synchronous memory systems. A boot memory is typically a separate device that is tied to a specific chip select line and/or address range of a system, whereas synchronous Flash memory generally can be placed in any available memory slot and assigned one of several possible chip selects and address ranges. This lack of predictability makes installing a boot memory based on a non-volatile synchronous memory device difficult. A synchronous Flash boot memory device of the detailed invention is adapted to identify itself and its chip select/address range to the memory controller at power up, reset, or upon receiving an identification request. This allows the utilization of the detailed synchronous Flash memory as a boot memory in synchronous systems where a reserved boot memory slot and/or chip select are not provided.

Abstract: A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register and which simultaneously transfers two data, in which, in the case where an LDCTX instruction which is the instruction for loading data to more than two register is executed, a combined data of two data each of which is to be loaded in different register is transferred from the operand access unit to the data register, and high order 4 bytes of data and low order 4 bytes of in the data register are simultaneously transfers to two register through two data transfer paths, respectively, and in the case where an STCTX instruction which is the instruction for storing data from more than two register is executed, contents of the two registers are simultaneously transferred to a high order 4 bytes and a low order 4 b

Abstract: A memory controlling apparatus which receives from an upper module of a system a command to read data from a memory module or write data in the memory module and controls accessing the memory module in response to the command. The memory controlling apparatus includes a first transmitter which transmits an address of read data or write data and the write data to a memory module via an address line; and a second transmitter which transmits data read from a memory module to the upper module of the system via a data line.

Abstract: A pair of buses connect devices and a processor on a backplane. Each device monitors both buses for a bus reset that is produced by the processor on detecting a fault with the active bus, at which time the processor switches to the inactive bus and produces a bus reset signal on the inactive bus, telling the devices to switch to the inactive active bus. The devices are programmed to respond to the reset signal on either bus to make it the active bus.

Abstract: To maintain order in a pipelined process, a number of memory locations of a result memory are sequentially reserved for a number of processes as the processes are sequentially dispatched for execution. As an integral part of the sequential reservation, validity determination facilitators to be subsequently employed to correspondingly facilitate determining whether valid processing results of said processes have been stored into corresponding ones of said reserved memory locations are also pre-determined. Additionally, the reserved memory locations are sequentially read to sequentially accept the processing results in order. Each value read from a reserved memory location is accepted only if the corresponding validity determination facilitator exhibits a predetermined relationship with a corresponding validity determination reference value. The validity determination reference values are complementarily maintained and integrally obtained through the sequential read process.

Abstract: The present invention provides methods for automatically assigning addresses to expanders in a computer I/O subsystem that is coupled to one or more host computers. The computer I/O subsystem includes one or more peripheral buses, a set of peripheral devices, and a set of expanders with each expander being arranged to couple a pair of peripheral buses. The peripheral devices are coupled to the peripheral buses. In this configuration, a host computer selects a peripheral device as a target device and writes an address data pattern to the selected target device. The host computer then selects the target device and reads the address data pattern from the target device. Unique addresses are then assigned to one or more expanders coupling the host computer and the target device starting from the address data pattern, preferably by incrementing the address data pattern.

Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.

Abstract: A data processing system is disclosed. The system includes a control command storage device, a data storage device, an address pointer, a multi-level signal decoder and a data processing unit. The control command storage device and the data storage device store the data to be processed in a multi-level data form. The address pointer is electrically connected to the control command storage device and the data storage device for pointing toward a first address of the control command storage device and a second address of the data storage device. The multi-level signal decoder is electrically connected to the control command storage device for decoding a control command stored in an n-level data form and read from the first address of the control command storage device, thereby delivering a control signal representing the corresponding control command.

Abstract: A data retrieval device capable of attaining a low power consumption while utilizing high speed retrieving characteristics of a CAM, wherein a plurality of rule data with determined priority is newly arranged in an order of the size and assigned to memory blocks in accordance with the order, information on the assigned data range is stored in a register, the rule data is rearranged again in the priority order in each memory block, a range comparator compares input retrieval data with a content held in the register and a memory block to be retrieved is specified by the result, and a block controller activates only the specified block at the time of retrieving and not activating other blocks, so that a power consumption at the tem of retrieving is reduced for that amount.

Abstract: A memory array portion, a connection circuit serving as an interface of the memory array portion and a signal wiring connecting the memory array portion to the connection circuit are provided. Mesh wirings comprising first and second wiring layers are provided on the memory array portion. The connection circuit is connected to a plurality of signal lines comprising a third wiring layer provided on the memory array portion, the connection circuit or the signal wiring, through an intermediate wiring comprising the second wiring layer. The region where the intermediate wiring is provide on the memory array portion or on the signal wiring, and the mesh wiring comprising the second wiring layer is not present on the region where the intermediate wiring is provided.

Abstract: Method and apparatus for managing operating system calls. In a computer system that includes a system vector and a first vector table, an alternative vector table is provided. The first vector table includes references to respective segments of operating system program code that are associated with operating system calls, and the alternative vector table includes references to one or more respective segments of wrapper program code associated with segments of operating, system program code. The system vector is set to reference the first vector table or the alternative vector table at selected times during execution of a user program. Thus, segments of operating system code are executed in response to operating system calls made when the system vector references the first vector table, and segments of code referenced in the alternative vector table are executed when the system vector references the alternative vector table.

Abstract: The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

Abstract: A data storage device that includes an array of resistive memory cells and a circuit that is electrically connected to the array. The resistive memory cells include magnetic random access memory cells that are electrically connected to diodes. The circuit is capable of applying a first voltage to some of the resistive memory cells in the array, a second voltage to other cells in the array, and a third voltage to yet other cells in the array. Also, a method of sensing the resistance state of a selected resistive memory cell using the circuit.