Abstract: A method (and system) for emulating a target system's memory addressing using a virtual-to-real memory mapping mechanism of a host multiprocessor system's operating system, includes inputting a target virtual memory address into a simulated page table to obtain a host virtual memory address. The target system is oblivious to the software it is running on.

Abstract: A method and system for promoting traces in an instruction processing circuit is disclosed. The method and system comprises determining if a current trace is promotable; and adding the current trace to a sequence buffer if the current trace is promotable. The current trace is marked as promoted and the current trace is marked as a first trace of a multi-block trace. The method and system includes determining if a next trace is promotable; adding the next trace to the sequence buffer if the next trace is promotable; and repeating the above until the next trace is not promotable and then adding the next trace to the sequence buffer if the next trace is not promotable.

Abstract: A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. A page is reserved in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid and contain the corresponding address of the reserved page.

Abstract: A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.

Abstract: A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.

Abstract: A system, method and computer-readable medium for updating an address translation table. In the method, a message indicating a physical memory location that corresponds to a virtual address is received from a processor. An I/O Memory Management Unit (IOMMU) is used to update an entry within the address translation table corresponding to the virtual address according to the indicated physical memory location.

Abstract: A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of contiguous page table entries may be cached using the larger memory page size in an entry of a translation lookaside buffer. The translation lookaside buffer may be a MIPS-like TLB in which multiple page table entries are cached in each TLB entry.

Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

Abstract: A system that, at a process checkpoint, pauses the process to copy the system state for the process and then copies pages of the process in memory to disk storage while the process continues to run. When a write to a page by the process is to occur that requires a translation from a virtual address to a physical address the write is intercepted. The page that is being modified is duplicated and then the process is allowed to modify the page and continue. The duplicate page is then stored as part of the checkpoint copy.

Abstract: Disclosed is a method implementable by a computer system for maintaining consistency between mirrors of a mirrored data volume. In one embodiment, the method includes the computer system generating first and second write transactions in response to the generation of transaction to write data to a mirrored data volume. The first and second write transactions comprise first and second tags, respectively. The first and second tags relate the first write transaction to the second write transaction. In one embodiment, the first and second tags are identical. After the first and second write transactions are generated, the computer system transmits the first and second write transactions to first and second storage subsystems, respectively. In one embodiment, the first and second storage subsystems store or are configured to store respective mirrors of the data volume.

Abstract: A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system memory and the microprocessor. The microprocessor also includes a stream prefetch unit that generates a plurality of prefetch requests to prefetch the data stream from the system memory into the microprocessor. The prefetch requests specify the stream prefetch priority. The microprocessor also includes a bus interface unit (BIU) that generates transaction requests on the bus to transfer data between the system memory and the microprocessor in response to the load/store requests and the prefetch requests. The BIU prioritizes the bus transaction requests for the prefetch requests relative to the bus transaction requests for the load/store requests based on the stream prefetch priority.

Abstract: Scalable session management is achieved by generating a cookie that includes an encrypted session key and encrypted cookie data. The cookie data is encrypted using the session key. The session key is then signed and encrypted using one or more public/private key pairs. The encrypted session key can be decrypted and verified using the same private/public key pair(s). Once verified, the decrypted session key can then be used to decrypt and verify the encrypted cookie data. A first server having the private/public key pair(s) may generate the cookie using a randomly generated session key. A second server having the same private/public key pair(s) may decrypt and verify the cookie even if the session key is not initially installed on the second server. A session key cache may be used to provide session key lookup to save public/private key operations on the servers.

Abstract: An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Abstract: A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receives a request for the first sub-page and in response to such a request, the DMMU instructs a pre-fetch engine to pre-fetch at least the second sub-page if the number of detected sequential accesses equals or exceeds a predetermined value.

Abstract: A method and apparatus are provided for supplying a reliable and maintainable operating system in a net-booted environment. According to one embodiment, a network computer (NC) client boots from a boot image provided by an NC server. The boot image includes information identifying the location of one or more system volumes on the NC server that contain operating system software. In response to an attempt to modify the contents of the one or more system volumes, the NC client causes information identifying the modification to be recorded on the NC server separate from the one or more system volumes in a storage area associated with the NC client.

Abstract: To avoid the need for storing a tree quota identifier attribute for every file in a quota tree, a tree quota identifier is included in the file handle returned by the file server to a client in response to a directory lookup request. The file server discovers that the file is in a quota tree when searching along a path specified by the file pathname and finding a directory having a tree quota identifier. The file server responds to a client request for changing the storage resources used by the file by inspecting the file handle and upon finding the tree quota identifier in the file handle, using the tree quota identifier to index a tree quota database to find usage and limits for the tree quota. The file server checks the limits against any increase in the storage resources for the file, and updates the usage.

Abstract: A message memory (1) with a flexible association between the message-object memories of the message memory (2) and the segments of a physical memory (3). The association is made through configuration, wherein one or more memory segments form a cluster as a function of the length of the message content to be stored.

Abstract: In one embodiment, the invention comprises a flash-media controller used for writing new data from an external system to a local flash-memory device. The newly written data may replace old data previously written to the flash-memory device, and may be written directly to unused locations within the flash-memory device. The flash-media controller may comprise a table of block descriptors and sector descriptors used to track specified characteristics of each block and sector of the flash-memory device, thereby allowing for write sequences to non-contiguous sectors within a block. Accordingly, copy operations may be deferred under the expectation that they will eventually become unnecessary, thereby designating old data as having become stale.

Abstract: A memory system includes a nonvolatile semiconductor memory and a controller which controls the semiconductor memory, the memory system being inserted into the host device. The host device further includes a file management system which allocates a cluster defined in a FAT file system to write data and manages the data allocated to the cluster by using management data including a file allocation table defined in the FAT file system and a directory entry. The directory entry includes a root directory entry serving as entry information of a root directory of an uppermost layer and a sub-directory entry serving as entry information of a sub-directory belonging to the root directory. The file system allocates the plurality of clusters in a predetermined range in which addresses are serial to the management data.

Abstract: A method for page random write and read in blocks of flash memory is disclosed. The data could be random written in the pages of block. The pages would be arranged when the block was filled with data, so as to prevent from data copied and erased repeatedly. Present invention would reduce the data read/write time and increase the life-span of flash memory.

Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

Abstract: Systems, methods and computer program products for improving data stream prefetching in a microprocessor are described herein.

Abstract: The present invention is to provide a method of specifying access sequence of a storage device, wherein queues with different priority are created in the storage device for recording access requests from at least one server at the front-end of the storage device to manage the access operation, and are recorded corresponding to the front-end servers and the priority thereof respectively via a priority table. When the front-end server makes an access request, the request will be added to the corresponding queue according to the source front-end server, and each queue will be processed according to the priority thereof. The maximum workload of the access request processed every single time of each queue is set respectively. Thus, the access requests of the queues with higher priority will be processed within a shorter time.

Abstract: A technique to speculatively assign a memory attribute. More specifically, embodiments of the invention include an architecture to assign and issue a speculative memory attribute based on a plurality of translation look-aside buffer (TLB) page attributes concurrently with the determination of the correct memory attribute, such that, in at least one case, determination of the correct memory attribute does not impact performance of a system in which at least one embodiment of the invention is included.

Abstract: A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer indicates the change in a set data structure, such as a data array, in memory that is shared by the producer and a consumer. There may be multiple producers and multiple consumers and each producer/consumer pair has a separate channel. At coherency events, at which incoherencies between the primary data and the secondary data should be removed, consumers read the channels to determine the changes, and update the secondary data accordingly. The system may be a multiprocessor virtual computer system, the actor may be a guest operating system, and the producers and consumers may be subsystems within a virtual machine monitor, wherein each subsystem exports a separate virtual central processing unit.

Abstract: A method according to one embodiment may include discovering at least one data block comprising logical block address information. The method may also include mapping logical block address information from a first domain into a second domain. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing access to said memory (EM). Furthermore, access control means (A) are provided for addressing said memory (EM) so as to operate said register memory sections as shift registers and to map shift register accesses of the at least one access port (P1 to PZ) to predetermined addresses in the global address space of the memory (EM). In this way, it is possible to combine a plurality of FIFO memories in a single addressable memory device. This implementation is favourable in view of power consumption and area. Furthermore, by introducing a buffer memory, a multi-port memory device can be replaced by a single-port memory device of the same capacity. This advanced implementation also provides a reduced cycle and access time.

Abstract: A method and system for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device using a storage controller is provided. The storage controller includes, a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.

Abstract: Coherent memory copy logic is operative to copy data from a source memory location to a destination memory location and duplicate a write request to a source memory region to produce a duplicated write request. Coherent memory copy logic is also operative to execute the duplicated write request to copy content from the external memory region to the destination memory region. Power to the source memory can then be reduced to save power while the internal memory is being used. Accordingly, a type of “hardware memory mover” does not require the use of any complex software synchronization and does not result in any service interruption during a memory move. The coherent memory copy logic reallocates the application memory space from, for example, external memory to internal memory within a chip in a manner that is transparent to the application software and the user. Corresponding methods are also set forth.

Abstract: In a particular embodiment, a system is disclosed that includes a controller to read data from and write data to a first storage medium. The controller is adapted to monitor logical block addresses (LBAs) of each read operation from the first storage medium and to selectively store files associated with the monitored LBAs that are less than a predetermined length at a second storage medium to enhance performance of applications associated with the LBAs.

Abstract: There is provided a storage system capable of handling a large amount of control data at low cost in high performance. The storage system includes a cache memory for temporarily storing data read/written between a host computer and a disk array, a CPU for making a control related to data transfer, and a local memory for storing control data utilized by the CPU. The disk array has a first user data storing area for storing user data and a control data storing area for storing all control data. A control unit has a virtualization unit for allocating a memory space of the control data storing area to a virtual address accessible from the CPU, reading the control data specified by the virtual address to a physical address of the local memory, and transferring the control data to the CPU.

Abstract: Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test.

Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

Abstract: A network switching device that prevents its shared buffer from suffering a blocking problem, while achieving a higher memory use efficiency in buffering variable-length packets. Every received packet is divided into one or more fixed-length data blocks and supplied to the buffer. Under the control of a buffer controller, a transmit queue is created to store up to a fixed number of data blocks for each different destination network, and the data blocks written in the buffer are registered with a transmit queue corresponding to a given destination. The linkage between data blocks in each packet, as well as the linkage between packets in each transmit queue, is managed as a linked list structure based on the locations of data blocks in the buffer.

Abstract: A method and system are disclosed for using a distributable virtual address space. According to an exemplary embodiment, a method for using a distributable virtual address space includes providing a distributable virtual address space shared between a plurality of network nodes, the distributable virtual address space including a virtual address mapped to a first physical memory location of a first network node of the plurality of network nodes, wherein the first physical memory location is accessible by a first processor of the first network node when processing a first machine code instruction using the virtual address. The method also includes remapping the virtual address to a second physical memory location of a second network node of the plurality of network nodes, wherein the second physical memory location is accessible by a second processor of the second network node when processing a second machine code instruction using the virtual address.

Abstract: A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.

Abstract: In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory system of a computer system that includes the IOMMU. The control logic is configured to translate an I/O device-generated memory request using the translation data. The translation data includes a type field indicating one or more attributes of the translation, and the control logic is configured to control the translation responsive to the type field.

Abstract: A filer converts a traditional volume to a flexible volume by: creating an aggregate on storage devices other than the storage devices of the traditional volume; on the aggregate, creating a flexible volume large enough to store metadata describing files residing on the traditional volume; on the flexible volume, creating metadata structures that describe the files of the traditional volume, except that the metadata indicates that data blocks and indirect blocks are absent and must be fetched from another location. As the filer handles I/O requests directed to the flexible volume, the filer calculates physical volume block number (PVBN) addresses where the requested blocks would be located in the aggregate and replaces the absent pointers with the calculated addresses. After the absent pointers have been replaced, the filer adds the storage devices of the traditional volume.

Abstract: A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run on either or both processors. A synchronization unit coupled to the first and second processors also may be provided to synchronize the processors. Further still, a translation lookaside buffer may be included that is shared between the processors. Each entry in the translation lookaside buffer (“TLB”) may include a task identifier to permit the operating system or middle layer software to selectively flush only some of the TLB entries (e.g., the entries pertaining to only one of the processors).

Abstract: A mechanism is provided for efficiently managing the operation of a translation buffer. The mechanism is utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache. A software pre-load mechanism may be provided for preloading a translation look aside buffer (TLB) via a hardware implemented controller. Following preloading of the TLB, control of accessing the TLB may be handed over to the hardware implemented controller. Upon an application context switch operation, the software preload mechanism may be utilized again to preload the TLB with new translation information for the newly active application instance.

Abstract: A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In the micro TLB, a TLB virtual address [63:13] and a TLB absolute address [46:13] are registered in a correlated manner. With such configuration, when registering an address translation pair in the micro TLB, the calculator chops the address translation pair to a page size of a first size or a fourth size to register it in the micro TLB. Upon receiving an address translation request, the calculator searches for an address corresponding to the page size of the first size or the fourth size registered in the micro TLB, so that address comparison conditions can be reduced, enabling to improve a processing performance.

Abstract: An integrated circuit (IC) module allows volatile data generated by applications to be stored within volatile data files in the volatile memory. A file system tracks the location of all data files as residing in either volatile memory or nonvolatile memory and facilitates access to the volatile data files in volatile memory in a similar manner to accessing nonvolatile data files in nonvolatile memory. The file system exposes a set of application program interfaces (APIs) to allow applications to access the data files. The same APIs are used to access both volatile data files and nonvolatile data files. When an application requests access to a data file, the file system initially determines whether the application is authorized to gain access to the data file. If it is, the file system next determines whether the data file resides in volatile memory or nonvolatile memory. Once the memory region is identified, the file system identifies the physical location of the data file.

Abstract: Various technologies and techniques are disclosed for concurrently performing address translation data lookups for use by an emulator. On a first thread, a first lookup is performed for address translation data for use by an emulator. On a second thread, a second lookup for the address translation data is concurrently and speculatively performed. The address translation data from a successful lookup from either the first lookup or the second lookup is used to map a simulated physical address to a virtual address of the emulator. For example, the first thread can perform a translation lookaside buffer lookup while the second thread concurrently and speculatively performs a page table entry lookup for the address translation data.

Abstract: A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management system wherein there is a tendency that lower logic addresses are used frequently like the MS-DOS is adopted, physical blocks of a flash memory are used in an averaged fashion and the life of the flash memory can be elongated thereby.

Abstract: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

Abstract: A system and method for synchronizing translation lookaside buffer (TLB) access in a multithread processor is disclosed. When a first exception is found while searching the TLB, the exception is handled. While the exception is handled, thread processors are restricted from requesting the handling of any other exception.

Abstract: The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.

Abstract: A data processor operable to process data said data processor comprising: a set associative cache divided into a plurality of cache ways and operable to store data processed by said data processor; a buffer operable to store a table comprising a plurality of mappings of pages of virtual addresses to pages of physical addresses for said data processor; a data store comprising a plurality of data entries each operable to store data for identifying an address of a memory location for each of a plurality of recent cache accesses, each of said plurality of data entries comprising a page index indicating a page in an address space, offset data indicating a location within said page and cache way data identifying a cache way of a cache storage location accessed by said cache access; wherein said data processor is operable in response to a cache access request comprising a virtual address indicating a memory location to access said table and said data store to determine whether said cache access request is to one of

Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.