Abstract: A system and method are disclosed for utilizing compression in database caches to facilitate access to database information. In contrast with applying compression to the database that is stored on disk, the present invention achieves performance advantages by using compression within the main memory database cache used by a database management system to manage data transfers to and from a physical database file stored on a storage system or stored on a networked attached device or node. The disclosed system and method thereby provide a significant technical advantage by increasing the effective database cache size. And this effective increase in database cache size can greatly enhance the operations-per-second capability of a database management system by reducing unnecessary disk or network accesses thereby reducing data access times.

Abstract: A processor may include a local addressable memory, e.g., an SRAM, in parallel with a local cache at the highest level of the memory hierarchy, e.g., Level 1 (L1) memory. A local memory controller may handle accesses to L1 memory. The local memory controller may determine the page which includes the requested memory location and examine a page descriptor, e.g., an L1 SRAM bit, to determine if the page is in local memory. The local memory controller routes the access to the local addressable memory or the local cache depending on the state of the L1 SRAM bit.

Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

Abstract: A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are performed using the Sequential-Access Read Ahead values set by the user. When low memory is detected, the system either turns off Sequential-Access Read Ahead operations or decreases the maximum page ahead (maxpgahead) value based upon whether the amount of free space is simply low or has reached a critically low level. The altered VMM Sequential-Access Read Ahead state remains in effect until enough free space is available so that normal VMM Sequential-Access Read Ahead operations can be performed (at which point the altered Sequential-Access Read Ahead values are reset to their original levels).

Abstract: A data processing system includes at least one system processor, chipset core logic, main memory to store computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized real memory pages, while the operating system operates on larger, second-sized virtual memory pages. In an embodiment GART driver software maps each virtual page to Z continuous or non-contiguous real pages by filling up the GART with Z entries per virtual page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a target address, corresponding to an address within a virtual page, issuing from a processor into a second address, corresponding to a base address of a real page in main memory. Also described are an integrated circuit and a computer-readable medium to map memory pages of disparate sizes.

Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Abstract: A searching system allowing high-speed data searching and operation is disclosed. A search table is provided which stores a copy of an entry that has been retrieved from a database to retrievably store a plurality of retrieved entries. Further, an address pointer table is provided which stores a list of retrieved entries which are linked from a leading one to a bottom one. A search processor can access a plurality of retrieved entries by referring to the list stored in the address pointer table so as to be consistent with a corresponding entry stored in the database when the corresponding entry has been updated.

Abstract: A system and method for encoding page size information has been described herein. In one embodiment, the method includes determining whether a virtual address is stored in a translation lookaside buffer (TLB), the TLB including a plurality of entries, wherein the entries include a minimum virtual page number bit string and a variable bit string. In one embodiment the method also includes determining whether the first bit string matches the minimum virtual page number bit string of one of the entries. In one embodiment, if the first bit string matches the minimum virtual page number bit string of one of the entries, the method includes decoding a page size stored in the variable portion of the matching entry and a 1-bit field associated with the matching entry, wherein the decoding determines a set of bits of the variable bit string.

Abstract: A hash table for a collection of data items includes a set of hash buckets, each hash bucket being associated with a subset of the collection of data items, and a set of properties entries in each of the hash buckets. Each properties entry includes a pointer to an associated data item in the subset associated with the bucket and a set of representative values identifying the associated data item. A hash table can also include bucket groups defining a second level hash table to permit resizing of the hash table.

Abstract: A translation look-aside buffer (TLB) has lockable entries. A number of entries to lock may be determined by counting unique page access instances during an active period of a process, determining a value of a page usage metric for the process, and comparing the value of the page usage metric to values of page usage metrics for other processes. The page usage metric may consider many different factors, including the amount of time a process is active, a frequency of invocation of the process, and a priority level of a process.

Abstract: A flash driver tracks data stored in a flash memory device through the use of logical-to-physical sector mapping. The mapping is stored in a data structure and allows data to be written into the next free physical sector in the flash memory medium. Write operations complete quickly, because there is no need to perform an erase operation in order to write new data on to the flash memory medium. Data loss due to power interruption during a write operation is also minimized by the described implementations. The logical-to-physical sector mapping stored in data structure is backed-up on the flash memory medium. In the event there is a catastrophic power interruption, logical-to-physical sector mapping can easily be reestablished by scanning the backed-up mapping in the flash memory medium. The backed-up information can be stored in a spare portion of a NAND or NOR flash memory medium.

Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

Abstract: A method and apparatus for reducing instruction ITLB accesses. In one embodiment, the method may comprise generating a next virtual fetch address corresponding to an instruction fetch request and determining whether a current physical address translation is valid for the next virtual fetch address in response to its generation, wherein the determination may comprise detecting a change in the virtual page number of the next virtual fetch address relative to a virtual page number of a current virtual fetch address. The method may further comprise activating an ITLB circuit in response to determining that the current physical address translation is not valid for the next virtual fetch address, and performing the instruction fetch using the current physical address translation without activating the ITLB circuit in response to determining that the current physical address translation is valid for said next virtual fetch address.

Abstract: A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and/or frequently used pages uncompressed in physical memory. The CMMU translates system addresses into physical addresses, and may manage the compression and/or decompression of data at the physical addresses as required. The CMMU may provide data to be compressed or decompressed to a compression/decompression engine. In some embodiments, the data to be compressed or decompressed may be provided to a plurality of compression/decompression engines that may be configured to operate in parallel. The CMMU may pass the resulting physical address to the system memory controller to access the physical memory. A CMMU may be integrated in a processor, a system memory controller or elsewhere within the system.

Abstract: The present invention discloses a network address forwarding table lookup apparatus and method for identifying a network address to determine a next hop address to which data packets having the network address should be forwarded. The apparatus comprises a memory storing a compression-trie forwarding table. The forwarding table has multiple level modules in a compression-trie structure. With the present invention, it is possible to achieve fast IP address lookup with a compact-sized compression-trie forwarding table.

Abstract: The present invention provides an optical disk drive, optical disk recording method, optical disk recording program and a recording medium having the optical disk recording method recorded therein, applicable to a DVD drive, for example, to permit recording of also a file of still pictures other than moving pictures with a sufficient extension of the recording ability of the optical disk. To this end, individual management information can be accessed via guide information for an extended file in consideration and an identification code CAT ID indicative of the type of the extended file and recording format CAT INFO TYPE of the management information are allocated to the extension-file guide information.

Abstract: Methods and apparatus for splitting a single logical block into two or more physical blocks are disclosed. According to one aspect of the present invention, a method for associating a plurality of physical blocks of a non-volatile memory with a logical block that includes of logical block elements involves grouping the logical block elements into at least a first logical set and a second logical set. Data associated with the first logical set is provided to a first physical block, and data associated with the second logical set is provided to a second physical block.

Abstract: The present invention provides an optical disk drive, optical disk recording method, optical disk recording program and a recording medium having the optical disk recording method recorded therein, applicable to a DVD drive, for example, to permit recording of also a file of still pictures other than moving pictures, thereby enabling more effective use of the information recording area of the optical disk and more quick search for desired data. To this end, the address of management information (DK) is identified with reference to a management table (TV) recorded in a fixed area on the optical disk, and a recording format is selected for the management information (DK) to be recorded in combination with an extension file (EF).

Abstract: A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

Abstract: An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to a different group, and means for assigning adjacent host addresses to different physical blocks belonging to the same virtual block. Thus, when a host computer issues a request to access the plurality of successive host addresses, the physical blocks to be accessed are different physical blocks. Since the physical blocks to be accessed can therefore operate independently, a series of operations can be performed in parallel.

Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

Abstract: A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.

Abstract: If a base register value, an index register value and a displacement value are given in the case of operand access, these values are inputted to an arithmetic unit to generate a correctly calculated logical address. Simultaneously, a logical address predicting unit predicts a logical address. An absolute address is predicted based on the predicted logical address by using an absolute address history table. Access to a cache memory (LBS) based on an absolute address is made using the predicted absolute address to obtain cache data. Then, the arithmetic unit calculates a correct absolute address using the correctly calculated address using a TLB and checks if the correct absolute address coincides with the predicted absolute address so as to perform result confirmation of the cache data read from the LBS. In the case of instruction fetch, similar processing is carried out except that the calculation of a logical address is not performed.

Abstract: A prefetch mechanism includes a prefetch predictor table coupled to a prefetch control. The prefetch predictor table may include a plurality of locations configured to store a plurality of entries each indicative of a stride between a respective pair of memory requests. Each of the plurality of entries may be stored in a respective one of the plurality of locations dependent upon a value of an earlier stride. The prefetch control may be configured to prefetch an address based upon a given one of the plurality of entries in the prefetch predictor table.

Abstract: A data processing system includes at least one system processor, chipset core logic, main memory to store computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized real memory pages, while the operating system operates on larger, second-sized virtual memory pages. In an embodiment GART driver software maps each virtual page to Z continuous or non-contiguous real pages by filling up the GART with Z entries per virtual page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a target address, corresponding to an address within a virtual page, issuing from a processor into a second address, corresponding to a base address of a real page in main memory. Also described are an integrated circuit and a computer-readable medium to map memory pages of disparate sizes.

Abstract: A data processing (10) includes memory management circuitry (14) which allows additional control over the physical address (83) and over the address attributes (84) which are provided for use by data processing system (10). One use of this additional control over the physical address (83) and over the address attributes (84) is to avoid address translation failure and unintended modification of cache (13) and memory (18) system state during debugging.

Abstract: A data transfer apparatus for simplifying a module structure for controlling a connected data recording apparatus and improving the processing efficiency. A control code issued by a common application module having a main purpose of check-out/check-in is made a control code corresponding to a device connected by a conversion module and transmitted via a device driver. Moreover, for example, a control code issued by a local application module having a main purpose of controlling processing depending on a device connected shares the aforementioned device driver. For example, the local application module issues a control code in a state matched with a control code format converted by the conversion module. Alternatively, the local application module issues a local control code by indicating issuance of a local control code of a format different from the control code format converted by the conversion module.

Abstract: A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation lookaside buffer (TLB) (300, 310(n)) of a memory management unit (MMU) and thereby access memory and devices. These resources can be instruction processors, coprocessors, DMA devices, etc. Each entry location in the TLB is filled during the normal course of action by a set of translated address entries (308, 309) along with qualifier fields (301, 302, 303) that are incorporated with each entry. Operations can be performed on the TLB that are qualified by the various qualifier fields. A command (360) is sent by an MMU manager to the control circuitry of the TLB (320) during the course of operation. Commands are sent as needed to flush (invalidate), lock or unlock selected entries within the TLB. Each entry in the TLB is accessed (362, 368) and the qualifier field specified by the operation command is evaluated (364).

Abstract: A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.

Abstract: A memory device with a nonvolatile memory and RAM for accessing the nonvolatile memory is generally provided with a table to convert a logical address to a physical address, however, in the invention, the table is divided to a first table on RAM and a second table on the nonvolatile memory. The first table converts specific bits of the logical address to a first physical address indicating a location of the second table. The second table converts the other bits of the logical address to a physical address of a representative page of pages contained in a storage area corresponding to the logical address. A unit operable to access data (a writing unit operable to, a reading unit operable to, and an erasing unit operable to) reaches a target physical address based on the logical address. Such configuration can reduce the capacity of each conversion table.

Abstract: A mechanism for enabling session information to be shared across multiple processes in a multi-process environment is disclosed. There is provided a shared persistent memory-mapped file in a file system, which is mapped to the memory space of each of the processes. This file is used by all of the processes to store session information. Because the memory space of each process is mapped to the shared file, each process is able to access and manipulate all of the sessions in the system. Thus, sessions are no longer maintained on a process-specific basis. Rather, they are maintained on a centralized, shared basis. As a result, different requests pertaining to the same session may be serviced by different server processes without any adverse effects. Each process will be able to access and manipulate all of the state information pertaining to that session. By enabling session information to be shared, this mechanism eliminates the session management errors experienced by the prior art.

Abstract: An external memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator.

Abstract: A computer system has physical pages of memory subject to access by input/output (“I/O”) devices, and a certain table with entries associating the physical pages with the I/O devices. Responsive to a request for data be moved from a first physical page to a second physical page, an entry is selected for the first physical page in the table. The selected entry indicates an association of the first physical page and one of the I/O devices. Arbitration is temporarily disabled for the selected I/O device so that I/O operations for the I/O device are temporarily disabled. Once arbitration is disabled for the device the data is moved from the first physical page to a second one of the physical pages and the entry is updated in the table to reflect a new association between the I/O device and the second physical page.

Abstract: A method of performing remote address translation in a multiprocessor system includes determining a connection descriptor and a virtual address at a local node, accessing a local connection table at the local node using the connection descriptor to produce a system node identifier for a remote node and a remote address space number, communicating the virtual address and remote address space number to the remote node, and translating the virtual address to a physical address at the remote node (qualified by the remote address space number). A user process running at the local node provides the connection descriptor and virtual address. The translation is performed by matching the virtual address and remote address space number with an entry of a translation-lookaside buffer (TLB) at the remote node. Performing the translation at the remote node reduces the amount of translation information needed at the local node for remote memory accesses.

Abstract: A remote translation mechanism for a multi-node system. One embodiment of the invention provides a method for remotely translating a virtual memory address into a physical memory address in a multi-node system. The method includes providing the virtual memory address at a source node, determining that the virtual memory address is to be sent to a remote node, sending the virtual memory address to the remote node, and translating the virtual memory address on the remote node into a physical memory address using a remote-translation table (RTT). The RTT contains translation information for an entire virtual memory address space associated with the remote node.

Abstract: Disclosed is a server farm or MetaServer environment in which thin servers or server appliances each include a programmable network interface card providing logic required for implementing service processor functions. The combined implementation of the network interface and service processor hardware and software substantially eliminates redundancies, which previously existed when both were separate components. Service processor functions that are provided on the programmable network interface card includes gathering sensor data about the hardware, forwarding alerts regarding hardware state, initiating shutdown and restart on command, and responding to operating system service processor inquiries and commands. Additionally, other low-level management and control functions are provided on the programmable network interface card. Also, in one embodiment, a re-partitioning of the functions between the service processor (or probes) and the network interface is provided.

Abstract: A system, method, and computer program product are disclosed for invalidating specified pretranslations maintained in a data processing system which maintains decentralized copies of pretranslations. A centralized mapping of virtual addresses to their associated physical addresses is established. The centralized mapping includes a listing of pretranslations of the virtual addresses to their associated physical addresses. Multiple lists of pretranslations are generated. Control of the lists may be passed from one entity to another, such that the lists are not owned by any particular entity. Each one of the lists includes a copy of pretranslations for virtual addresses. A particular one of the physical addresses is specified. Each list that includes a pretranslation of a virtual address to the specified physical addresses is located. The pretranslation of the virtual address to the specified physical address is then invalidated within each one of the lists.

Abstract: A software tool automatically places files and folders of a software program within segments of a DVD. The segments are defined by security placeholders, and the disposition of the placeholders is initially randomly determined, consistent with predefined rules. The placeholders are included on the disc to hinder unauthorized copying. A developer generally defines the order in which the files and folders are to be laid out, and the software tool automatically places the files and folders, filling successive segments and shifting the placeholders to accommodate files that will not fit in a current segment. However, any movement of the placeholders must be done by the tool and is only permitted if the new disposition of the placeholder is in accord with the predefined rules. A user can manually modify the automated layout, and in response, the files and folders are automatically shifted to accommodate the changes introduced by the user.

Abstract: A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A flash driver tracks data stored in a flash memory device through the use of logical-to-physical sector mapping. The mapping is stored in a data structure and allows data to be written into the next free physical sector in the flash memory medium. Write operations complete quickly, because there is no need to perform an erase operation in order to write new data on to the flash memory medium. Data loss due to power interruption during a write operation is also minimized by the described implementations. The logical-to-physical sector mapping stored in data structure is backed-up on the flash memory medium. In the event there is a catastrophic power interruption, logical-to-physical sector mapping can easily be reestablished by scanning the backed-up mapping in the flash memory medium. The backed-up information can be stored in a spare portion of a NAND or NOR flash memory medium.

Abstract: A data processing system that includes a mode/reserve bit utilized to dynamically change a processor's operating mode between a virtual addressing mode and a real addressing mode. Each address block includes a reserve bit that indicates whether real or virtual addressing is desired, and the reserve bit is assigned a value by the software application executing on the processor. The value of the reserve bit is dynamically set and signals the processor which operating mode is required for the particular address block. The selection of virtual or real addressing mode is determined by the particular application that is being executed by the processor. When the particular application process seeks increased performance rather than protection, the virtual operating mode is selected, allowing the application process to send the effective addresses directly to the OS and hypervisor. This is accomplished by setting the reserve bit to the value for virtual addressing mode.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the I/O subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: Disclosed is a method of managing memory to prevent an operating system from writing into user memory space, the method comprising providing a translation look-aside buffer (TLB) for storing TLB entries, each said TLB entry comprising a virtual address of a page in system memory space, a real address of said page, a flag entry for storing a value F indicating whether said page is a user page in said user memory space, providing a space recovery mode register comprising a mode entry for storing a value E indicating whether the system is in a normal mode or in a space recovery mode, said value of E set to said space recovery mode when available free user space fall below a predetermined threshold value, and for each said TLB entry, designating said page in system memory space as read-only when F=0 and E=0. An alternative embodiment is also disclosed wherein no modifications to memory structures are required.

Abstract: A method and apparatus for input/output virtual address translation and validation assigns a range of memory to a device driver for its exclusive use. The device driver invokes system functionality for receiving a logical address and outputting a physical address having a length greater than the logical address. Another feature of the invention is a computer system providing input/output virtual address translation and validation for at least one peripheral device. In one embodiment, the computer system includes a scatter-gather table, an input/output virtual address cache memory associated with at least one peripheral device, and at least one device driver. In a further embodiment, the input/output virtual address cache memory includes an address validation cache and an address translation cache.

Abstract: In an information processsing unit with key controlled protection, since it takes a long time to fetch a storage key from key storage, an instruction and computation unit of a CPU receives data from a memory control unit of the CPU before a key is received, and then the transferred storage key is checked.

Abstract: A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is able to address a second space of the hardware memory using second identifiers initiates I/O requests directed to a device that is able to address a different, first memory space using first identifiers, which are represented using a second number of address bits. The second identifiers are initially mapped into the second memory space, but for any I/O request that meets a remapping criterion, the corresponding second identifier is remapped to one of the first identifiers that identifies a portion of the memory in the first memory space. The second space is different from the first space and the second number of address bits is greater less than the first number of address bits.

Abstract: A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a plurality of entries. Each entry includes a plurality of entry items. Each entry item identifies one of the memories. A first logical address is received. The first logical address includes a plurality of address bits. The plurality of address bits includes a first set of address bits corresponding to a first set of entries in the at least one map table. A first entry in the first set of entries is identified based on the first set and a second set of the address bits. A first entry item in the first entry is identified based on a third set of the address bits. The memory identified by the first entry item is accessed.

Abstract: A system, method, and computer program product are disclosed for migrating real pages. A real page of data is established. Virtual addresses that are associated with the real addresses that are included within the real page are generated. A mapping table is established that includes mappings of the virtual addresses to these real addresses. A routine is executed that accesses the mapping table to obtain the mappings of virtual addresses to real addresses. The routine utilizes the virtual addresses to access the data that is stored in the real page. While the routine is executing, the data is migrated from the real page to a new real page. The mapping table is then updated while the routine is executing so that the routine utilizes the same virtual addresses to access the data that is now stored in the new real page. Execution of the routine continues while the mapping table is being updated.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A computer system including a processor, an object cache operatively connected to the processor, a memory, and a translator interposed between the object cache and the memory, wherein the translator maps an object address to a physical address within the memory.