Abstract: A data processing system providing high performance two-dimensional and three-dimensional graphics includes at least one system processor, chipset core logic, a graphics processor, main memory storing computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized memory pages, while the operating system operates on larger, second-sized memory pages. In one embodiment GART driver software maps each second-sized page to Z first-sized pages by filling up the GART with Z entries per second-sized page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a first page number, corresponding to a first-sized page, issuing from a system processor into a second page number, corresponding to a second-sized page, and a page offset within the second-sized page.

Abstract: A computer system is provided with a memory management unit (MMU) utilizing a translation look-aside buffer (TLB) arrangement. The computer system includes a bus, a unified cache memory, a main memory, a processor, and a memory controller. The TLB is configured for storing code and/or data. The main memory is coupled to the bus. The main memory contains descriptor tables for mapping virtual-to-physical address translations within a virtual memory system. The processor is coupled to the bus and the unified cache memory. The processor is configured to communicate and sequentially move through the main memory to retrieve a line of information from the main memory for storage in the unified cache memory. The cache is configured for storing the most recently retrieved code and data from main memory. The memory controller is coupled between the bus and the main memory.

Abstract: A data processing system and a data processor in which the control information for controlling an external device, especially, a device having a PCMCIA interface is stored in an address translation circuit for translating a first address outputted from a CPU to a second address in association with the first or second address.

Abstract: A pointer structure on the storage unit of a non-volatile memory maintains a correspondence between the physical and logical address. The controller and storage unit transfer data on the basis of logical sector addresses with the conversion between the physical and logical addresses being performed on the storage unit. The pointer contains a correspondence between a logical sector address and the physical address of current data as well as maintaining one or more previous correspondences between the logical address and the physical addresses at which old data is stored. New and old data can be kept in parallel up to a certain point. When combined with background erase, performance is improved. In an exemplary embodiment, the pointer structure is one or more independent non-volatile sub-arrays, each with its own row decoder.

Abstract: In a computing system having swappable and non-swappable address spaces, wherein the computing system includes an operating system that includes a Real Storage Manager (RSM), a Systems Resource Manager (SRM) and a Region Control Task (RCT), a method for recovering swappable fixed non-preferred memory is provided which includes receiving a request from the operating system to configure an area of real memory to create an intercepted swappable address space, wherein the intercepted swappable address space includes a flagged fixed frame element identified for configuration, examining the intercepted swappable address space so as to determine if the intercepted swappable address space will remain swappable, requesting the SRM to coordinate the swapping process, quiescing the intercepted address space, generating a first return code responsive to the intercepted swappable address space remaining swappable, communicating the first return code to the RCT so as to cause the RCT to respond to the first return code, in

Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.

Abstract: A memory system includes a memory array for storing a plurality of data elements, the memory array comprising a plurality of memory blocks. In one embodiment, the data element are tag string data. The memory system may also include a comparator unit coupled to receive a memory block output and an input signal, wherein when the memory block output matches the input signal, the memory system transmits a match signal and a code word on a result bus. In one embodiment, data elements are stored as fragments in different portions of the memory array. The input signal may be received as fragments and compared to the data elements over different time periods. In one embodiment, the present invention provides a memory lookup system and method that supports multiple protocols.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: Disclosed is a disk system for controlling divided areas of a cache memory. Identification information that denotes whether data to be accessed is user data or meta data is added to each I/O command issued from a CPU. A disk controller, when receiving such an I/O command, selects a target virtual area from among a plurality of virtual areas set in the cache memory according to the identification information. When new data is to be stored in the cache memory upon the execution of the I/O command, the disk controller records the number of the selected virtual area in the cache memory in correspondence with the new data. A cache data replacement is executed independently for each cache area, thereby a predetermined upper limit size of each cache memory area can be kept.

Abstract: A method and apparatus is used select a multiplication constant for addressing a storage location with reduced processing requirements. The selection includes receiving a multiplication constant for use in an arithmetic operation to address a storage location, determining an upper limit multiplication constant compared with the received multiplication constant, counting the number of zero digits for each binary value contained in the range of binary values greater than the multiplication constant value and less than or equal to the upper limit multiplication constant and selecting the binary value from the range having the greatest number of zero digits as the modified multiplication constant.

Abstract: A system for optimizing data storage and retrieval by an audio/video system using a number of different tables is disclosed. According to one aspect of the system, the system includes two different types of hierarchical file allocation tables (HFATs), a contiguous space table, a track table and a list table. The two different types of HFATs are a 0th order HFAT and a 1st order HFAT. Each of the two types of HFATs contains a number of entries. Each 0th order HFAT entry corresponds to a specific disk block and each 1st order HFAT entry corresponds to a specific subdivision within a subdivided disk block. A 0th order HFAT entry and an 1st order HFAT entry is linkable to one another to allow disk blocks and subdivisions which make up a file to be identified. The contiguous space table is used to store information relating to the location and availability of contiguous spaces or disk blocks. The track table contains a number of records. Each record, in turn, contains various track, HMSF and descriptor information.

Abstract: An object-based multi-threaded computing system has a cyclic garbage collection strategy and includes an object locking system having (i) a first mode in which access by a single thread without contention to an object is controlled by a monitor internal to said object, and (ii) a second mode in which access by multiple threads with contention to said object is controlled by a monitor external to said object. For any given object a transition from the first mode to the second mode is termed inflation, and a transition from the second mode to the first mode is termed deflation. Responsive to the start of a period of contention for an object in said first mode, the object is inflated to the second mode, and an inflation rate counter is incremented. After the period of contention has concluded the value of the inflation rate counter is compared against a predetermined value in order to determine whether or not to deflate the object. The inflation rate counter is reset at every garbage collection cycle.

Abstract: A behavioral memory mechanism for a data processing system is disclosed. The data processing system includes a processor, a real memory, a behavioral address generator, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The behavioral address generator generates a behavioral virtual memory address associated with the behavioral virtual memory region. The address translator translates the behavioral virtual memory address to a real address associated with the real memory.

Abstract: A page table method that allows programming of flash memory without corrupting the translation lookaside buffers is described. Flash memory is used to store page tables and other data. In one embodiment of the invention, the page tables are shadowed in random access memory after system bootup to prevent the system from crashing in the event the page tables are accessed while the read only memory is being programmed. In a second embodiment of the invention, the translation lookaside buffers are pre-charged.

Abstract: A digital data storage system comprises a storage device, a descriptor memory and a control device. The storage device stores a series of records, the records being organized in a plurality of tracks, each track being associated with one of a plurality of cylinders. The descriptor memory stores a descriptor associated with storage device. The descriptor contains selected information relating to the records stored by the at least one storage device. Each descriptor includes a plurality of cylinder portions each configured to store selected information relating to a respective one of the cylinders in the storage device. Each cylinder portion, in turn, includes a plurality of track descriptors each configured to store selected information relating to a respective one of the tracks in the respective cylinder. The storage device also stores the descriptor associated therewith, the cylinder portions of the descriptor being augmented with additional information relating to the respective ones of the cylinders.

Abstract: A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: An operation method for controlling memorized page access attribute of the memory and its structure, particularly a control method for a low-level driver or system chipset to perform the control of read and write to partial areas of the memory, mainly by means of making use of buffer memory to configure procedures to perform operation area configuration of memory, and by means of practical operation procedures to confirm the operation mode of the said area, to further control said region in such modes as read only, write only, write once, read once, etc., to prevent programs which have been loaded into the memory and will be executed and passwords which have been verified from being intruded by illegal hacker, virus, etc, to provide a common protective design to the system safety.

Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.

Abstract: The present invention provides a virtual storage system that generally stores uses larger segmentations, but divides large segments into smaller sub-segments during data movement operations. The present invention provides a method and system having this hierarchy of segment sizes, namely a large segment for the normal case, while breaking the large segment into single disk blocks during data movement. The mapping has large segments except for those segments undergoing data movement. For those segments, it would be desirable to have the smallest segment size possible, namely, a single disk block. In this way, the administration costs are generally low, but latencies caused by the movement of large data blocks are avoided.

Abstract: A processor includes a translation look-aside buffer (TLB) that relates virtual page addresses to both physical page addresses and main-memory addresses. If the processor references a virtual page address in the TLB for which there is no corresponding information in cache, the processor passes the main-memory address directly to main memory, avoiding the latency normally associated with systems that translate a physical page address to a main-memory address before accessing information from main memory.

Abstract: A recoverable I/O request processor includes computer-executable instructions for processing I/O requests, such as requests to send or receive data through a network. The recoverable I/O request processor translates virtual memory addresses to physical memory addresses utilizing translation tables local to an I/O device. If a local translation fails, the recoverable I/O request processor requests virtual address mapping information from the operating system.

Abstract: A data processing system that includes a mode/reserve bit utilized to dynamically change a processor's operating mode between a virtual addressing mode and a real addressing mode. Each address block includes a reserve bit that indicates whether real or virtual addressing is desired, and the reserve bit is assigned a value by the software application executing on the processor. The value of the reserve bit is dynamically set and signals the processor which operating mode is required for the particular address block. The selection of virtual or real addressing mode is determined by the particular application that is being executed by the processor. When the particular application process seeks increased performance rather than protection, the virtual operating mode is selected, allowing the application process to send the effective addresses directly to the OS and hypervisor. This is accomplished by setting the reserve bit to the value for virtual addressing mode.

Abstract: A data storage subsystem including a storage disk array employing dynamic data striping. A data storage subsystem includes a plurality of storage devices configured in an array and a storage controller coupled to the storage devices. The storage controller is configured to store a first stripe of data as a plurality of data stripe units across the plurality of storage devices. The plurality of data stripe units includes a plurality of data blocks and a parity block which is calculated for the plurality of data blocks. The storage controller is further configured to store a second stripe of data as a plurality of data stripe units across the storage devices. The second plurality of data stripe units includes another plurality of data blocks, which is different in number than the first plurality of data blocks, and a second parity block calculated for the second plurality of data blocks. Furthermore, the second plurality of data blocks may be a modified subset of the first plurality of data blocks.

Abstract: An apparatus and method provide simultaneous local and global addressing capabilities. A global address space is defined that may be accessed by all processes. In addition, each process has a local address space that is local (and therefore available) only to that process. An address translation mechanism is implemented, preferably in hardware, to compare an address to defined addresses for local and global addressing and to detect when a virtual address computation result would go outside a boundary for the appropriate addressing scheme. The address translation mechanism maps a virtual address to a corresponding physical address, and uses different criteria depending on whether the address is local or global.

Abstract: A system for recording data to a disc shaped record medium. The data is recorded according to a universal disc format employing a hierarchical file system, and data within the hierarchical structure is referenced using pointer information. The pointer information includes a file identifier descriptor and a file entry and is recorded such that the pointer information and its corresponding substantive data are stored at successive addresses.

Abstract: A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory region. Requests for memory are mapped at least once, for example from virtual to physical page numbers. The I/O requests are conditionally remapped to pages in the first region as a function of how often they are involved in the I/O operations and would normally otherwise need to be copied. Remapping may also be made conditional on a function of availability of memory in the first region. In a preferred embodiment of the invention, the I/O requests are initiated by a subsystem within a virtual machine, which runs via an intermediate software layer such as a virtual machine monitor on an underlying hardware and software platform. A typical application of the invention is DMA.

Abstract: A method for memory management in execution of a program by a computer having a memory includes setting an attribute of an unallocated unit of the memory in preparation for allocation of the memory in the unit, and allocating respective portions of the memory in the unit to data objects to be held in a heap created by the program. Responsive to the attribute that is set on the allocated portions of the memory, the data objects in the heap are traced, so as to mark the data objects that are reachable at a given stage in the program. The heap is then swept so as to free the memory that is allocated to data objects that are not marked as reachable, for reallocation to new data objects.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up the data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A system for moving physically stored data in a distributed, virtualized storage network is disclosed. A group of data sets is written to a first storage device as part of a write operation such as migration. A plurality of storage devices partially filled with data are designated as substitutes. The write operation to the first storage device is suspended upon receiving a request to read a data set stored in the first storage device, such as occurs in a recall operation. A second storage device is then selected from the plurality of substitute storage devices. The write operation is continued by writing data sets from the group of data sets included in the write operation that were not written to the first storage device to the selected second storage device. The requested data is then read from the first storage device.

Abstract: Methods and apparatus are disclosed for moving logical entities from one storage element to another storage element. Movement of the logical entity may be accomplished by using a logical volume identifier, which is unique to the logical volume with respect to other logical volumes stored on the storage elements. The movement may be accomplished by changing an entry for the physical storage location corresponding to the unique logical volume identifier.

Abstract: A translation lookaside buffer mechanism 10 is described incorporating a set associative translation lookaside buffer 16 operating in parallel with a fully associative translation lookaside buffer 18. Lockdown entries are stored within the fully associative translation lookaside buffer 18 and non-lockdown entries are stored within the set associative translation lookaside buffer 16. Victim selection for the fully associative translation lookaside buffer 18 is performed using a control register 50 within a coprocessor 12 which is set under operating system software control.

Abstract: A system and method are provided for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART). In the system and method, a translation look-aside buffer cache has a plurality of translation look-aside buffer entries. Each translation look-aside buffer entry is operable to buffer information which may be accessed for use in translating a virtual address into a physical address. A least recently used pointer circuit is operable to point to a translation look-aside buffer entry buffering information least recently used in the translation look-aside buffer cache. During operation, updates to the least recently used pointer circuit may be pipelined with corresponding accesses to the translation look-aside buffer cache.

Abstract: In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to tables entries in which the entries are addressed after adding a plurality of address parts wherein the plurality is two (2) or (3). Particularly, a smaller and/or faster adder is used having, for example, only n=2 ports in the time critical path. In order to make the exact address calculation, during array accesses, a multiplexor is implemented to decide, after the TLB arrays are accessed for preselection, which of a plurality of possible entries has to be taken.

Abstract: An apparatus and method for reducing power consumption in a processor front end are provided. The processor includes an instruction cache, a TLB, and a branch predictor. For sequential code execution, the instruction cache is disabled unless the next instruction fetch will cross a cache line boundary, thus reducing unnecessary accesses to the instruction cache. The TLB is disabled unless the next instruction fetch will cross a page boundary, thus reducing unnecessary TLB look-ups. For code branching, the branch predictor is configured to include, for each target address, an indication of whether the target address is in the same page as the corresponding branch address. When a branch occurs so as to cause access to a given entry in the branch predictor, the TLB is disabled if the target address is in the same page as the branch address.

Abstract: Memory corruption can be suppressed. When data stored in a random access area are read, the read data (physical block) are retrieved by a logic block number and newest data are read by referring to an incremental counter of data having that logic block number. When data are stored in the random access area, the incremental counter and the logic block number of data already stored in the random access area are referred and a physical block set to be unnecessary is set to a writer buffer, and then the data are written to this write buffer.

Abstract: A method for adding compressed page tables to an operating system is disclosed. An embodiment provides for a method in which a single entity, for example, an operating system has control of the compression and decompression of data and where the data is stored. When a data access is desired, the method accesses a table specifying the physical memory location of uncompressed data to determine if specified data is in uncompressed memory. The method of this embodiment accesses a table specifying the physical memory location of data in compressed memory to determine if the data is in the compressed memory. The method also access a page directory table to determine the location of the data in virtual memory in the event of a page fault. Then, this embodiment accesses the data based on the table look-up results.

Abstract: A system and method for extracting data from a protected region of memory loads at least a first part of extraction code into physical memory and, thereafter, activates a memory mapping facility that maps a real memory onto the physical memory and prevents programs from accessing a protected memory region of the physical memory. At least a second part of the extraction code is then loaded into the virtual memory utilizing the memory mapping facility. The extraction code is then executed to deactivate the memory mapping facility and to copy data from the protected memory region to a second physical memory region, such that reactivating the memory mapping facility will cause a real memory region to be mapped onto the second physical memory region.

Abstract: A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copied to local memory space of a node such that accesses to the data may be performed locally rather than globally. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, multiple pages of the address space are mapped to an entry in a translation table. To decrease the probability that an entry is not available for a page, the translation table may be implemented as a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

Abstract: The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which code is executed very frequently, e.g. which code is hot code. The hardware also maintains the branch history information. When the hardware determines that a section or block of code is hot code, the hardware sends a signal to the software. The software then forms the trace from the hot code, and uses the branch history information in making branch predictions.

Abstract: A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable in a q-bit module address and an (n−q) bit row address in a power-of-two stride fashion. The row address is selected from (n−q) bits of the index address, and the module address for one of the Q accesses is obtained from bitwise exclusive-OR operation on bits obtained from corresponding positions in a plurality of q-bit fields grouped from the index address.

Abstract: An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware description 10 are input into the extracting portion 101, the extracting portion 101 extracts from the data whether the memory element is a memory device or an FF. The extracting portion 101 reads the top address and the address size of the memory element when the memory is the memory element and reads address when the memory is an FF, and the thus read data are output to the address competition detecting portion 103. The address competition detecting portion 103 detects competition of the addresses by determining whether the address information stored in the bit data memory portion 102 includes 1. The output portion 104 converts the data concerning address of the memory into a description language of the hardware of the bus interface circuit.

Abstract: A translation buffer is described which can translate virtual addresses to physical addresses wherein the virtual addresses have varying page sizes. The translation buffer includes a decoder to generate a hashed index, the index identifying an entry into two arrays. The first of the two arrays identifies a corresponding physical page address and the other array identifies a corresponding variable page address that in comparison to a variable portion of the virtual address, will indicate whether the entry in the first array has a matching entry. If the first array identifies a matching physical page address, then the physical page address is combined with the offset of the virtual address to yield a physical address translation of the virtual address.

Abstract: The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information of memory areas which are data storage destinations designated by a logical address issued by a host device. After an initializing process, the host device is immediately notified of canceling of a busy state, without production of the memory management table. Alternatively, only a part of the memory management table is produced and the host device is notified of the canceling of the busy state. After that, until the host device issues a process request, or when the host device is issuing a process request, an incomplete part of the memory management table is completed. Thus, the memory management table can be completed.

Abstract: A memory controller for reading data stored in a nonvolatile memory that includes a number of erasable blocks containing a number of pages. A logical/physical address control table stored in a logical/physical address control table block of the nonvolatile memory is searched, read, and manipulated in the nonvolatile memory.

Abstract: A translation buffer is described which can translate virtual addresses to physical addresses wherein the virtual addresses have varying page sizes. The translation buffer includes a decoder to generate a hashed index, the index identifying an entry into two arrays. The first of the two arrays identifies a corresponding physical page address and the other array identifies a corresponding variable page address that in comparison to a variable portion of the virtual address, will indicate whether the entry in the first array has a matching entry. If the first array identifies a matching physical page address, then the physical page address is combined with the offset of the virtual address to yield a physical address translation of the virtual address.

Abstract: A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the cache array. In one embodiment, the untranslated physical address bits select four virtual sets of cache lines. In parallel with the selection of the four virtual sets, a TLB translates the virtual portion of the store address to a physical address. Comparators compare the tags of all of the virtual sets with the translated physical address to determine if a match occurred. If a match occurs for any of the four virtual sets, even if not the set specified by the original virtual address bits of the store address, the cache indicates a hit. The matching virtual set, way and status are saved and used during the update pass to store the data.

Abstract: An exemplary embodiment of the invention is a virtual memory structure having a first virtual memory space and a virtual page frame table space. The first virtual memory space includes at least one private area and at least one common area. The virtual page frame table space is separate from the first virtual memory space. The virtual page frame table space includes at least one page frame table entry representing a frame of real memory.