Including Plural Logical Address Spaces, Pages, Segments, Blocks Patents (Class 711/209)
  • Patent number: 12013787
    Abstract: A computing device is configured to allocate memory for exclusive use of an execution entity from both a shared memory area and a private memory area of the device. Specifically, the shared memory area is configured with a united memory pool (UMP) component. The UMP component is configured to provide portions of huge page-based memory to execution entities for exclusive use of the execution entities. Memory granules that are allocated to the UMP component are divided into smaller memory chunks (which are smaller than a huge page), each of which can be allocated for exclusive use of an execution entity. These memory chunks are mapped to virtual address spaces of the assigned execution entities. Because memory granules can be allocated to, and deallocated from, the UMP component at run-time, the amount of memory that is available for private data generated by execution entities is able to be dynamically adjusted.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: June 18, 2024
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Nagarajan Muthukrishnan, William Henry Benjamin Habeck, Roshni Chatterjee, Sue-Kyoung Lee, Ravi Shankar Thammaiah, Sumanta Chatterjee
  • Patent number: 11922012
    Abstract: Apparatus and methods are disclosed, including a sequential mapping table located within a flash memory array of a flash memory device. Selected examples include firmware in the flash memory device to load the sequential mapping table into a cache upon power and perform read and write operations using the sequential mapping table. Selected examples include firmware in the flash memory device to store an updated sequential mapping table into the flash memory array upon power down of the flash memory device.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Xinghui Duan
  • Patent number: 11886362
    Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having an streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data is selectively via at least one of an accelerator interface, a data connection interface, a gateway interface and an memory interface, wherein the streaming engine is configured to perform data preparation processing of the batches of data streamed into the gateway prior to said batches of data being streamed out of the gateway, wherein the data preparation processing comprises at least one of: data augmentation; decompression; and decryption.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Ola Torudbakken, Brian Manula
  • Patent number: 11849129
    Abstract: A device includes a decoder configured to identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address for data access associated with a particular operation of the IBC decoding process. The target virtual address is generated according to an addressing scheme of a virtual memory used by the IBC decoding process. The decoder is configured to dynamically map the target virtual address to a particular memory address of a portion of an on-chip memory. The on-chip memory is configured to store reconstructed blocks of the video data and has a second size that is smaller than a first size of the virtual memory. The decoder is also configured to access the on-chip memory using the particular memory address to perform the particular operation of the IBC decoding process.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: December 19, 2023
    Assignee: QUALCOMM Incorporated
    Inventor: John Thodiyil
  • Patent number: 11656779
    Abstract: A computing system includes a host computing device and a slave computing device. The host computing device comprises a host processor, a host device memory and a host address mapping management. The host address mapping management manages a system memory page table, and converts, in response to a data access request from a processing process run on the host processor, requested virtual addresses into host device physical addresses based on the system memory page table to allow the processing process to access corresponding host storage units. The slave computing device includes a slave processor callable by the host processor to assist the host processor in running the processing processes, a slave device memory and a slave address mapping management unit.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: May 23, 2023
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Ye Yang, Jingzhong Yang, Gang Shan
  • Patent number: 11630920
    Abstract: A system may use memory tagging for side-channel defense, memory safety, and sandboxing to reduce the likelihood of successful attacks. The system may include memory tagging circuitry to address existing and potential hardware and software architectures security vulnerabilities. The memory tagging circuitry may prevent memory pointers from being overwritten, prevent memory pointer manipulation (e.g., by adding values), and increase the granularity of memory tagging to include byte-level tagging in cache. The memory tagging circuitry may sandbox untrusted code by tagging portions of memory to indicate when the tagged portions of memory include contain a protected pointer. The memory tagging circuitry provides security features while enabling CPUs to continue using and benefiting from speculatively performing operations.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: David M. Durham, Michael Lemay, Siddhartha Chhabra, Kai Cong
  • Patent number: 11625324
    Abstract: A storage device includes: a memory device including a map data block including mapping information between a logical address and a physical address; a buffer memory device for storing a block state table including block state information; and a memory controller for determining valid data of a source block among the plurality of memory blocks based on mapping information and block state information corresponding to the source block, and moving the valid data to open memory block. The memory controller may generate a valid page list in which information of the valid data is arranged in a stripe page unit according to an order of logical addresses, and control the memory device to move the valid data to the open memory block, based on the valid page list.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: April 11, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyeong Ju Na
  • Patent number: 11556480
    Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Aditya Navale, Ankur Shah, Murali Ramadoss, Ben Ashbaugh, Ronald Silvas
  • Patent number: 11550820
    Abstract: A system and method for partitioned snapshot creation of caches in a distributed data grid is provided. The system and method enables a snapshot to be created in a running system without quiescing a cache service. Moreover for each particular partition, execution of read/write requests are not blocked during the period that a snapshot creation task is being performed for the particular partition. The cache service thread continues to execute read requests for all partitions with write requests for the partition under snapshot experiencing delayed response. The system and method reduces the period of time for which partitions are unavailable during a snapshot process and increases the availability of cache services provided by a distributed data grid compared to prior snapshot systems.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: January 10, 2023
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Harvey Raja, Gene Gleyzer
  • Patent number: 11500768
    Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device and a memory controller. The memory device may include first memory blocks and second memory blocks. The memory controller may be configured to control the memory device so that valid data stored in a victim block, among the first memory blocks, is stored in a target block, among the second memory blocks, based on a result of a comparison between an amount of valid data stored in the victim block and a reference value. Each of the first memory blocks may include memory cells each configured to store n bits, where n is a natural number of 2 or more. Each of the second memory blocks may include memory cells each configured to store m bits, where m is a natural number less than n.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Eun Jae Ock
  • Patent number: 11467905
    Abstract: A stripe merging method and system based on erasure codes are provided. A StripeMerge-P algorithm is used first to determine alignment information of parity chunks of erasure code stripes based on a preprocessed hash table. Through a greedy strategy, erasure code stripe pairs to be merged are selected for merging. Through the hash table, location information of the parity chunks is directly looked up, so that no additional computing overhead is required, and the overhead of selecting and merging the erasure code stripe pairs is further reduced through the combination with the greedy strategy.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: October 11, 2022
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Yuchong Hu, Qiaori Yao, Liangfeng Cheng, Yazhe Zhang, Dan Feng
  • Patent number: 11455246
    Abstract: A garbage collection method is provided and applied to a data storage device. The garbage collection method includes the following steps: selecting source blocks from data blocks, wherein a total number of valid data of the source blocks is larger than or equal to a predetermined data number of a block; copying valid data of a part of the source blocks into a destination block, wherein a total number of the valid data of the part of the source blocks is smaller than the predetermined data number; copying all or a part of valid data of remaining source blocks into the destination block; updating a logical to physical addresses mapping table based on a mapping information of the destination block; and recovering all or a part of the source blocks as spare blocks.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 27, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Hsueh-Chun Fu
  • Patent number: 11379124
    Abstract: Apparatuses and methods related to updating data lines for data generation in, for example, a memory device or a computing system that includes a memory device. Updating data lines can include updating a plurality of data lines. The plurality of data lines can provide data form the memory array responsive to a receipt of the access command. The plurality of data lines can also be updated responsive to a determination that an access command received at a memory device is unauthorized.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Naveh Malihi
  • Patent number: 11379404
    Abstract: Remote memory management of the memory of a consumer computer by a producer computer is described. A system is described that can include a first computer, and a second computer communicatively coupled to the first computer via a remote direct memory access enabled communication network. The first computer can include a first operating system. The second computer can include a second operating system and a second memory. The second memory can include a plurality of buffers. The first computer can remotely manage the plurality of buffers of the second memory of the second computer without involving either the first operating system or the second operating system. The managing can further include the first computer identifying available buffers amongst the plurality of buffers. Related methods, apparatuses, articles, non-transitory computer program products, non-transitory computer readable media are also within the scope of this disclosure.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: July 5, 2022
    Assignee: SAP SE
    Inventors: Oliver Schmidt, Andreas Ludwig Erz
  • Patent number: 11334255
    Abstract: There is provided a method and device for data replication. The method comprises: obtaining, in a network interface card, data segments by segmenting input first data; determining, in the network interface card, fingerprints corresponding to the data segments; and comparing, in a central processing unit, the fingerprints of the data segments with existing fingerprints corresponding to processed data segments, and determining, based on a result of the comparing, whether to de-duplicate the data segments corresponding to the fingerprints, to perform the data replication.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 17, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Kun Wang, Colin Yong Zou, Sean Cheng Ye, Lyne Yuwei Li
  • Patent number: 11321354
    Abstract: The disclosed computing node comprises a processor and a non-transitory storage medium storing instructions executable by the processor. A method and a system are also disclosed. A subset of a plurality of conventional redo records, corresponding to received write requests, is selected based on an identical data location identifier. The conventional redo records of such selected subset are combined into a consolidated redo record. The consolidated redo record is then transmitted to a target node for processing.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 3, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xun Xue, Huaxin Zhang, Yuk Kuen Chan, Wenbin Ma
  • Patent number: 11237958
    Abstract: A garbage collection process, wherein a system, concurrently with execution of a mutator application that modifies a heap memory computes, for each of a plurality of regions in the heap memory, an estimate indicative of a time required to evacuate the respective region. Thereafter, during a garbage collection pause having a particular pause duration, the system selects a candidate subset of memory regions for evacuation. The system merges the estimates indicative of the time required to evacuate each region of the candidate subset and determines a remaining time during the pause. The system may determine that the total estimated evacuation time to evacuate the candidate subset of regions does not exceed the determined first remaining time, and may evacuate each region in the candidate subset of memory regions for evacuation.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 1, 2022
    Assignee: Oracle International Corporation
    Inventors: Thomas Schatzl, Erik Duveblad
  • Patent number: 11237982
    Abstract: Provided are a method and an apparatus for managing a page cache in a virtualization service and a method for managing a page cache in a virtualization service according to an exemplary embodiment of the present disclosure includes: comparing a weight value of a container and a weight variable of a page possessed by a process operated by the container in the virtualization service with each other, changing the weight variable of the page based on a comparison result, and managing pages of the page cache using the changed weight variable of the page.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: February 1, 2022
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Young Ik Eom, Kwon Je Oh, Jong Gyu Park
  • Patent number: 11200121
    Abstract: Provided are a method, system, and computer program product in which a computational device stores a data structure that includes identifications of a plurality of volumes and identifications of one or more time locks associated with each of the plurality of volumes. The data structure is indexed into, to determine whether an input/output (I/O) operation from a host with respect to a volume is to be permitted.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Carol S. Mellgren
  • Patent number: 11188640
    Abstract: A method includes establishing an isolated execution environment for executing a platform firmware operating mode subroutine in a platform firmware operating mode. In response to receiving an interrupt, the platform firmware operating mode subroutine is executed in the isolated execution environment. In response to detecting an attempted access of a hardware resource resulting from execution of the platform firmware operating mode subroutine, the attempted access is blocked when the attempted access violates a security policy.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 30, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeremy W Powell, David A Kaplan
  • Patent number: 11150819
    Abstract: A memory system includes a memory device including a plurality of memory blocks, and a controller in communication with the memory device to control an operation of the memory device, the controller allocating, among the plurality of memory blocks, a normal region and a redundancy region. The controller divides the normal region into a user region for storing user data, a user overprovisioning region for user data management, a map region for storing map data, and a map overprovisioning region for map data management, and divides the redundancy region into a reserved region and an additional map overprovisioning region, and wherein the reserved region, upon determination that a block in the normal region is a bad block, replaces the bad block.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11029869
    Abstract: Systems and methods are disclosed herein for multithreaded access to cloud storage. An exemplary method comprises creating a plurality of mount points by mounting, by a hardware processor, a plurality of file systems on a computer system, creating an image file on each of the plurality of mount points, instantiating, for each of the plurality of mount points, a block device on the image file, creating a union virtual block device that creates one or more stripes from each block device, delegating a request for accessing the union virtual block device, received from a client, to one or more block devices and merging a result of the request from each of the one or more block devices and providing the result to the client.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 8, 2021
    Assignee: Virtuozzo International GmbH
    Inventors: Maxim Patlasov, Alexey Kuznetzov, Pavel Emelyanov, Alexey Kobets
  • Patent number: 10956320
    Abstract: A memory system may include: a memory device including a plurality of memory dies; and a controller including a memory, and configured to: sequentially store, after storing data segments of sequential user data in the memory, the data segments of the sequential user data in the memory dies through interleaving; store in a first buffer region of the memory, after updating map segments of lower level map data corresponding to the storage of the data segments in the memory dies, the map segments of the lower level map data; and store in a second buffer region of the memory map segments of upper level map data corresponding to storage of the map segments of the lower level map data.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10949123
    Abstract: In one embodiment, a solid state device includes a controller and a non-volatile memory. The non-volatile memory includes a plurality of dies. Each die includes a plurality of planes. A first super-plane-block is structured from a first plane of the plurality of dies. A second super-plane-block is structured from a second plane of the plurality of dies. A plurality of memory operation instructions that, when executed by the controller, cause the controller to receive a first data stream, write the first data stream to the first super-plane-block, receive a second data stream, and write the second data stream to the second super-plane-block.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Liam Parker
  • Patent number: 10922241
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Patent number: 10909077
    Abstract: A system and method for utilizing slack space as another file system. The system identifies available slack space caused by storing data on a drive. The slack space is then made available as part of a separate file system. The separate file system allows for dynamic cluster sizes as the cluster size depends on the slack space of each individual file. The available space for the file system also dynamically changes based on the change in slack space caused by new data files being stored on the drive, edits to data files on the drive, or deletion of data files.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 2, 2021
    Assignee: PayPal, Inc.
    Inventor: Shlomi Boutnaru
  • Patent number: 10901912
    Abstract: An apparatus is provided that includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller is configured to access a global address table (GAT) that maps logical addresses of a host to physical addresses of the non-volatile memory, receive a request from the host to write first data to the non-volatile memory, determine that the first data comprises fragmented data that are not aligned to a minimum write unit of the non-volatile memory, and create an unaligned GAT page, wherein the unaligned GAT page comprises a logical-to-physical mapping for the first data.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Patent number: 10891055
    Abstract: Data address management systems, methods, devices and uses for minimizing interaction with data consumers' data on data storage devices, an embodiment comprising an external bus for communicatively interfacing the data storage system and data consumers; at least one storage medium components, each storage medium component comprising a plurality of storage locations having a unique storage location indicators; a translation layer module comprising a data address space having data addresses associable with storage location indicators; and a controller configured to store data in the storage locations and creating associations in the translation layer module between data addresses and the physical location indicators; wherein the data address space is accessible by the data consumer for addressing requests relating to data stored on the storage device and wherein the controller is configured to manipulate the arrangement of the data addresses in the data address space.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 12, 2021
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: Andrew Warfield, Timothy John Deegan, Keir Fraser, Daniel Stodden, Kevin Jamieson
  • Patent number: 10871921
    Abstract: One embodiment facilitates atomicity assurance for storing data and metadata in a data stream. The system receives a first stream of data to be written to a storage device, wherein the first stream includes a plurality of I/O requests associated with data and corresponding metadata. In response to determining that residual data associated with a preceding I/O request of the first stream exists in a data buffer: the system appends, to the residual data, a first portion of data from a current I/O request to obtain a first page of data; the system writes a remainder portion of the current I/O request to the data buffer to obtain current residual data; and the system writes the first page of data to the storage device. Thus, the system thereby facilitates atomicity assurance for storing the data and corresponding metadata of each I/O request of the first data stream.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 22, 2020
    Assignee: Alibaba Group Holding Limited
    Inventors: Shu Li, Ping Zhou
  • Patent number: 10834241
    Abstract: Apparatus and associated methods relating to data packet deparsing include an editing circuit configured to perform one or more predetermined editing operations on headers of an incoming data packet step by step without extracting all headers from the incoming data packet. In an illustrative example, an editor circuit may include an updating circuit configured to receive the data packet and update a header in the data packet. The editor circuit may also include a removal circuit configured to remove a header from the data packet. The editor circuit may also include an insertion circuit configured to insert one or more consecutive headers to the data packet. A state machine may be configured to enable or disable the updating circuit, the removal circuit, and/or the insertion circuit based on the predetermined editing operations. By using the editing circuit, packet deparsing may be performed with less hardware resources and low latency.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 10, 2020
    Assignee: XILINX, INC.
    Inventors: Ian McBryan, Gordon J. Brebner, Jaime Herrera, Rowan Lyons
  • Patent number: 10826840
    Abstract: Some embodiments provide a method for a packet processing pipeline of a network forwarding integrated circuit. The method stores two copies of a stateful table used by the packet processing pipeline. The stateful table is modified according to data processed by the packet processing pipeline. Upon receiving data to write to the stateful table, the method generates (i) a first copy of the received data along with an indicator for a first one of the copies of the stateful table and (ii) a second copy of the received data along with an indicator for a second one of the copies of the stateful table. The method sends the first copy of the received data into the packet processing pipeline before sending the second copy of the received data into the packet processing pipeline.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 3, 2020
    Assignee: Barefoot Networks, Inc.
    Inventors: Jay Evan Scott Peterson, Michael Gregory Ferrara, Anurag Agrawal, Patrick Bosshart, Jeongkeun Lee
  • Patent number: 10747563
    Abstract: Systems and techniques are described for optimizing memory sharing. A described technique includes grouping virtual machines (VMs) into groups including a first group; initializing a first VM in the first group, wherein initializing the first VM includes identifying, for each of one or more first memory pages for the first VM, a respective base address for storing the first memory page using an address randomization technique, and storing, for each of the one or more first memory pages, data associating the first memory page with the respective base address for the first group, and initializing a second VM while the first VM is active, wherein initializing the second VM includes determining that the second VM is a member of the first group, and in response, storing one or more second memory pages for the second VM using the respective base addresses stored for the first group.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 18, 2020
    Assignee: VMware, Inc.
    Inventors: Guang Gong, Qi Kang, Le Tian, Chengxiao Wang, Yimin Zhao, Shiyao Yuan
  • Patent number: 10740026
    Abstract: Recording an indicator of time at which a super block is erased, recording an indicator of time at which a first page of the super block is programmed, and recording an indicator of time at which a last page of the super block is programmed.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kevin R. Brandt
  • Patent number: 10733316
    Abstract: Techniques are described herein for allowing a container DBMS to impose restrictions, on a per-pluggable-database basis, on operations based on the pluggable database to which the users that request the operations belong. In one embodiment, lockdown profiles can be created and mapped to pluggable databases. Lockdown profiles specify PDB-wide restrictions on operations. The restrictions may apply to all operations of a given type, may apply to specific features, may require use of specific parameter values, etc. All users that belong to a pluggable database are restricted by the restrictions specified in the lockdown profile to which their pluggable database is mapped, unless the lockdown profile has a user-specific exemption for them. Bitmaps and/or hash tables may be used to more quickly determine, at query runtime, whether a query violates any profile-specified restrictions. Execution of queries that violate any profile-specified restrictions is prevented.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: August 4, 2020
    Assignee: Oracle International Corporation
    Inventors: Prashanth Shanthaveerappa, Sanket Jain, Kumar Rajamani, Andre Kruglikov
  • Patent number: 10684955
    Abstract: Examples described herein include systems and methods which include an apparatus comprising a memory array including a plurality of memory cells and a memory controller coupled to the memory array. The memory controller comprises a memory mapper configured to configure a memory map on the basis of a memory command associated with a memory access operation. The memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array. For example, the specific sequence of memory access instructions for a diagonal memory command comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fa-Long Luo, Tamara Schmitz, Jeremy Chritz, Jaime Cummins
  • Patent number: 10671528
    Abstract: A memory system may comprise: a memory device including a plurality of memory dies; and a controller including a first memory, Wherein the controller may store data segments of user data, corresponding to a plurality of commands received from a host, in the first memory, controls the memory device to sequentially store the data segments in the memory dies through interleaving, may update map segments of map data corresponding to storage of the data segments in the memory dies, may store the map segments in the first memory, controls the memory device to store the map segments stored in the first memory in the memory dies, and may assist the host in storing the map segments, stored in the first memory, in a second memory in the host.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hyniX Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10628308
    Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: April 21, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Kunal Desai, Satyaki Mukherjee, Abhinav Mittal, Siddharth Kamdar, Umesh Rao, Vinayak Shrivastava
  • Patent number: 10628613
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for secure memory page mapping in a virtual machine (VM) environment. The system may include a processor configured to execute a virtual machine monitor (VMM). The VMM may be configured to maintain a table of cryptographic keys and associate a token with one of the memory pages to be mapped from a guest linear address (GLA) to a guest physical address (GPA). The token may include a key identifier (key ID) associated with one of the cryptographic keys, and an authentication code based on the GLA, the GPA, and one of the cryptographic keys. The system may also include a page walk processor configured to validate the token to indicate that the memory page associated with the token is authorized to be mapped from the GLA to the GPA.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventor: Michael LeMay
  • Patent number: 10565101
    Abstract: For storing data in a storage device, a storage allocation request may be received. The storage allocation request may include a logical offset of data to be stored. Further, a chunk size of the storage device and a device offset for a free region on the storage device may be received. An offset value may be computed based on the chunk size, file system block size, the device offset, and the logical offset. A device start address, for storing the data in response to the storage allocation request, can be determined by offsetting the device offset with the offset value.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 18, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Narayanan Ananthakrishnan Nellayi, Shyamalendu Sarkar, Subhakar Vipparti
  • Patent number: 10558611
    Abstract: Embodiments relate to a computer system, computer program product, and method to process complex files, and specifically, to support read and write requests of a multi-object file. Upon receipt of a file, a computer system parses the file into two or more logical objects. Each logical object has an associated or inherent characteristic. Each of the logical objects is matched to a storage tier in a multi-tier storage array. Each logical object is then assigned to a tier based on one or more object characteristics in the matched storage tier, and stored in a decomposed format. In addition, an identification of each logical object, and the object assignment, is recorded in an index.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dean Hildebrand, Vasily Tarasov
  • Patent number: 10552308
    Abstract: Techniques for determining whether processes are running on a computing device are described. As an example, a detection process may create a virtual mapping of data to memory of the computing device. The detection process may access a file system storing special files including attributes of virtual memory mappings. The detection process may analyze the attributes of the virtual memory mapping, such as an amount of data stored or shared by the memory mapping, to determine that another process is sharing the memory mapping with the detection process. The detection process may send data to a server associated with the computing device indicating that a process other than the detection process is operating on the computing device.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 4, 2020
    Assignee: Square, Inc.
    Inventor: Christopher Rohlf
  • Patent number: 10540235
    Abstract: The disclosed techniques include generation of a single index table when backing up data in a first backup format to a backup storage system that uses a second backup format. Using the single index table, a query for a data item can be answered by searching the single index table. The single index table avoids having to search through multiple index tables, each corresponding to a different backup format that may be used for backing up the searched data item.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 21, 2020
    Assignee: Commvault Systems, Inc.
    Inventor: Manoj Kumar Vijayan
  • Patent number: 10528435
    Abstract: Provided are a method, system, and computer program product in which a computational device stores a data structure that includes identifications of a plurality of volumes and identifications of one or more time locks associated with each of the plurality of volumes. The data structure is indexed into, to determine whether an input/output (I/O) operation from a host with respect to a volume is to be permitted.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Carol S. Mellgren
  • Patent number: 10521156
    Abstract: A management apparatus of a multi-solid state disk (SSD) system implemented by a computer is provided. The management apparatus of the multi-SSD system may include a first SSD group including a plurality of SSDs arranged in rows or columns and configured to execute a received write command using segments in the plurality of SSDs, a second SSD group including a plurality of SSDs arranged in rows or columns and configured to execute a read command for valid data in the plurality of SSDs, and a manager configured to copy a valid page in the second SSD group while a write command for the first SSD group being executed and to erase all data in the second SSD group when the copying is completed.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 31, 2019
    Assignee: UNIST (Ulsan National Institute of Science and Technology)
    Inventors: Sam H Noh, Byungsuck Kim, Jaeho Kim, KwangHyun Lim
  • Patent number: 10482039
    Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: November 19, 2019
    Assignee: Montage Technology Co., Ltd.
    Inventors: Shuna Xu, Guobing Mo, Cheng-Tie Chen
  • Patent number: 10459642
    Abstract: There is provided a method and device for data replication. The method comprises: obtaining, in a network interface card, data segments by segmenting input first data; determining, in the network interface card, fingerprints corresponding to the data segments; and comparing, in a central processing unit, the fingerprints of the data segments with existing fingerprints corresponding to processed data segments, and determining, based on a result of the comparing, whether to de-duplicate the data segments corresponding to the fingerprints, to perform the data replication.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 29, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Kun Wang, Colin Yong Zou, Sean Cheng Ye, Lyne Yuwei Li
  • Patent number: 10437476
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: receive, via the host interface, a request from a host to allocate a namespace of a quantity of non-volatile memory; generate, in response to the request, a namespace map identifying a plurality of blocks of addresses having a same predetermined block size, and a partial block of addresses having a size smaller than the predetermined block size; and convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory. For example, the request for allocating the namespace can be in accordance with an NVMe protocol.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 8, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Alex Frolikov
  • Patent number: 10430280
    Abstract: The disclosed techniques include generation of a single index table when backing up data in a first backup format to a backup storage system that uses a second backup format. Using the single index table, a query for a data item can be answered by searching the single index table. The single index table avoids having to search through multiple index tables, each corresponding to a different backup format that may be used for backing up the searched data item.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 1, 2019
    Assignee: Commvault Systems, Inc.
    Inventor: Manoj Kumar Vijayan
  • Patent number: 10369473
    Abstract: A method for providing virtual world functionality to a user of a base virtual world having base virtual world functionality and a base world list of base virtual world users, includes providing a virtual world layer, communicating to the base virtual world that the virtual world layer will overlay the base virtual world and adding the virtual world layer to the base world list in order to register the virtual world layer with the base virtual world.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: George R. Dolbier, Rick A. Hamilton, II, Neil A. Katz, Brian M. O'Connell
  • Patent number: 10331577
    Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: June 25, 2019
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Shuna Xu, Guobing Mo, Cheng-Tie Chen