Including Plural Logical Address Spaces, Pages, Segments, Blocks Patents (Class 711/209)
  • Patent number: 10331577
    Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: June 25, 2019
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Shuna Xu, Guobing Mo, Cheng-Tie Chen
  • Patent number: 10303620
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
  • Patent number: 10248556
    Abstract: Computer-implemented methods and systems for managing data in one or more data storage media are provided. An example method may comprise creating a data structure within the data storage media. The data structure includes a plurality of memory pages, each page comprising a plurality of sessions, and each session comprising a header and a plurality of data objects. The method also comprises enabling writing data to the data storage medium, in response to routine requests, such that the data is recorded to the one or more data objects nearest the current location of a virtual cursor. When a data management operation is performed, the virtual cursor is moved within a single page in a single direction.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 2, 2019
    Assignee: EXABLOX CORPORATION
    Inventor: Frank E. Barrus
  • Patent number: 10203954
    Abstract: Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Jesus Corbal, Robert Valentine, Bret L. Toll, Mark J. Charney
  • Patent number: 10185828
    Abstract: Systems and methods are provided that may be implemented to securely load Unified Extensible Firmware Interface (UEFI) images (e.g., UEFI Applications, UEFI Drivers, UEFI firmware volumes, etc.) onto an information handling system from an authenticated (e.g., OEM authenticated) hardware image source device or “IO store” (e.g., such as USB device, network file system device, PCIe device, network storage, shared storage, dynamic RAM disk, etc.) based on a UEFI virtual device path that is mapped to an authenticated hardware device path that is established for the authenticated hardware image source device.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 22, 2019
    Assignee: Dell Products L.P.
    Inventors: Sumanth Vidyadhara, Chandrasekhar Puthillathe, Aniruddha Herekar
  • Patent number: 10162548
    Abstract: A distributed network of storage elements (DNSE) is provided in which the physical capacity of each drive is split into a set of equal sized logical splits which are individually protected within the DNSE using separate RAID groups. To reduce restoration latency, members of the RAID groups having a member in common on a given drive are spread within the DNSE to minimize the number of sets of drives within the DNSE that have RAID members in common. By causing the splits to be protected by RAID groups, restoration of the splits may occur in parallel involving multiple drives within the DNSE. By minimizing the overlap between RAID members on various drives, failure of a given drive will not require multiple reads from another drive in the DNSE. Likewise, spare splits are distributed to enable write recovery to be performed in parallel on multiple drives within the DNSE.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 25, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Edward S. Robins, Kevin Granlund, Seema Pai, Evgeny Malkevich, Stephen Richard Ives, Roii Raz, Barak Bejerano
  • Patent number: 10133640
    Abstract: A storage apparatus includes a first storage device and a processor. The first storage device is configured to store therein first information blocks used to recover second information blocks stored in a second storage device. The processor is configured to read the first information blocks from the first storage device in an order of addresses of storage areas of the first storage device. The processor is configured to output part of the first information blocks which have been read from the first storage device to respective recovery destinations of the second information blocks to recover the second information blocks step by step.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: November 20, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Kensuke Shiozawa
  • Patent number: 10102218
    Abstract: A file system allows a different checksum algorithm to be used for different extents of a file system object independently of other extents of the file system object. The checksum algorithm can be a selectable attribute of an extent or range of extents of a file system object, such that some extents of a file system object can use a first checksum algorithm, while other extents of the file system object can use a second checksum algorithm. An extent of the file system object also may have no associated checksum algorithm. The file system stores, for each extent of a file system object, data indicating a checksum for the extent and an indication of any checksum algorithm used for the extent.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 16, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chesong Lee, Raj Das, Cornel Rat, William Tipton
  • Patent number: 10007609
    Abstract: A data processing system includes a plurality of virtual machines each having associated memory pages; a shared memory page cache that is accessible by each of the plurality of virtual machines; and a global hash map that is accessible by each of the plurality of virtual machines. The data processing system is configured such that, for a particular memory page stored in the shared memory page cache that is associated with two or more of the plurality of virtual machines, there is a single key stored in the global hash map that identifies at least a storage location in the shared memory page cache of the particular memory page. The system can be embodied at least partially in a cloud computing system.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Parijat Dube, Xavier R. Guerin, Seetharami R. Seelam
  • Patent number: 9912591
    Abstract: An exact-match flow table structure of an integrated circuit stores flow entries. Each flow entry includes a Flow Id and an action value. Each Flow Id is a multi-bit digital value that uniquely identifies a flow. A Flow Id does not include any wildcard indictor. The flow table structure cannot and does not store an indicator that any particular part of a packet should be matched against any part of a Flow Id. In one example, a packet is received onto the integrated circuit. A Flow Id is generated from the packet. If the flow table structure determines that the Flow Id is a bit-by-bit exact-match of any Flow Id of any stored flow entry, then the packet is handled according to the action value of the flow entry. If, on the other hand, there is not exact-match, then a miss indication is output from the integrated circuit.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 6, 2018
    Assignee: Netronome Systems, Inc.
    Inventors: Gavin J. Stark, Stuart C. Wray
  • Patent number: 9852081
    Abstract: A multi-dimension engine, connected to a system TLB, generates sequences of addresses to request page address translation prefetch requests in advance of predictable accesses to elements within data arrays. Prefetch requests are filtered to avoid redundant requests of translations to the same page. Prefetch requests run ahead of data accesses but are tethered to within a reasonable range. The number of pending prefetches are limited. A system TLB stores a number of translations, the number being relative to the dimensions of the range of elements accessed from within the data array.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: December 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Laurent Moll
  • Patent number: 9778874
    Abstract: The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated with the write command, determining if a transformation value of the data exists in a transformation table, and responsive to a determination that the transformation value does not exist in the transformation table, writing the data associated with the write command to a memory device.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventor: John C. Rudelic
  • Patent number: 9740624
    Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. For a system configuration that includes partitions, the translation mechanism to be used for a partition or a portion thereof is selectable and may be different for different partitions or even portions within a partition.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9740625
    Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. For a system configuration that includes partitions, the translation mechanism to be used for a partition or a portion thereof is selectable and may be different for different partitions or even portions within a partition.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9734051
    Abstract: Example apparatus and methods provide improved reclamation, garbage collection (GC) and defragmentation (defrag) for data storage devices including solid state drives (SSD) or shingled magnetic recording (SMR) drives. An erasure code (EC) layer that facilitates logically or physically erasing data from the SSD or SMR as a comprehensive GC or defrag is added to the SSD or SMR. Erased data may be selectively recreated from the EC layer as needed. Pre-planned EC write zones may be established to further optimize GC and defrag. Recreated data may be written to selected locations to further optimize SSD and SMR performance. Erasure code data may be distributed to co-operating devices to further improve GC or defrag. Example apparatus and methods may also facilitate writing data to an SMR drive using tape or VTL applications or processes and providing a pseudo virtual tape library on the SMR drive.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: August 15, 2017
    Assignee: Quantum Corporation
    Inventors: Roderick Wideman, Don Doerner
  • Patent number: 9715350
    Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9658792
    Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: May 23, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9639464
    Abstract: A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: May 2, 2017
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Haggai Eran, Shachar Raindel, Liran Liss, Noam Bloch
  • Patent number: 9632953
    Abstract: An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Assaf Shacham, Dolev Raviv, David Teb
  • Patent number: 9628438
    Abstract: Computer-implemented methods and systems for managing data objects within a computer network infrastructure that facilitate more efficient and reliable data storage and access are provided. An exemplary method may comprise establishing a physical identifier for each storage resource. A plurality of unique virtual identifiers for each storage resource is generated based on the physical identifier. The plurality of unique virtual identifiers is stored in a consistent ring namespace accessible to every node. An object identifier associated with a location of a data object to be stored in a storage resource is generated. The object identifier is mapped to the consistent ring namespace. The method may also include enabling traversing the consistent ring namespace from any node in the computer network to locate and access the data object.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: April 18, 2017
    Assignee: EXABLOX
    Inventors: Charles Hardin, Sridhar Subramaniam, Tad Hunt, Frank E. Barrus
  • Patent number: 9569243
    Abstract: Embodiments disclosed herein generally include a computer-implemented method, computer program product, and system to facilitate offloaded and parallelized direct memory access (DMA) translation table operations. The method includes a hypervisor requesting a lease on an auxiliary parallel processing element assigned to a first virtual machine hosted by the hypervisor. The method further includes receiving a grant of the lease, whereby ownership of the auxiliary parallel processing element is transferred from the first virtual machine to the hypervisor. The method further includes, during the lease, providing a predefined program to execute on the auxiliary parallel processing element in order to perform a desired operation on the hypervisor DMA translation table and with parallelism. The method further includes, upon completion of the predefined program, terminating the lease by the hypervisor, whereby ownership of the auxiliary parallel processing element is returned to the first virtual machine.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Justin K. King
  • Patent number: 9552295
    Abstract: Technologies are described herein for improving performance and energy efficiency in a computing system while using a large memory page size. Some example technologies may configure a main memory of the computing system to include a page-to-chunk table and a data area. The page-to-chunk table may include multiple entries such as a first entry. The first entry may correspond to a page that is made up of multiple chunks. The first entry may include pointers to the multiple chunks stored in the data area.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: January 24, 2017
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 9542340
    Abstract: An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: January 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Assaf Shacham, Dolev Raviv, David Teb
  • Patent number: 9507730
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
  • Patent number: 9437327
    Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
  • Patent number: 9437031
    Abstract: A large non-patterned noise texture occupies a relatively small physical memory space. Each of a small set of physical pages in physical memory includes noise texels forming part of a noise texture. A large “virtual” noise texture is created by mapping each one of a large number of pages in virtual address space to one of the small set of physical pages; multiple virtual pages may be mapped to the same physical page. The physical page that each virtual page maps to is randomly or pseudo-randomly selected such that the resulting noise texture appears to be non-repeating. When a noise texel is requested by reference to a virtual address during rendering, the virtual address of the virtual page is translated to the corresponding physical address, and the noise texel is retrieved.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: September 6, 2016
    Assignee: NVIDIA Corporation
    Inventor: Cass W Everitt
  • Patent number: 9329803
    Abstract: A data storage system includes storage devices and a processing subsystem executing software forming a lower-deck file system and an upper-deck file system. The lower-deck file system presents a volume file from which storage is provided to the upper-deck file system, and units of storage of the storage devices are allocable to the upper-deck file system but are not reserved to it. The volume file is thinly provisioned, and additional units of storage are added dynamically to increase its allocated size in response to demand from the upper-deck file system. The lower-deck file system operates in a mapped mode in which a block address in the lower-deck file system is obtained by a generally arbitrary mapping (e.g., an Inode/IB tree) of a block address in the volume file.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 3, 2016
    Assignee: EMC Corporation
    Inventors: Jean-Pierre Bono, William C. Davenport, Miles A. de Forest, Walter C. Forrester, Michal Marko, Ye Zhang, Philippe Armangau
  • Patent number: 9298614
    Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence D. Curley, Patrick J. Meaney, George C. Wellwood
  • Patent number: 9292437
    Abstract: The allocation of virtual memory within a virtual machine based upon the previous mapping of virtual memory blocks to physical memory blocks is optimized. Virtual memory blocks that have been mapped to a corresponding physical memory block over virtual memory blocks that are unmapped when fulfilling an allocation request can be reallocated preferentially.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: March 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles D. Brant, Esther M. Burwell, Robert L. Orr, Troy M. Volin, Douglas A. Wood
  • Patent number: 9141554
    Abstract: Data processing methods and apparatus for efficiently storing and retrieving data, e.g., blocks of data, to and from memory. The data processing including, e.g., techniques such as using linked lists and/or tables for tracking duplicate data blocks received for storage, the use of lossless data compression, and de-duplication based on comparing hash values, compressed data block sizes, and/or bit by bit comparisons of the block of data to be stored and previously stored blocks of data.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: September 22, 2015
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: James Candelaria
  • Patent number: 9122415
    Abstract: The present invention aims at preventing the access performance of a distributed memory system by accessing via cross-over ownership a track mapping information formed as a hierarchical memory. In the process of assigning a real data storage area to a virtual volume, at first, a page from a pool is assigned, and thereafter, a track is assigned from said page. The page is composed of multiple tracks into which track data assigned at host write operation timings are stored sequentially from the top. A mapping information of the virtual volume and the page is stored in a control information page that differs from the track data, and the mapping information is stored in the control information page which could only be accessed by a microprocessor having the ownership of the virtual volume.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: September 1, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Kohei Tatara
  • Patent number: 9110794
    Abstract: In one embodiment, a method includes recording, for each of a plurality of data frames, a virtual write address including a multiframe indicator and a byte number indicator; and reading a group of associated data frames identified by corresponding multiframe indicators and byte number indicators. The reading is based on determining a minimum write address from a plurality of physical write addresses in the group of associated data frames by comparing virtual write addresses of all members in the group.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: August 18, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jing Ling, Soowan Suh, Juan-Carlos Calderon
  • Patent number: 9037832
    Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the at least one local page address linking table includes linking relationships between at least one physical page address of the at least one block and at least one logical page address; and building a global page address linking table of the memory apparatus according to the at least one local page address linking table.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 19, 2015
    Assignee: Silicon Motion Inc.
    Inventors: Tsai-Cheng Lin, Chun-Kun Lee
  • Patent number: 9032145
    Abstract: A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The protection system is used to prevent at least some of a plurality of processors in a system from accessing addresses designated by one of the processors as a protected memory address. Until the processor releases the protection, only the designating processor can access the memory device at the protected address. If the memory device contains a cache memory, the protection system can alternatively or additionally be used to protect cache memory addresses.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventor: David Resnick
  • Patent number: 9021232
    Abstract: There is provided a method of operating a multipath storage system, the method comprises: identifying a primary storage control port configured to be responsible for a given LBA range and a secondary storage control port configured to have secondary responsibility for the given LBA range; reducing, in a manner unaffecting respective inbound I/O operation, outbound I/O operation related to the given LBA range and occurring at the primary storage control port, thereby causing a situation requiring switching all respective I/O requests to an alternating path; analyzing responsive changes in outbound I/O operation related to the given LBA range and occurring at the secondary storage control port, and verifying operability of switching to the alternating path in accordance with the obtained results.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 28, 2015
    Assignee: Infinidat Ltd.
    Inventors: Haim Kopylovitz, Leo Corry
  • Patent number: 9020541
    Abstract: A method of processing a paging message, the method being suitable for a User Equipment (UE) for a wireless telecommunication system, and comprising the steps of:—monitoring a Paging Indicator (PI) included in a Paging Indicator Channel (PICH) message;—upon reception (210) of a Paging Indicator (PI) relevant to said User Equipment, detecting and decoding a paging (PCH) channel in order to decode a corresponding paging message (220);—computing and checking the CRC (230) of said paging message and, in case of failure of the CRC check, performing the following steps:—performing (240, 250) a partial checking of said paging message, said partial checking being limited to a number of fields of said paging message;—determining whether said paging message is relevant to one single UE (260);—if said paging message is relevant to one single UE, replacing (261) the bits not relevant to said single UE by default bits and computing and checking (262) a new CRC—if the new CRC check succeeds, forwarding the processed paging
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: April 28, 2015
    Assignee: St-Ericsson SA
    Inventors: Pierre Demaj, Fabrizio Tomatis, Martial Gander
  • Publication number: 20150106587
    Abstract: A processor remaps stored data and the corresponding memory addresses of the data for different processing units of a heterogeneous processor. The processor includes a data remap engine that changes the format of the data (that is, how the data is physically arranged in segments of memory) in response to a transfer of the data from system memory to a local memory hierarchy of an accelerated processing module (APM) of the processor. The APM's local memory hierarchy includes an address remap engine that remaps the memory addresses of the data at the local memory hierarchy so that the data can be accessed by routines at the APM that are unaware of the data remapping. By remapping the data, and the corresponding memory addresses, the APM can perform operations on the data more efficiently.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shuai Che, Bradford Beckmann, Blake Hechtman
  • Patent number: 9009424
    Abstract: Embodiments of the invention relate to data placement for loss protection in a storage system. One embodiment includes constructing multiple logical compartments. Each logical compartment includes a placement policy including a set of storage placement rules for placement of storage symbols into a set of physical storage containers. A first logical compartment of said plurality of logical compartments is container-overlapped with respect to a second logical compartment of said plurality of logical compartments. The first logical compartment is data loss independent with respect to the second logical compartment. Each of multiple storage volumes is associated with a logical compartment. The storage symbols that represent a data stripe are placed onto physical storage containers in conformity with the placement policy associated with the logical compartment containing the data stripe.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventor: David D. Chambliss
  • Patent number: 9009386
    Abstract: A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. One computer storage medium includes a computer program product for performing the above method.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Hatfield, Wenjeng Ko, Lei Liu
  • Patent number: 9003161
    Abstract: A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Hatfield, Wenjeng Ko, Lei Liu
  • Patent number: 8996837
    Abstract: A technique provides multi-tenancy within a data storage apparatus. The technique involves dividing, by processing circuitry, storage units of the data storage apparatus into multiple groups of storage units. The technique further involves forming, by the processing circuitry, segregated slice pools from the multiple groups of storage units. Each segregated slice pool is formed from a different group of storage units. The technique further involves allocating, by the processing circuitry, slices from the segregated slice pools to mutually exclusive sets of virtual storage processors (VSPs) on the data storage apparatus. Each mutually exclusive set of VSPs operates as a separate tenant of the data storage apparatus.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: EMC Corporation
    Inventors: Jean-Pierre Bono, Frederic Corniquet, Miles A. de Forest, Himabindu Tummala, Walter C. Forrester
  • Patent number: 8996843
    Abstract: A method for assigning data in a plurality of physical storage resources for an information handling system is disclosed. The plurality of physical storage resources includes a first tier and a second tier with a lower performance and cost relative to capacity than the first tier. A tier manager hosted on the information handling system and in electronic communication with the plurality of physical storage resources is configured to: determine a seek distance value, operation rate, operation size value, and elapsed time value for each page; and calculate a relative randomness value for each page using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page. A classification module may assign a physical location for each page such that the relative randomness value for each page in the first tier is greater than the relative randomness value for each page in the second tier.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: March 31, 2015
    Assignee: Dell Products L.P.
    Inventors: William Price Dawkins, Stephen Gouze Luning
  • Patent number: 8996844
    Abstract: A system including a storage device and a controller. The storage device is configured to store a map. The map relates (i) a first portion of a memory to a first order of first dimensions, and (ii) a second portion of the memory to a second order of second dimensions. The first portion of the memory and the second portion of the memory are non-overlapping. Each of the first dimensions and each of the second dimensions has corresponding memory cells in the memory. The controller is configured to control access to the first portion of the memory according to the first order of first dimensions while controlling access to the second portion of the memory according to the second order of the second dimensions.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 31, 2015
    Assignee: Marvell International Ltd.
    Inventors: Jun Zhu, Joseph Jun Cao, Samitinjoy Pal, Hongyan Liu, Can Ma
  • Patent number: 8990504
    Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tara Astigarraga, Michael E. Browne, Joseph Demczar, Eric C. Wieder
  • Patent number: 8990541
    Abstract: A method, system, and computer program product for improving memory utilization of sparse pages are provided in the illustrative embodiments. A set of virtual pages is identified. Each virtual page in the set of virtual pages is a sparse virtual page. The set of virtual pages includes a first sparse virtual page and a second sparse virtual page. At least a portion of data of the first sparse virtual page in the set of virtual pages is stored in a first physical page. The first physical page belongs to a set of consolidation physical pages, and the first physical page also stores at least a portion of the data of the second sparse virtual page. The first and the second sparse pages are mapped to the first physical page.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adekunle Bello, Douglas Griffith, Angela Astrid Jaehde, Srinivasa Muppala Rao
  • Patent number: 8977834
    Abstract: A method or system for determining storage location of an isolation region based on a data region sizing specified by a host device. In one implementation, the isolation region comprises a set of storage locations required for isolation of or more data region of the storage device.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 10, 2015
    Assignee: Seagate Technology LLC
    Inventor: Timothy Richard Feldman
  • Patent number: 8972648
    Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to hypervisor, allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keerthi Kumar, Shailaja Mallya
  • Patent number: 8972691
    Abstract: A mechanism is provided for cross-allocated block repair in a mounted file system. A set of cross-allocated blocks are identified from a plurality of blocks within an inode of the mounted file system, based on a corresponding bit associated with each cross-allocated block in a duplicated block information bitmap being in a first identified state. The set of cross-allocated blocks are repaired using a user-defined repair process. Then one or more of the set of cross-allocated blocks are deallocated based on results of the user-defined repair process.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kalyan C. Gunda, Srikanth Srinivasan
  • Patent number: 8966209
    Abstract: Systems and methods are disclosed for efficient allocation policies for a system having non-volatile memory. A file system allocator of the system can be configured to allocate memory regions that are aligned with one or more logical blocks of a logical space (e.g., one or more super block-aligned regions). In some embodiments, the file system allocator can monitor the number of free sectors corresponding to each logical block. In other embodiments, the file system allocator can monitor a ratio of free space to total space corresponding to each logical block. The file system allocator can select a logical block based at least in part on the number of free sectors of the logical block. In some cases, the file system allocator can allocate the free sectors of the logical block in a sequential order.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: February 24, 2015
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Brian Sutton
  • Patent number: 8954697
    Abstract: A system configures page tables to cause an operating system to copy original page data in a data store when any one of the application processes makes a first write request for the original page data. The system detects a page fault from a memory management unit receiving a first write request from one of the application processes and creates the copy in physical memory to allow the application process to modify the page data copy. The other application processes have read access to the original page data. The system replaces the original page data in the data store with the page data copy in response to receiving a first synchronization request from the application process and updates a page table for one of the other application processes to configure access to the replaced page data in response to receiving a second synchronization request from the one other application process.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: February 10, 2015
    Assignee: Red Hat, Inc.
    Inventors: Neil R. T. Horman, Eric L. Paris, Jeffrey T. Layton