Including Plural Logical Address Spaces, Pages, Segments, Blocks Patents (Class 711/209)
  • Patent number: 11150819
    Abstract: A memory system includes a memory device including a plurality of memory blocks, and a controller in communication with the memory device to control an operation of the memory device, the controller allocating, among the plurality of memory blocks, a normal region and a redundancy region. The controller divides the normal region into a user region for storing user data, a user overprovisioning region for user data management, a map region for storing map data, and a map overprovisioning region for map data management, and divides the redundancy region into a reserved region and an additional map overprovisioning region, and wherein the reserved region, upon determination that a block in the normal region is a bad block, replaces the bad block.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11029869
    Abstract: Systems and methods are disclosed herein for multithreaded access to cloud storage. An exemplary method comprises creating a plurality of mount points by mounting, by a hardware processor, a plurality of file systems on a computer system, creating an image file on each of the plurality of mount points, instantiating, for each of the plurality of mount points, a block device on the image file, creating a union virtual block device that creates one or more stripes from each block device, delegating a request for accessing the union virtual block device, received from a client, to one or more block devices and merging a result of the request from each of the one or more block devices and providing the result to the client.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 8, 2021
    Assignee: Virtuozzo International GmbH
    Inventors: Maxim Patlasov, Alexey Kuznetzov, Pavel Emelyanov, Alexey Kobets
  • Patent number: 10956320
    Abstract: A memory system may include: a memory device including a plurality of memory dies; and a controller including a memory, and configured to: sequentially store, after storing data segments of sequential user data in the memory, the data segments of the sequential user data in the memory dies through interleaving; store in a first buffer region of the memory, after updating map segments of lower level map data corresponding to the storage of the data segments in the memory dies, the map segments of the lower level map data; and store in a second buffer region of the memory map segments of upper level map data corresponding to storage of the map segments of the lower level map data.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10949123
    Abstract: In one embodiment, a solid state device includes a controller and a non-volatile memory. The non-volatile memory includes a plurality of dies. Each die includes a plurality of planes. A first super-plane-block is structured from a first plane of the plurality of dies. A second super-plane-block is structured from a second plane of the plurality of dies. A plurality of memory operation instructions that, when executed by the controller, cause the controller to receive a first data stream, write the first data stream to the first super-plane-block, receive a second data stream, and write the second data stream to the second super-plane-block.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 16, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Liam Parker
  • Patent number: 10922241
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Patent number: 10909077
    Abstract: A system and method for utilizing slack space as another file system. The system identifies available slack space caused by storing data on a drive. The slack space is then made available as part of a separate file system. The separate file system allows for dynamic cluster sizes as the cluster size depends on the slack space of each individual file. The available space for the file system also dynamically changes based on the change in slack space caused by new data files being stored on the drive, edits to data files on the drive, or deletion of data files.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 2, 2021
    Assignee: PayPal, Inc.
    Inventor: Shlomi Boutnaru
  • Patent number: 10901912
    Abstract: An apparatus is provided that includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller is configured to access a global address table (GAT) that maps logical addresses of a host to physical addresses of the non-volatile memory, receive a request from the host to write first data to the non-volatile memory, determine that the first data comprises fragmented data that are not aligned to a minimum write unit of the non-volatile memory, and create an unaligned GAT page, wherein the unaligned GAT page comprises a logical-to-physical mapping for the first data.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramkumar Ramamurthy, Ramanathan Muthiah
  • Patent number: 10891055
    Abstract: Data address management systems, methods, devices and uses for minimizing interaction with data consumers' data on data storage devices, an embodiment comprising an external bus for communicatively interfacing the data storage system and data consumers; at least one storage medium components, each storage medium component comprising a plurality of storage locations having a unique storage location indicators; a translation layer module comprising a data address space having data addresses associable with storage location indicators; and a controller configured to store data in the storage locations and creating associations in the translation layer module between data addresses and the physical location indicators; wherein the data address space is accessible by the data consumer for addressing requests relating to data stored on the storage device and wherein the controller is configured to manipulate the arrangement of the data addresses in the data address space.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 12, 2021
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: Andrew Warfield, Timothy John Deegan, Keir Fraser, Daniel Stodden, Kevin Jamieson
  • Patent number: 10871921
    Abstract: One embodiment facilitates atomicity assurance for storing data and metadata in a data stream. The system receives a first stream of data to be written to a storage device, wherein the first stream includes a plurality of I/O requests associated with data and corresponding metadata. In response to determining that residual data associated with a preceding I/O request of the first stream exists in a data buffer: the system appends, to the residual data, a first portion of data from a current I/O request to obtain a first page of data; the system writes a remainder portion of the current I/O request to the data buffer to obtain current residual data; and the system writes the first page of data to the storage device. Thus, the system thereby facilitates atomicity assurance for storing the data and corresponding metadata of each I/O request of the first data stream.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 22, 2020
    Assignee: Alibaba Group Holding Limited
    Inventors: Shu Li, Ping Zhou
  • Patent number: 10834241
    Abstract: Apparatus and associated methods relating to data packet deparsing include an editing circuit configured to perform one or more predetermined editing operations on headers of an incoming data packet step by step without extracting all headers from the incoming data packet. In an illustrative example, an editor circuit may include an updating circuit configured to receive the data packet and update a header in the data packet. The editor circuit may also include a removal circuit configured to remove a header from the data packet. The editor circuit may also include an insertion circuit configured to insert one or more consecutive headers to the data packet. A state machine may be configured to enable or disable the updating circuit, the removal circuit, and/or the insertion circuit based on the predetermined editing operations. By using the editing circuit, packet deparsing may be performed with less hardware resources and low latency.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 10, 2020
    Assignee: XILINX, INC.
    Inventors: Ian McBryan, Gordon J. Brebner, Jaime Herrera, Rowan Lyons
  • Patent number: 10826840
    Abstract: Some embodiments provide a method for a packet processing pipeline of a network forwarding integrated circuit. The method stores two copies of a stateful table used by the packet processing pipeline. The stateful table is modified according to data processed by the packet processing pipeline. Upon receiving data to write to the stateful table, the method generates (i) a first copy of the received data along with an indicator for a first one of the copies of the stateful table and (ii) a second copy of the received data along with an indicator for a second one of the copies of the stateful table. The method sends the first copy of the received data into the packet processing pipeline before sending the second copy of the received data into the packet processing pipeline.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 3, 2020
    Assignee: Barefoot Networks, Inc.
    Inventors: Jay Evan Scott Peterson, Michael Gregory Ferrara, Anurag Agrawal, Patrick Bosshart, Jeongkeun Lee
  • Patent number: 10747563
    Abstract: Systems and techniques are described for optimizing memory sharing. A described technique includes grouping virtual machines (VMs) into groups including a first group; initializing a first VM in the first group, wherein initializing the first VM includes identifying, for each of one or more first memory pages for the first VM, a respective base address for storing the first memory page using an address randomization technique, and storing, for each of the one or more first memory pages, data associating the first memory page with the respective base address for the first group, and initializing a second VM while the first VM is active, wherein initializing the second VM includes determining that the second VM is a member of the first group, and in response, storing one or more second memory pages for the second VM using the respective base addresses stored for the first group.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 18, 2020
    Assignee: VMware, Inc.
    Inventors: Guang Gong, Qi Kang, Le Tian, Chengxiao Wang, Yimin Zhao, Shiyao Yuan
  • Patent number: 10740026
    Abstract: Recording an indicator of time at which a super block is erased, recording an indicator of time at which a first page of the super block is programmed, and recording an indicator of time at which a last page of the super block is programmed.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kevin R. Brandt
  • Patent number: 10733316
    Abstract: Techniques are described herein for allowing a container DBMS to impose restrictions, on a per-pluggable-database basis, on operations based on the pluggable database to which the users that request the operations belong. In one embodiment, lockdown profiles can be created and mapped to pluggable databases. Lockdown profiles specify PDB-wide restrictions on operations. The restrictions may apply to all operations of a given type, may apply to specific features, may require use of specific parameter values, etc. All users that belong to a pluggable database are restricted by the restrictions specified in the lockdown profile to which their pluggable database is mapped, unless the lockdown profile has a user-specific exemption for them. Bitmaps and/or hash tables may be used to more quickly determine, at query runtime, whether a query violates any profile-specified restrictions. Execution of queries that violate any profile-specified restrictions is prevented.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: August 4, 2020
    Assignee: Oracle International Corporation
    Inventors: Prashanth Shanthaveerappa, Sanket Jain, Kumar Rajamani, Andre Kruglikov
  • Patent number: 10684955
    Abstract: Examples described herein include systems and methods which include an apparatus comprising a memory array including a plurality of memory cells and a memory controller coupled to the memory array. The memory controller comprises a memory mapper configured to configure a memory map on the basis of a memory command associated with a memory access operation. The memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array. For example, the specific sequence of memory access instructions for a diagonal memory command comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fa-Long Luo, Tamara Schmitz, Jeremy Chritz, Jaime Cummins
  • Patent number: 10671528
    Abstract: A memory system may comprise: a memory device including a plurality of memory dies; and a controller including a first memory, Wherein the controller may store data segments of user data, corresponding to a plurality of commands received from a host, in the first memory, controls the memory device to sequentially store the data segments in the memory dies through interleaving, may update map segments of map data corresponding to storage of the data segments in the memory dies, may store the map segments in the first memory, controls the memory device to store the map segments stored in the first memory in the memory dies, and may assist the host in storing the map segments, stored in the first memory, in a second memory in the host.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hyniX Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10628308
    Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: April 21, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Kunal Desai, Satyaki Mukherjee, Abhinav Mittal, Siddharth Kamdar, Umesh Rao, Vinayak Shrivastava
  • Patent number: 10628613
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for secure memory page mapping in a virtual machine (VM) environment. The system may include a processor configured to execute a virtual machine monitor (VMM). The VMM may be configured to maintain a table of cryptographic keys and associate a token with one of the memory pages to be mapped from a guest linear address (GLA) to a guest physical address (GPA). The token may include a key identifier (key ID) associated with one of the cryptographic keys, and an authentication code based on the GLA, the GPA, and one of the cryptographic keys. The system may also include a page walk processor configured to validate the token to indicate that the memory page associated with the token is authorized to be mapped from the GLA to the GPA.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventor: Michael LeMay
  • Patent number: 10565101
    Abstract: For storing data in a storage device, a storage allocation request may be received. The storage allocation request may include a logical offset of data to be stored. Further, a chunk size of the storage device and a device offset for a free region on the storage device may be received. An offset value may be computed based on the chunk size, file system block size, the device offset, and the logical offset. A device start address, for storing the data in response to the storage allocation request, can be determined by offsetting the device offset with the offset value.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 18, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Narayanan Ananthakrishnan Nellayi, Shyamalendu Sarkar, Subhakar Vipparti
  • Patent number: 10558611
    Abstract: Embodiments relate to a computer system, computer program product, and method to process complex files, and specifically, to support read and write requests of a multi-object file. Upon receipt of a file, a computer system parses the file into two or more logical objects. Each logical object has an associated or inherent characteristic. Each of the logical objects is matched to a storage tier in a multi-tier storage array. Each logical object is then assigned to a tier based on one or more object characteristics in the matched storage tier, and stored in a decomposed format. In addition, an identification of each logical object, and the object assignment, is recorded in an index.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dean Hildebrand, Vasily Tarasov
  • Patent number: 10552308
    Abstract: Techniques for determining whether processes are running on a computing device are described. As an example, a detection process may create a virtual mapping of data to memory of the computing device. The detection process may access a file system storing special files including attributes of virtual memory mappings. The detection process may analyze the attributes of the virtual memory mapping, such as an amount of data stored or shared by the memory mapping, to determine that another process is sharing the memory mapping with the detection process. The detection process may send data to a server associated with the computing device indicating that a process other than the detection process is operating on the computing device.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 4, 2020
    Assignee: Square, Inc.
    Inventor: Christopher Rohlf
  • Patent number: 10540235
    Abstract: The disclosed techniques include generation of a single index table when backing up data in a first backup format to a backup storage system that uses a second backup format. Using the single index table, a query for a data item can be answered by searching the single index table. The single index table avoids having to search through multiple index tables, each corresponding to a different backup format that may be used for backing up the searched data item.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 21, 2020
    Assignee: Commvault Systems, Inc.
    Inventor: Manoj Kumar Vijayan
  • Patent number: 10528435
    Abstract: Provided are a method, system, and computer program product in which a computational device stores a data structure that includes identifications of a plurality of volumes and identifications of one or more time locks associated with each of the plurality of volumes. The data structure is indexed into, to determine whether an input/output (I/O) operation from a host with respect to a volume is to be permitted.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Carol S. Mellgren
  • Patent number: 10521156
    Abstract: A management apparatus of a multi-solid state disk (SSD) system implemented by a computer is provided. The management apparatus of the multi-SSD system may include a first SSD group including a plurality of SSDs arranged in rows or columns and configured to execute a received write command using segments in the plurality of SSDs, a second SSD group including a plurality of SSDs arranged in rows or columns and configured to execute a read command for valid data in the plurality of SSDs, and a manager configured to copy a valid page in the second SSD group while a write command for the first SSD group being executed and to erase all data in the second SSD group when the copying is completed.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 31, 2019
    Assignee: UNIST (Ulsan National Institute of Science and Technology)
    Inventors: Sam H Noh, Byungsuck Kim, Jaeho Kim, KwangHyun Lim
  • Patent number: 10482039
    Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: November 19, 2019
    Assignee: Montage Technology Co., Ltd.
    Inventors: Shuna Xu, Guobing Mo, Cheng-Tie Chen
  • Patent number: 10459642
    Abstract: There is provided a method and device for data replication. The method comprises: obtaining, in a network interface card, data segments by segmenting input first data; determining, in the network interface card, fingerprints corresponding to the data segments; and comparing, in a central processing unit, the fingerprints of the data segments with existing fingerprints corresponding to processed data segments, and determining, based on a result of the comparing, whether to de-duplicate the data segments corresponding to the fingerprints, to perform the data replication.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 29, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Kun Wang, Colin Yong Zou, Sean Cheng Ye, Lyne Yuwei Li
  • Patent number: 10437476
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: receive, via the host interface, a request from a host to allocate a namespace of a quantity of non-volatile memory; generate, in response to the request, a namespace map identifying a plurality of blocks of addresses having a same predetermined block size, and a partial block of addresses having a size smaller than the predetermined block size; and convert, using the namespace map, logical addresses in the namespace communicated from the host to physical addresses for the quantity of the non-volatile memory. For example, the request for allocating the namespace can be in accordance with an NVMe protocol.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 8, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Alex Frolikov
  • Patent number: 10430280
    Abstract: The disclosed techniques include generation of a single index table when backing up data in a first backup format to a backup storage system that uses a second backup format. Using the single index table, a query for a data item can be answered by searching the single index table. The single index table avoids having to search through multiple index tables, each corresponding to a different backup format that may be used for backing up the searched data item.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 1, 2019
    Assignee: Commvault Systems, Inc.
    Inventor: Manoj Kumar Vijayan
  • Patent number: 10369473
    Abstract: A method for providing virtual world functionality to a user of a base virtual world having base virtual world functionality and a base world list of base virtual world users, includes providing a virtual world layer, communicating to the base virtual world that the virtual world layer will overlay the base virtual world and adding the virtual world layer to the base world list in order to register the virtual world layer with the base virtual world.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: George R. Dolbier, Rick A. Hamilton, II, Neil A. Katz, Brian M. O'Connell
  • Patent number: 10331577
    Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: June 25, 2019
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Shuna Xu, Guobing Mo, Cheng-Tie Chen
  • Patent number: 10303620
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
  • Patent number: 10248556
    Abstract: Computer-implemented methods and systems for managing data in one or more data storage media are provided. An example method may comprise creating a data structure within the data storage media. The data structure includes a plurality of memory pages, each page comprising a plurality of sessions, and each session comprising a header and a plurality of data objects. The method also comprises enabling writing data to the data storage medium, in response to routine requests, such that the data is recorded to the one or more data objects nearest the current location of a virtual cursor. When a data management operation is performed, the virtual cursor is moved within a single page in a single direction.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 2, 2019
    Assignee: EXABLOX CORPORATION
    Inventor: Frank E. Barrus
  • Patent number: 10203954
    Abstract: Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Jesus Corbal, Robert Valentine, Bret L. Toll, Mark J. Charney
  • Patent number: 10185828
    Abstract: Systems and methods are provided that may be implemented to securely load Unified Extensible Firmware Interface (UEFI) images (e.g., UEFI Applications, UEFI Drivers, UEFI firmware volumes, etc.) onto an information handling system from an authenticated (e.g., OEM authenticated) hardware image source device or “IO store” (e.g., such as USB device, network file system device, PCIe device, network storage, shared storage, dynamic RAM disk, etc.) based on a UEFI virtual device path that is mapped to an authenticated hardware device path that is established for the authenticated hardware image source device.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 22, 2019
    Assignee: Dell Products L.P.
    Inventors: Sumanth Vidyadhara, Chandrasekhar Puthillathe, Aniruddha Herekar
  • Patent number: 10162548
    Abstract: A distributed network of storage elements (DNSE) is provided in which the physical capacity of each drive is split into a set of equal sized logical splits which are individually protected within the DNSE using separate RAID groups. To reduce restoration latency, members of the RAID groups having a member in common on a given drive are spread within the DNSE to minimize the number of sets of drives within the DNSE that have RAID members in common. By causing the splits to be protected by RAID groups, restoration of the splits may occur in parallel involving multiple drives within the DNSE. By minimizing the overlap between RAID members on various drives, failure of a given drive will not require multiple reads from another drive in the DNSE. Likewise, spare splits are distributed to enable write recovery to be performed in parallel on multiple drives within the DNSE.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 25, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Edward S. Robins, Kevin Granlund, Seema Pai, Evgeny Malkevich, Stephen Richard Ives, Roii Raz, Barak Bejerano
  • Patent number: 10133640
    Abstract: A storage apparatus includes a first storage device and a processor. The first storage device is configured to store therein first information blocks used to recover second information blocks stored in a second storage device. The processor is configured to read the first information blocks from the first storage device in an order of addresses of storage areas of the first storage device. The processor is configured to output part of the first information blocks which have been read from the first storage device to respective recovery destinations of the second information blocks to recover the second information blocks step by step.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: November 20, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Kensuke Shiozawa
  • Patent number: 10102218
    Abstract: A file system allows a different checksum algorithm to be used for different extents of a file system object independently of other extents of the file system object. The checksum algorithm can be a selectable attribute of an extent or range of extents of a file system object, such that some extents of a file system object can use a first checksum algorithm, while other extents of the file system object can use a second checksum algorithm. An extent of the file system object also may have no associated checksum algorithm. The file system stores, for each extent of a file system object, data indicating a checksum for the extent and an indication of any checksum algorithm used for the extent.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 16, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chesong Lee, Raj Das, Cornel Rat, William Tipton
  • Patent number: 10007609
    Abstract: A data processing system includes a plurality of virtual machines each having associated memory pages; a shared memory page cache that is accessible by each of the plurality of virtual machines; and a global hash map that is accessible by each of the plurality of virtual machines. The data processing system is configured such that, for a particular memory page stored in the shared memory page cache that is associated with two or more of the plurality of virtual machines, there is a single key stored in the global hash map that identifies at least a storage location in the shared memory page cache of the particular memory page. The system can be embodied at least partially in a cloud computing system.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Parijat Dube, Xavier R. Guerin, Seetharami R. Seelam
  • Patent number: 9912591
    Abstract: An exact-match flow table structure of an integrated circuit stores flow entries. Each flow entry includes a Flow Id and an action value. Each Flow Id is a multi-bit digital value that uniquely identifies a flow. A Flow Id does not include any wildcard indictor. The flow table structure cannot and does not store an indicator that any particular part of a packet should be matched against any part of a Flow Id. In one example, a packet is received onto the integrated circuit. A Flow Id is generated from the packet. If the flow table structure determines that the Flow Id is a bit-by-bit exact-match of any Flow Id of any stored flow entry, then the packet is handled according to the action value of the flow entry. If, on the other hand, there is not exact-match, then a miss indication is output from the integrated circuit.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 6, 2018
    Assignee: Netronome Systems, Inc.
    Inventors: Gavin J. Stark, Stuart C. Wray
  • Patent number: 9852081
    Abstract: A multi-dimension engine, connected to a system TLB, generates sequences of addresses to request page address translation prefetch requests in advance of predictable accesses to elements within data arrays. Prefetch requests are filtered to avoid redundant requests of translations to the same page. Prefetch requests run ahead of data accesses but are tethered to within a reasonable range. The number of pending prefetches are limited. A system TLB stores a number of translations, the number being relative to the dimensions of the range of elements accessed from within the data array.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: December 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Laurent Moll
  • Patent number: 9778874
    Abstract: The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated with the write command, determining if a transformation value of the data exists in a transformation table, and responsive to a determination that the transformation value does not exist in the transformation table, writing the data associated with the write command to a memory device.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventor: John C. Rudelic
  • Patent number: 9740625
    Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. For a system configuration that includes partitions, the translation mechanism to be used for a partition or a portion thereof is selectable and may be different for different partitions or even portions within a partition.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9740624
    Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. For a system configuration that includes partitions, the translation mechanism to be used for a partition or a portion thereof is selectable and may be different for different partitions or even portions within a partition.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 9734051
    Abstract: Example apparatus and methods provide improved reclamation, garbage collection (GC) and defragmentation (defrag) for data storage devices including solid state drives (SSD) or shingled magnetic recording (SMR) drives. An erasure code (EC) layer that facilitates logically or physically erasing data from the SSD or SMR as a comprehensive GC or defrag is added to the SSD or SMR. Erased data may be selectively recreated from the EC layer as needed. Pre-planned EC write zones may be established to further optimize GC and defrag. Recreated data may be written to selected locations to further optimize SSD and SMR performance. Erasure code data may be distributed to co-operating devices to further improve GC or defrag. Example apparatus and methods may also facilitate writing data to an SMR drive using tape or VTL applications or processes and providing a pseudo virtual tape library on the SMR drive.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: August 15, 2017
    Assignee: Quantum Corporation
    Inventors: Roderick Wideman, Don Doerner
  • Patent number: 9715350
    Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9658792
    Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: May 23, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
  • Patent number: 9639464
    Abstract: A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: May 2, 2017
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Haggai Eran, Shachar Raindel, Liran Liss, Noam Bloch
  • Patent number: 9632953
    Abstract: An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Assaf Shacham, Dolev Raviv, David Teb
  • Patent number: 9628438
    Abstract: Computer-implemented methods and systems for managing data objects within a computer network infrastructure that facilitate more efficient and reliable data storage and access are provided. An exemplary method may comprise establishing a physical identifier for each storage resource. A plurality of unique virtual identifiers for each storage resource is generated based on the physical identifier. The plurality of unique virtual identifiers is stored in a consistent ring namespace accessible to every node. An object identifier associated with a location of a data object to be stored in a storage resource is generated. The object identifier is mapped to the consistent ring namespace. The method may also include enabling traversing the consistent ring namespace from any node in the computer network to locate and access the data object.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: April 18, 2017
    Assignee: EXABLOX
    Inventors: Charles Hardin, Sridhar Subramaniam, Tad Hunt, Frank E. Barrus
  • Patent number: 9569243
    Abstract: Embodiments disclosed herein generally include a computer-implemented method, computer program product, and system to facilitate offloaded and parallelized direct memory access (DMA) translation table operations. The method includes a hypervisor requesting a lease on an auxiliary parallel processing element assigned to a first virtual machine hosted by the hypervisor. The method further includes receiving a grant of the lease, whereby ownership of the auxiliary parallel processing element is transferred from the first virtual machine to the hypervisor. The method further includes, during the lease, providing a predefined program to execute on the auxiliary parallel processing element in order to perform a desired operation on the hypervisor DMA translation table and with parallelism. The method further includes, upon completion of the predefined program, terminating the lease by the hypervisor, whereby ownership of the auxiliary parallel processing element is returned to the first virtual machine.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Justin K. King