Including Plural Logical Address Spaces, Pages, Segments, Blocks Patents (Class 711/209)
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Patent number: 8925074Abstract: Incoming files are examined to detect abnormal files. The incoming files may be examined for a weak file structure, such as a weak file format structure or a weak file data structure, to detect abnormal files. A weak file structure includes file structures that do not conform to the file format of the file yet still loadable by a file loader of the file format. The incoming files may also be examined for suspicious loading in memory to detect abnormal files.Type: GrantFiled: July 17, 2012Date of Patent: December 30, 2014Assignee: Trend Micro IncorporatedInventor: Chik-Kun Ho
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Patent number: 8918621Abstract: The performance and efficiency of file systems for data allocation access in random-access storage media is enhanced by isolating block addresses from other metadata and the actual data itself in a separate address space. Block addresses are stored in memory and file system structures that are separate from those structures that store other metadata and the actual data. This affords faster address lookup and access to data storage locations, and more efficient storage allocation and accessing algorithms. The block address isolation may be implemented in separate logic, in a hardware controller for a storage drive, or in software in a storage hierarchy.Type: GrantFiled: September 29, 2011Date of Patent: December 23, 2014Assignee: EMC CorporationInventor: Cimarron D. Taylor
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Patent number: 8909900Abstract: A storage device and method for updating data stored in a partition of the storage device are provided. In one embodiment, a storage device is provided that contains a logical-to-physical address map and a memory with a first partition storing original data and a second partition. The storage device receives from a host device (i) a command to write updated data to a first logical address and (ii) a signature for verifying integrity of the updated data, wherein the first logical address is mapped to a physical address of the first partition. The storage device then stores the updated data in the second partition instead of the first partition and attempts to verify the signature of the updated data. If the attempt to verify the signature is successful, the storage device updates the logical-to-physical address map to map the first logical address to a physical address of the second partition.Type: GrantFiled: November 23, 2011Date of Patent: December 9, 2014Assignee: SanDisk IL Ltd.Inventors: Boris Dolgunov, Nir Ekhauz, Nir Paz
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Patent number: 8904096Abstract: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.Type: GrantFiled: August 9, 2013Date of Patent: December 2, 2014Assignee: Sony CorporationInventors: Toshiyuki Nishihara, Yoshio Sakai
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Publication number: 20140351485Abstract: An approach is described to overcome the rapid consumption of available flash space when frequently modifying files stored on the flash space. This “differential” sector approach determines the correlation between the new content and the old content, and saves only the “delta” part of the old and the new content to the sectorized memory device. A predetermined threshold can be used to determine whether to use the “differential” sector approach or the fixed sector approach, based on the amount of data change in a given memory access request.Type: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Applicant: Spansion LLCInventors: Shulan DENG, Stephan Rosner, Venkataraman Natarajan
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Patent number: 8898374Abstract: A flash memory device includes a flash memory and a controller. The flash memory includes a single level memory module and a multi level memory module. The single level memory module includes a first data bus and at least one single level cell flash memory. Each memory cell of the single level cell flash memory stores one bit of data. The multi level memory module includes a second data bus and at least one multi level cell flash memory. Each memory cell of the multi level cell flash memory stores more than one bit of data. The first data bus is coupled to the second data bus. During a write operation, the controller writes data to the single level memory module, and the single level memory module further transmits the data to the multi level memory module through the first and second data buses coupled therebetween without passing the data through the controller.Type: GrantFiled: July 21, 2011Date of Patent: November 25, 2014Assignee: Silicon Motion, Inc.Inventor: Tsung-Chieh Yang
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Patent number: 8898423Abstract: A data storage system is disclosed that utilizes a high performance caching architecture. In one embodiment, the caching architecture utilizes a cache table, such as a lookup table, for referencing or storing host data units that are cached or are candidates for being cached in the solid-state memory. Further, the caching architecture maintains a segment control list that specifies associations between particular cache table entries and particular data segments. Such separation of activities related to the implementation of a caching policy from activities related to storing cached data and candidate data provides robustness and scalability while improving performance.Type: GrantFiled: January 31, 2012Date of Patent: November 25, 2014Assignee: Western Digital Technologies, Inc.Inventors: Chandra M. Guda, Michael Ainsworth, Choo-Bhin Ong, Marc-Angelo P. Carino
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Patent number: 8892847Abstract: The storage apparatus comprises a storage unit storing data read/written by the host apparatus, and a control unit controlling writing of the data to the storage unit. The control unit configures one or more pools from the storage unit and divides one of the pools into first pages having an area of a first size and divides the first pages into second pages having the second area, and manages the pages, manages a data storage area of a first volume storing the data by using the first-size area and manages a data storage area of a second volume storing the data by using the second-size area, assigns the first page to the data storage area of the first volume, and assigns the first page in units of the second volume and assigns the second page obtained by dividing the first page to the data storage area of the second volume.Type: GrantFiled: April 5, 2011Date of Patent: November 18, 2014Assignee: Hitachi, Ltd.Inventors: Miho Imazaki, Yusuke Nonaka
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Patent number: 8885203Abstract: An optical reading device has an optical reading unit having optical elements disposed in a line that reads a medium; a storage unit having a ring buffer formed in the storage space; and a control unit that writes scanned data read by the optical reading unit to the ring buffer, reads the scanned data written to the ring buffer, and transfers the scanned data that was read. The control unit also manages positions in the ring buffer for writing and reading the scanned data using a write pointer denoting the position for writing the scanned data to the ring buffer, and a read pointer denoting the position of scanned data that has not been read.Type: GrantFiled: March 9, 2012Date of Patent: November 11, 2014Assignee: Seiko Epson CorporationInventor: Kenji Asada
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Publication number: 20140331024Abstract: A method of dynamically adjusting a mapping manner for a non-volatile memory includes mapping a plurality of logical addresses to a plurality of physical addresses by a first mapping unit; storing data in the non-volatile memory by the first mapping unit; and mapping at least one logical address to at least one physical address by a second mapping unit according to the stored data.Type: ApplicationFiled: August 7, 2013Publication date: November 6, 2014Applicant: Skymedi CorporationInventors: Yi-Cheng Wu, Yi-Chun Liu
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Patent number: 8880803Abstract: A generation-code storage unit stores therein a generation code in association with identification information for identifying the block datum. A generation-code managing unit assigns a new generation code to a detected consecutive data set and any block datum included in writing data other than the consecutive data set and stores the assigned generation code in the generation-code storage unit. A data writing unit adds the new generation code to the block datum or consecutive data set included in the writing data and writes it to a storage unit. A determining unit determines whether the generation code added to a read block datum or consecutive data set is accordant with the generation code of the read block datum or consecutive data set stored in the generation-code storage unit. A data transmitting unit transmits, when the generation codes are accordant, the read block datum or consecutive data set.Type: GrantFiled: December 20, 2011Date of Patent: November 4, 2014Assignee: Fujitsu LimitedInventor: Yuji Noda
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Patent number: 8862860Abstract: Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks comprising a plurality of sectors, assign partial page blocks from the plurality of blocks for memory storage, fill some of the sectors by storing data bits associated with the allocation request in the at least one of the plurality of sectors, determine that the sectors are full, assigning a full page block from the plurality of blocks, and transfer the data bits associated with the allocation request from the partial page blocks to the full page block. Other apparatus, systems, and methods are disclosed.Type: GrantFiled: May 26, 2011Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Viet Ly, Michael Murray
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Patent number: 8856438Abstract: A disk drive is disclosed that utilizes an additional address mapping layer between logical addresses used by a host system and physical locations in the disk drive. Physical locations configured to store metadata information can be excluded from the additional address mapping layer. As a result, a reduced size translation table can be maintained by the disk drive. Improved performance, reduced costs, and improved security can thereby be attained.Type: GrantFiled: December 9, 2011Date of Patent: October 7, 2014Assignee: Western Digital Technologies, Inc.Inventors: Nicholas M. Warner, Marcus A. Carlson, David C. Pruett
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Patent number: 8856425Abstract: A method for performing meta block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: utilizing a meta block mapping table to store block grouping relationships respectively corresponding to a plurality of meta blocks, where blocks in each meta block respectively correspond to the channels; and when it is detected that a specific block corresponding to a specific channel within a meta block does not have remaining space for programming, according to the meta block mapping table, utilizing at least one blank block corresponding to the specific channel within at least one other meta block as extension of the specific block, for use of further programming. An associated memory device and a controller thereof are also provided.Type: GrantFiled: July 12, 2011Date of Patent: October 7, 2014Assignee: Silicon Motion Inc.Inventor: Yang-Chih Shen
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Patent number: 8856463Abstract: The disclosed system and method enhances performance of pipelined data transactions involving FIFO buffers by implementing a transaction length indicator in a transaction header. The length indicator in the header is formed by components coupled to a memory controller through FIFO buffers. The memory controller uses the length indicator to execute pipelined data transfers at relatively high speeds without causing additional inadvertent shifts or indexes in the FIFO buffer being read. The system and method can be applied to any memory type in general, and avoids the use of additional control signals or added complexity or size in the memory controller.Type: GrantFiled: December 16, 2008Date of Patent: October 7, 2014Inventor: Frank Rau
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Patent number: 8856490Abstract: A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.Type: GrantFiled: September 14, 2012Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Jon K. Kriegel, Martin Ohmacht, Burkhard Steinmacher-Burow
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Patent number: 8850161Abstract: Methods are provided for efficiently storing data to a data storage device or subsystem. The data storage device may be a Solid-State Device (SSD), and may be implemented as part of a RAID (Redundant Array of Independent Disks) or other subsystem. When existing data is read and updated, and must be re-stored, the data is assembled and stored as if it were new data, and is written in a sequential manner, instead of being written to the same storage location. A newer generation number distinguishes it from the previous version. If the storage subsystem employs data striping, stripe size may be matched with the size of a logical collection of data (e.g., an extent), so that each such logical collection of data is wholly stored on just device in the storage subsystem. Concurrent device access may be supported by concurrently writing substripes of data to each device/extent.Type: GrantFiled: October 13, 2010Date of Patent: September 30, 2014Assignee: Riverbed Technology, Inc.Inventors: Robert Punkunus, Kallol Mandal, Sumanth Sukumar, Nitin Jain
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Patent number: 8850160Abstract: Systems and methods are disclosed for adaptive writing behavior for a system having non-volatile memory (“NVM”). A memory interface of a system can be configured to determine whether a write preference of the system is skip-sequential. In response to determining that the write preference is skip-sequential, the memory interface can sequentially program data to a first set of pages of a block of the NVM. In addition, the memory interface can sequentially pre-merge gaps between the first set of pages with one or more pages of a data block. Moreover, the memory interface can be configured to switch to an alternative programming state in response to determining that at least one condition has been satisfied. For example, the memory interface can stop programming data sequentially, and instead program data in the order that the data is received from a file system.Type: GrantFiled: August 23, 2010Date of Patent: September 30, 2014Assignee: Apple Inc.Inventors: Daniel J. Post, Brian Sutton
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Patent number: 8843727Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.Type: GrantFiled: September 30, 2004Date of Patent: September 23, 2014Assignee: Intel CorporationInventors: Ioannis Schoinas, Gilbert Neiger, Rajesh Madukkarumukumana, Ku-jei King, Richard Uhlig, Achmed Rumi Zahir, Koichi Yamada
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Patent number: 8838936Abstract: A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host, the method including receiving, by the processor, data for storing at a physical address in the non-volatile memory, the data being associated with a logical address of the host, storing, by the processor, the physical address in a first LtoP zone of a plurality of LtoP zones of the LtoP table, the LtoP table being stored in the volatile memory, adding, by the processor, the first LtoP zone to a list of modified zones, and storing, by the processor, a second LtoP zone of the plurality of LtoP zones in the non-volatile memory when a size of the list of modified zones exceeds a threshold.Type: GrantFiled: November 27, 2013Date of Patent: September 16, 2014Assignee: NXGN Data, Inc.Inventors: Nader Salessi, Joao Alcantara
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Patent number: 8819088Abstract: Techniques are provided for accessing sector data. An embedded storage function is received. One or more data management functions are generated in response to receiving the embedded storage function. The one or more data management functions are invoked to retrieve the sector data from a sector table.Type: GrantFiled: July 14, 2005Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Balakrishna Raghavendra Iyer, Lin S. Qiao, Aamer Sachedina
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Patent number: 8819389Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.Type: GrantFiled: April 25, 2013Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Charles J. Archer, Gary R. Ricard
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Patent number: 8819291Abstract: A set of logical extents, each having compressed logical tracks of data, is mapped to a head physical extent and, if the head physical extent is determined to have been filled, to at least one overflow extent having spatial proximity to the head physical extent. Pursuant to at least one subsequent write operation and destage operation, the at least one subsequent write operation and destage operation determined to be associated with the head physical extent, the write operation is mapped to one of the head physical extent, the at least one overflow extent, and an additional extent having spatial proximity to the at least one overflow extent.Type: GrantFiled: April 19, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Matthew J. Kalos, Gail A. Spear
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Patent number: 8812756Abstract: A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.Type: GrantFiled: October 1, 2010Date of Patent: August 19, 2014Assignee: Phison Electronics Corp.Inventor: Ching-Wen Chang
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Publication number: 20140229703Abstract: A control unit of an information processing apparatus extracts an address string of memory access generated in a processor executing a program in an arbitrary computer, divides the address string into a plurality of sections. And the control unit searches an address pattern accessible by an address generator that converts a command to be input into an address string including a plurality of address block numbers by a predetermined algorithm for the each divided section.Type: ApplicationFiled: November 11, 2011Publication date: August 14, 2014Applicant: NEC CORPORATIONInventor: Nozomi Ishihara
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Patent number: 8806172Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.Type: GrantFiled: March 15, 2013Date of Patent: August 12, 2014Assignee: Intel CorporationInventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
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Patent number: 8787101Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: GrantFiled: August 5, 2013Date of Patent: July 22, 2014Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
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Patent number: 8788740Abstract: A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data.Type: GrantFiled: December 21, 2007Date of Patent: July 22, 2014Assignee: Spansion LLCInventors: Sunil Atri, Robert Brent France, Walter Allen
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Patent number: 8788790Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.Type: GrantFiled: December 7, 2012Date of Patent: July 22, 2014Assignee: Intel CorporationInventors: Jason W Brandt, Sanjoy K Mondal, Richard A Uhlig, Gilbert Neiger, Robert T George
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Publication number: 20140201496Abstract: Embodiments of the disclosure include a method for reserving large pages in a large frame area (LFAREA) of a main memory. The method includes pre-scanning a plurality of storage increments and counting a number of available large pages that are online and issuing a message that indicates the number of available large pages. The method also includes receiving and parsing an LFAREA request including a target number of large pages to be reserved. The method further includes calculating an optimal number of large pages to be reserved, based upon the target number of available pages and a system limit. The method includes determining if the LFAREA request is valid and if the LFAREA request can be satisfied and scanning the plurality of the storage increments and reserving the optimal number of pages in the LFAREA.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alfred F. Foster, David Hom, Charles E. Mari, Matthew J. Mauriello, Robert Miller, Jr., Mariama Ndoye, Scott B. Tuttle, Elpida Tzortzatos
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Patent number: 8782338Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.Type: GrantFiled: October 1, 2013Date of Patent: July 15, 2014Assignee: STMicroelectronics (Rousset) SASInventor: Hubert Rousseau
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Patent number: 8775772Abstract: Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.Type: GrantFiled: December 21, 2009Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: James A. Fuxa, Lance W. Shelton, Justin C. Haggard
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Patent number: 8769356Abstract: A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.Type: GrantFiled: August 9, 2012Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Soo Yu, Chul-Woo Park, Uk-Song Kang, Joo-Sun Choi, Hong-Sun Hwang, Jong-Pil Son
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Patent number: 8762685Abstract: A data writing method for writing updated data from a host into a memory module is provided. Herein, some physical units of the memory module are gotten to be global random physical units for storing data from the host. The method includes determining whether the updated data is sequential data and determining whether a logical page corresponding to the updated data is a start logical page. The method further includes getting a blank physical unit from the physical units as a new global random physical unit and writing the updated data into the new global random physical unit when the updated data is the sequential data and the logical page corresponding to the updated data is the start logical page. Accordingly, the method can write updated data belonging to the same logical unit into the same physical unit, thereby shortening the time for executing write commands.Type: GrantFiled: March 2, 2011Date of Patent: June 24, 2014Assignee: Phison Electronics Corp.Inventor: Chih-Kang Yeh
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Patent number: 8756399Abstract: Method and apparatus for mutably associating logical block addresses to physical blocks. A physical storage space is apportioned into one or more bands. A logical block address (LBA) from a logical space is assigned to one of the bands, and the LBA is mutably associated with a particular physical block (sector) at an associated physical block address (PBA) within the assigned band. Such mutable association preferably includes the writing of user data associated with the LBA to the associated physical sector. During a subsequent operation, user data associated with the LBA can be stored in a second physical sector in the assigned band. The physical storage space preferably comprises a magnetic recording medium, and some or all of the bands preferably utilize overlapping tracks. The logical space is preferably divided into sets of sequential LBAs, with non-adjacent sets assigned to the same band. Map data are used to track sector allocation status in each band.Type: GrantFiled: January 25, 2006Date of Patent: June 17, 2014Assignee: Seagate Technology LLCInventor: Timothy R. Feldman
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Patent number: 8751598Abstract: Described herein is a novel technique for implementing an unordered delivery (UOD) of write logs between nodes in a cluster to optimize processing resources during log mirroring operations. A mirroring entry may be generated for each write log in a local log cache constituting the write log and an order indicator for the write log. The order indicator may be, for instance, a storage location of the write log in the local log cache. The mirroring entry may then be forwarded across a network from the local node to the remote node, where the mirroring entry may be stored at a next available location of an interim cache at the remote node independent of the write log storage location in the local log cache.Type: GrantFiled: November 3, 2010Date of Patent: June 10, 2014Assignee: NetApp, Inc.Inventor: Hari Shankar
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Patent number: 8745357Abstract: A method and a corresponding apparatus provide for remapping for wear leveling of a memory. The method is implemented as logic and includes the steps of receiving a memory operation, the memory operation including a logical memory address; dividing the logical address into a logical block address portion, a logical line address portion, and a logical subline address portion; translating the logical block address portion into a physical block address; selecting a line remap key; applying the line remap key to the logical line address portion to produce a physical line address; producing a physical subline address portion; and combining the physical block, line, and subline address portions to produce a physical address for the memory operation.Type: GrantFiled: November 30, 2009Date of Patent: June 3, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Joseph A. Tucek, Eric A. Anderson
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Patent number: 8745349Abstract: A detection module selects logically adjacent first and second control areas of a cluster. The detection module further determines that the first and second control areas satisfy a migration test wherein the first control area has free space exceeding a free threshold, the free space is at least equal to a space requirement for each second control area control interval, and the second control area has fewer control intervals than a control interval threshold. In addition, a copy module copies each second control area control interval to the first control area in response to determining that the first and second control areas satisfy the migration test.Type: GrantFiled: July 12, 2011Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Douglas L. Lehr, Franklin E. McCune, David C. Reed, Max D. Smith
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Patent number: 8738889Abstract: Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes receiving an instruction requiring an address translation; initiating, in response to receiving the instruction, a page walk from a page table pointed to by the contents of a page table pointer storage location; finding, during the page walk, a transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on one of a plurality of a virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of a plurality of virtual machines; and re-initiating the page walk.Type: GrantFiled: October 12, 2012Date of Patent: May 27, 2014Assignee: Intel CorporationInventors: Uday Savagaonkar, Madhavan Parthasarathy, Ravi Sahita, David Durham
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Patent number: 8725986Abstract: The present invention provides a system and method for virtual block numbers (VBNs) to disk block number (DBN) mapping that may be utilized for both single and/or multiple parity based redundancy systems. Following parity redistribution, new VBNs are assigned to disk blocks in the newly added disk and disk blocks previously occupied by parity may be moved to the new disk.Type: GrantFiled: April 18, 2008Date of Patent: May 13, 2014Assignee: NetApp, Inc.Inventor: Atul Goel
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Patent number: 8719533Abstract: Provided is a method of using a dynamic chunk allocation function to efficiently carry out data volume migration. A storage apparatus according to the present invention includes first and second storage units and divides a storage extent in the second storage unit into chunks to add the chunks to a chunk pool to dynamically allocate the chunks in the chunk pool to a newly created logical data volume (see FIG. 3).Type: GrantFiled: September 20, 2011Date of Patent: May 6, 2014Assignee: Hitachi, Ltd.Inventors: Atsumi Terayama, Akihisa Nagami, Toru Tanaka, Yasunori Kaneda
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Patent number: 8719543Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.Type: GrantFiled: December 29, 2009Date of Patent: May 6, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Patryk Kaminski, Thomas Woller, Keith Lowery, Erich Boleyn
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Patent number: 8694562Abstract: A generational garbage collector utilizes a pool-based heap to store objects dynamically generated at runtime. The pool-based heap is configured as a collection of pools where each pool stores objects associated with the same generation. Each pool contains a pool header that identifies the generation of all objects within the pool. The pools are aligned to a memory boundary that is a multiple of the pool size. Select bits of an object's memory address may be used to access the pool header so that an object's generation, which is needed in various phases of the garbage collection process, is readily determined.Type: GrantFiled: May 22, 2012Date of Patent: April 8, 2014Assignee: Microsoft CorporationInventors: Abhinaba Basu, Jaiprakash Sharma
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Patent number: 8694640Abstract: Communication protocols, systems, and methods that facilitate communication between disaggregated elements, and also to devices adapted to function as such disaggregated elements, particularly across peer-to-peer (masterless) and include one or more unique features such as packet atomicity, blind ACKs, NAT bridging, locking, multicast spanning and mirroring, and authentication.Type: GrantFiled: February 11, 2011Date of Patent: April 8, 2014Assignee: Rateze Remote Mgmt. L.L.C.Inventors: Charles Frank, Thomas Ludwig, Thomas Hanan, William Babbitt
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Patent number: 8688954Abstract: Inoperable bits are determined in a memory block. Rather than abandon the block as inoperable, a data structure is generated that includes at least one memory page pointer that identifies the location of the inoperable bits in the memory block. The data structure is stored in one of a group of memory blocks that are reserved for the data structures. A pointer to the data structure is stored in metadata associated with the memory block with the inoperable bits. When a later memory operation is received for the memory block, the pointer is retrieved from the metadata and the memory page pointers are used to avoid the inoperable bits.Type: GrantFiled: August 26, 2011Date of Patent: April 1, 2014Assignee: Microsoft CorporationInventor: John D. Davis
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Patent number: 8688636Abstract: A request is received to clone a source data object. A source block range of the source data object in a source logical storage unit is determined. An empty data object in the destination logical storage unit is created. A destination block range of the empty data object in the destination logical storage unit is determined. The source block range is mapped to the destination block range. The source data object is cloned based on the mapping.Type: GrantFiled: December 10, 2010Date of Patent: April 1, 2014Assignee: NetApp, Inc.Inventor: Anagha Barve
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Patent number: 8688952Abstract: An arithmetic processing apparatus includes: a plurality of TLBs holding as entries a portion of a conversion table for conversion of virtual addresses into physical addresses that has been placed in a main memory unit; an entry registration determining unit that, while registering an entry output from the main memory unit in any one of a plurality of TLBs, determines whether an entry has already been registered in an area of a TLB as registration destination; and a relocation control unit that, when the entry registration determining unit determines that an entry has already been registered in the area of the TLB as registration destination, evicts the entry that has already been registered and registers evicted entry in other TLB.Type: GrantFiled: December 16, 2009Date of Patent: April 1, 2014Assignee: Fujitsu LimitedInventor: Hiroaki Kimura
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Patent number: 8682872Abstract: A technique is disclosed that avoids index page splits when inserting large numbers of rows into a table of a relational database. Keys in index pages are moved to successive index pages to make room to insert keys on the original index page. Where no room is available on successive pages, a new index page is created to hold moved keys. The result is typically a smaller chain of index pages with better locality than using the conventional insertion technique of splitting index pages.Type: GrantFiled: December 17, 2009Date of Patent: March 25, 2014Assignee: BMC Software, Inc.Inventor: Randol K. Bright
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Patent number: 8667180Abstract: For facilitating data compression, a set of logical extents, each having compressed logical tracks of data, is mapped to a head physical extent and, if the head physical extent is determined to have been filled, to at least one overflow extent having spatial proximity to the head physical extent. Pursuant to at least one subsequent write operation and destage operation, the at least one subsequent write operation and destage operation determined to be associated with the head physical extent, the write operation is mapped to one of the head physical extent, the at least one overflow extent, and an additional extent having spatial proximity to the at least one overflow extent.Type: GrantFiled: June 25, 2012Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventors: Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Matthew J. Kalos, Gail A. Spear
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Patent number: 8667234Abstract: A method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory module. The method includes partitioning a physical page into storage segments and configuring a state mark for each storage segment, wherein the state marks indicate the validity of data stored in the storage segments. The method also includes writing the updated data into at least one of the storage segments and changing the state mark corresponding to the storage segment containing the updated data, wherein the state mark corresponding to the storage segment containing the updated data indicates a valid state, and the state marks corresponding to the other storage segments of the physical page not containing the updated data indicate an invalid state. Thereby, the time for writing data into a physical page is effectively shortened.Type: GrantFiled: October 6, 2011Date of Patent: March 4, 2014Assignee: Phison Electronics Corp.Inventor: Chih-Kang Yeh