Abstract: An address generating circuit of simple configuration for repeating a selected block of instructions is provided. An instruction address maintained by program counter 72 is compared to register 76 that holds the address of the end of the selected block of instructions. When the end address is detected, the program counter is loaded with a starting address of the block of instructions, which is stored in register 80. Block repeat count register 86 maintains a repeat count. Zero detection circuit 70 delays decrements of register 86 by a number of clock cycles that is equivalent to a pipeline depth for instruction prefetching of a processor connected to program counter 72. The zero detection circuit 70 outputs a loop-end control signal which controls a selector to selectively provide an incremented address or the start address to the program counter. By delaying decrements of register 86, the state of the repeat count is correctly maintained when the processor pipeline is flushed during an interrupt.

Abstract: A method of automatic address generation by units within clusters of a plurality of such units in which individual configurable elements of a unit can be addressed. It is thus possible to address the individual elements directly for reconfiguration. This is a prerequisite for being able to reconfigure parts of the unit by an external primary logic unit without having to change the entire configuration of the unit. In addition, the addresses for the individual elements of the units are automatically generated in the X and Y directions, so that the addressing scheme represents the actual arrangement of units and configurable elements. Furthermore, manual allocation of addresses is not necessary due to automatic address generation.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: Methods and systems for generating alternate and zigzag address scans in a reconfigured two-dimensional map under the MPEG-1 and MPEG-2 are provided. In one embodiment, a control signal generator determines the subsequent alternate address based on the present alternate address. In another embodiment, the control signal generator determines the subsequent zigzag address based on the present zigzag address. The subsequent address is generated by incrementing, decrementing, or resetting a pair of up/down counters that are coupled to the inputs of the control signal generator.

Abstract: The present disclosure concerns a method and apparatus for mapping each of a plurality of logical addresses to a physical address identifying a location in a memory device. The memory device has a plurality of columns and rows, wherein each row has a plurality of data paragraphs including data and at least one parity paragraph including parity data. Each paragraph is comprised of a plurality of contiguous columns. A physical address identifies a location of a paragraph in the memory device. To map the logical addresses to physical addresses, a determination must be made as to whether the row and column portions of each logical address identify a physical address location including parity data. If a logical address identifies a physical address location in the memory device including parity data, then the logical address is incremented until the row and column portions of the logical address identify a physical address location not including parity data.

Abstract: Each of a plurality of output circuits is coupled with one pair of a plurality of pairs of adjacent odd and even bits of a sequential group of address bits. The output circuits provide an address bus with the odd address bits during a first time period and with the even address bits during a second time period. The odd address bits are provided as a column address (or a row address) and the even address bits are provided as the row address (or column address).

Abstract: A method and apparatus for controlling transfer of data in which a plurality of burst transfer operations starting from an arbitrary byte as a start address are performed consecutively without a high-speed adder provided in the conventional data transfer apparatus performing burst transfer. Data is transferred between memories by a plurality of consecutive burst transfer operations performed on data stored in consecutive addresses. Each of the burst transfer operations is performed on the data stored in a respective one of memory cell areas each of which corresponds to a unit of burst transfer. A first address representing an address of one of the memory cell areas storing data to be transferred is calculated. The first address is a part of a start address of a second or later burst transfer operation. A second address representing an address of one of memory cells provided in the one of the memory cell areas is calculated separately. The data transfer operation is started from the one of the memory cells.

Abstract: A storage device has a relative address table. An address is sequentially generated by an address adder based on a start address and a plurality of relative addresses held in the relative address table. When a pattern of the address is unchanged, a succeeding access is processed without resetting the relative addresses in the relative address table.

Abstract: A method and apparatus for generating addresses. The present invention provides for fast generation of a series of addresses in an array where the series comprises a column or diagonal of the array, such as for layered ECC code words in CD-ROM. Whereas each address is computable individually using multipliers and modulo circuits, the present invention operates on the series of addresses as a whole, forming a dependence between successive addresses. The dependence is separated into multiple address indices that may be summed together for the desired address. The present invention is thus able to generate a series of addresses by accumulation processes requiring only selection of the appropriate increment value and addition to a previously stored address index value. Address generation throughput is increased with savings in layout area and power.

Abstract: A method of executing a program includes reading a next operation of an executing program and determining if a given pointer corresponding to the next operation is stored in a pointer table. If the given pointer is stored in the pointer table, an instruction identified by the given pointer is executed in a processor. However, if the given pointer is not stored in the pointer table, a replaceable pointer in the pointer table is identified and replaced by the given pointer. Instructions corresponding to the given pointer are also imported into a processor instruction unit from a supplemental storage area and subsequently executed by the processor. The instructions can comprise microcode or a portion of a programmable gate array. In the latter case, the supplemental storage area can store gate array programming instructions for use in reprogramming the instructions in the processor.

Abstract: A memory speed testing circuit including a memory addressing circuit (11, 13, 15) for sequentially providing to the address input of the memory device a binary address A and a binary address A which is a binary 1's complement of the binary address A, wherein the binary address A is provided within a selected time interval after the provision of the binary address A when the memory device is in a read mode; a data circuit (21, 23, 24) for generating a first binary test word and a second binary test word that is a 1's complement of the first binary test word; wherein the first binary test word is input to the data port of the memory device when the binary address A is provided the address input of the memory device when the memory device is in the write mode, and wherein the second binary test word is input to the data port of the memory device when the binary address A is provided to the address input of the memory device when the memory device is in the write mode; and a comparator (25) for comparing the firs

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM (SDRAM) is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a SDRAM during a test process in real time and generates column addresses for the SDRAM by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, a Z address signal, and an operation mode control signal, a conversion memory that outputs data based on a conversion table, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with a burst length control signal.

Abstract: A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride operand of the stride instruction and the address corresponding to another load memory operation immediately preceding the particular load memory operation in the series. A base address operand specifies the address of the first load memory operation in the series, and a repetition count operand specifies the number of load memory operations in the series. The cache lines corresponding to the series of load memory operations (i.e. the cache lines storing the bytes addressed by the load memory operations) are fetched into the data cache of the microprocessor in response to the series of load memory operations.

Abstract: A method and circuit are provided for generating a minimum-sized address filter to detect when the address space of an embedded memory having a smaller address space than another larger embedded memory is being exceeded. The method includes decomposing a maximum address into alternating sequences of consecutive binary ones (1's) and zeros (0's), discarding a final sequence if it contains binary 1's, and generating a filter circuit from a filter function formed from the alternating sequences of consecutive binary 1's and 0's. A built-in self test (BIST) circuit incorporating the address filter provides the ability to test a plurality of embedded memories at full speed in parallel. A computer system including a computer program for generating the filter circuit may also be provided.

Abstract: A bridge device (4) for connecting a plurality of communication networks (1-3) around which data is transmitted in frames which include control information defining at least the identity of a destination for data in the frame, each network having at least one end station (8-12). The bridge device comprises a corresponding plurality of data coupling units (13,14) for connection to respective ones of the networks (1-3), each data coupling unit including receive (13) and transmit (14) interfaces for respectively receiving data from and transmitting data onto the connected network. A common store (17) is connected to all the data coupling units for receiving data being transmitted from one network to another.

Abstract: An address generator has a designating value storing section for storing a designating value for designating each of register sections of an offset register into an address register. The address generator also has a designating value storing section for storing a designating value for designating each of register sections of a modulo register into the address register. Each of the register sections of the offset register and each of the register sections of the modulo register are automatically designated by designating the address generator. In this address generator, a degree of freedom of addressing can be increased while an increase in hardware scale is avoided as much as possible.

Abstract: A method and apparatus for generating a modulo address for accessing a circular buffer. The method and apparatus accept as inputs a length L of the circular buffer, a current address A of the circular buffer, and an offset M between the current address and the next address to be generated. The offset M may be positive or negative. During operation of the present invention, the current address A first is broken down into a base address B and an offset from the base address a. Then, in accordance with the length L and the offset M, the invention determines an absolute offset and a wrapped offset. One of these offsets is added to the base address B to generate a next address for the circular buffer. The determination of which offset to add to the base address B is made by performing one of two comparisons.

Abstract: The adaptive sequential pattern memory search technique only examines the contents of a subset of the total number of memory locations in each search for information representative of a character string. The subset includes a plurality of storage locations and each examination is performed in one concurrent read operation. If the character string is not matched, the memory must be updated to store information representative of the unmatched string. This updating process selects one location from the subset for storing this representative information. Advantageously, an indicator of when each stored representative information last matched a character string is maintained and utilized in the selection process. In addition, to avoid operational errors associated with outputting invalid information from the "child" of a previously discarded "parent", an indication of the time each stored entry is created is utilized to remove such invalid information as it is detected in the updating process.

Abstract: A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses corresponding to memory locations in the cache, and determines in which sub-arrays the memory locations reside. If the two memory locations reside in the same sub-array, the arbitration circuit sends the higher priority address to the sub-array. If a received address operand is the real address of a cache miss, the arbitration circuit sends the cache miss address to the sub-array before other pre-fetch memory access request.

Abstract: An efficient integer-division-by-an-constant method and apparatus. This integer-division-by-an-constant is useful in calculations which must be performed often and/or quickly, and where the denominator is fixed for the calculations, such as address calculations in massively parallel, distributed memory processor systems. Also described is a method and apparatus using the integer-division-by-an-constant method and apparatus, which facilitates removing power-of two restrictions on the reorganization and redistribution of data between remote and local memory blocks in a massively parallel, distributed-memory processing system. The flexible addressing scheme provided supports data organizations which vary widely depending on the processing task. In particular, a plurality of processing elements (PEs) operating in parallel within a subset of all the PEs in a massively parallel processor system, may simultaneously operate on an array data structure, the array data structure having an arbitrary size and shape.

Abstract: A device and method for comparing cancel tags, and for canceling data from a finite wrap-around data buffer. The data buffer stores tag values that are continuous, or sequential. A cancel tag is used to cancel all tags with a value "greater-than" the cancel tag. In comparing cancel tags of a wrap-around buffer, however, the comparator must take into account wrap-around conditions. When a wrap-around condition occurs, tags that have a lower value may be "greater-than" the cancel tag. The present invention advantageously adds an additional bit to the tags stored in the data buffer and the cancel tag. The additional bit is toggled whenever a wrap-around condition occurs. By comparing the additional bit of the tag to the additional bit of the cancel tag, a wrap-around condition can be detected without extensive additional circuitry. The comparison of the additional bit indicates whether the comparator should cancel tags that are greater-than or less-than the cancel tag.

Abstract: A method and device for generating address aliases corresponding to memory locations, for avoiding false load/store collisions during memory disambiguation. The alias generator takes advantage of the fact that the entire address range will most likely not be active in the registers at any one time. The subset of the address range that is active can be represented with a smaller number of bits and, hence, the computation of true dependencies is greatly reduced. The address alias generator includes an array for receiving the memory addresses, comparators having inputs connected to each array entry and having outputs connected to an alias encoder, and a control logic unit for writing the given memory address in one of the entries. The output of a given gate is turned on if a memory address is the same as the contents of one of the entry corresponding to that output, and the control means is activated if the output of all of the gates are turned off.

Abstract: A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to create burst cycles on a second bus that has protocols that allow burst cycles such as a Peripheral Component Interconnect (PCI) bus.

Abstract: A computer system having a bridge and I.sup.2 C EEPROMs is provided with a host I.sup.2 C controller implemented in the bridge for accelerating the reading of the I.sup.2 C EEPROMs. The host I.sup.2 C controller accelerates the reading of I.sup.2 C EEPROMs by executing current address reads of the I.sup.2 C EEPROM when a requested slave address matches a current slave address stored in a current slave address register, and the requested EEPROM address matches a current EEPROM address stored in a current EEPROM address counter. The host I.sup.2 C controller thus eliminates the use of software to track the read accesses of a plurality of masters to an I.sup.2 C EEPROM and also eliminates the use of bus command protocols to support both random reads and current address reads to an I.sup.2 C EEPROM.

Abstract: A data writing and reading method for a frame memory which provides a high speed data access by using a memory which is divided into a plurality of portions each of which has a plurality of banks. The frame memory stores sets of data corresponding to an image to be displayed on a screen of a display unit. A set of data is written in one of the banks of one of the frame memory portions in accordance with two-dimensional accessing. Then another set of data is written in another one of the banks of one of the frame memory portions when that one of the memory portions is next accessed. The sets of data written in the frame memory is read in accordance with one-dimensional accessing.

Abstract: A memory of a computer system is sized and configured after the memory has been loaded with data. The sizing and configuration of the memory causes the data to become scattered among memory chips on a single memory module or among two or more memory modules. To gather the data, gather code loads itself into the instruction cache of the computer system and while executing from the instruction cache configures the memory and gathers the data in the memory such that it is again located at the same address it held before the configuration occurred.

Abstract: A method of scheduling prefetch instructions in a compiler is described that improves performance by minimizing the performance degradation due to dirty cache misses. The method determines the length N of a loop (step 66). The number of prefetch instructions were M within that loop are then determined (step 68). A prefetch spacing P is then calculated according to the formula P=N/M, where the length of the loop is expressed in cycles (step 70). This prefetch spacing is then attached to each prefetch instruction and the instruction scheduler schedules the prefetch instructions so as to space the prefetch instructions apart by approximately the prefetch spacing P (step 72). After the scheduler arranged for P cycles, a prefetch instruction will be assigned a higher priority for scheduling in the next lot.

Abstract: A method and apparatus for causing a data line to be fetched in an order consistent with the data structure of a processor's modified little endian mode or big endian mode of operation is accomplished when the processor requests a particular word that is not currently stored in cache memory. The request includes an address of the particular word and an indication is provided as to whether the processor is operating in the modified little endian mode or the big endian mode. A memory manager, upon receiving the request, retrieves a line of data from memory (storage device) based on the address and the mode of operation. For example, when the big endian mode is used, the line of data is retrieved using a target word first ordering and when the modified little endian mode is used, the line of data is retrieved using a reverse target word first ordering.

Abstract: A multimedia data encoding and decoding system capable of handling various types of data arranged in variable-size blocks. Frames of image, graphics and text data are supplied to a frame buffer. In response to an encoding command from a CPU, an MPEG encoder compresses the data from the frame buffer in accordance with the MPEG compression algorithm, and outputs to a texture buffer a variable-size data block that corresponds to the frame portion to be displayed. The size of the data block is set by the CPU, and may vary from one macroblock to, e.g., 22.times.16 macroblocks (one frame for MPEG-1). An MPEG decoder reads the variable-size data block from the texture buffer, decompresses and supplies it to a graphics engine that manipulates various type of data to create a picture to be displayed at a video monitor.

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a semiconductor device under test during a test process in real time and generates column addresses for the device under test by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, Z address signal, and an operation mode control signal is arranged, a conversion memory that outputs certain conversion table contents is arranged, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with the burst length control signal.

Abstract: An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of processing elements (PE) constituting a parallel computer system. An adder provided within the global address generating unit sequentially adds an increment of an address, d.sub.-- Adr.sub.-- exl, and d.sub.-- Adr.sub.-- in to an address Adr.sub.-- exl and Adr.sub.-- in, respectively. A subtracter outputs a quotient obtained by dividing d.sub.-- Adr.sub.-- exl by band width bexl as a logical PE number. Additionally, a remainder obtained as an output from a subtracter is added to Adr.sub.-- in, thereby enabling a logical in-PE address to be obtained. The logical PE number and the logical in-PE address thus obtained are converted to a real PE number and a real in-PE address. Generating a global address by hardware reduces overhead incurred by parallel operation of array data.

Abstract: An improved method for performing memory writes from a processor in a personal computer system is provided whereby single writes are combined into burst writes based on detection of suitable write operations in instruction code. In a preferred embodiment, the improved method is implemented in microcode. The method includes detecting multiple suitable write operations prior to the execution, collecting the data elements in a storage unit, and writing the data elements as burst write operations. Write operations that meet specific conditions for quantity of data elements to be written and specific conditions for destination address are suitable for bursting. The improved method can be implemented in existing personal computers, thereby improving system performance without requiring new software applications or a new computer board design.

Abstract: Vector register circuitry is provided which includes a vector register file comprising at least one vector register having a plurality of elements, the vector register file further having at least one data port and at least one address port for accessing selected ones of the elements of the vector register. Address generation circuitry is provided coupled to the address port and includes an adder having an output coupled to the address port, a first element register having an output coupled to a first input of the adder and an element counter having an output coupled to a second input of the adder.

Abstract: An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor. The memory subsystem includes a cache memory. The address provided to the memory subsystem is divided into a cache index and a tag, and the cache index is hashed to provide a plurality of alternative addresses for accessing the cache. During a cache read, each of the alternative addresses are selected to search for the data responsive to an indicator of the validity of the data at the locations. The selection of the alternative address may be done through a mask having a number of bits corresponding to the number of alternative addresses. Each bit indicates whether the alternative address at that location should be used during the access of the cache in search of the data.

Abstract: There is provided by the present invention a mirror disk device, in which specific numbers identical to those written in disks and name of a drive used as for a master disk are recorded in a set-up memory incorporated therein, this data is compared to a specific number written in a disk to determine a master disk or to transfer data to a slave disk. In the mirror disk according to the present invention, ranges of specific numbers are discretely defined without any conflict according to switching positions of a rotary switch. A first specific number is decided within each of the ranges by a random function and then serial numbers subsequent to the first specific number are assigned as specific numbers. With this feature, it is possible to prevent effective data from being lost due to, for instance, instruction miss because of manual operation.

Abstract: In a method and system of performing a write cycle to a memory address in a multi-processor system, a first write cycle is initiated to the memory address, and a second write cycle is initiated to the memory address. Data from the first and second write cycles is merged, and the merged data is written to the memory address.

Abstract: A Method for increasing data-processing speed in computer systems containing at least one microprocessor (1), a memory device (3), and a cache (2,4) connected to the processor, in which the cache (2,4) is arranged to fetch data from the addresses in the memory device (3) requested by the processor (1) and then also fetches data from one or several addresses in the memory device (3) not requested by the processor (1). The computer system includes a circuit called the stream-detection circuit (5), connected to interact with a cache (2,4) such that the stream-detection circuit (5) detects the addresses which the processor (1) requests in the cache (2,4) and registers whether the addresses requested already existed in cache (2,4) . The stream-detection circuit (5) is arranged such that it is made to detect one or several sequential series of addresses requested by the processor (1) in the cache (2,4).

Abstract: A digital signal processor includes first and second counters which increment from each initial address value in first and second address areas synchronous with first and second sampling clock signals, an address generating circuit which generates a first address number in the above first address area according to a counter value in the above first counter and generates a second address number in the above second address area according to a counter value in the above second counter, a data memory which stores information signals supplied synchronous with the above first and second sampling clock signals in the first and second address numbers generated by the above address generating circuit readably and an arithmetic operating circuit which performs arithmetic operation of information signals stored in the above data memory.

Abstract: A method and apparatus for efficiently reading or writing a number of successive address locations within a memory. In an exemplary embodiment, a processor or the like may not be required to provide an address to a memory unit for each read and/or write operation when successive address locations are accessed. That is, for multiple memory accesses which access successive address locations, the processor or the like may provide an initial address but thereafter may not be required to provide subsequent addresses to the memory unit. The subsequent addresses may be automatically generated by an automatic-increment block.

Abstract: A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry.

Abstract: A memory linked address generator and method for a complex arithmetic processor executing an algorithm sequence includes memories, a clock for generating a clock cycle, and a decoder for determining position of the complex arithmetic processor within the algorithm sequence. The decoder is coupled to the clock and address pointer generators are coupled to the decoder and to the memories. The address pointer generators generate address pointers within the clock cycle for at least some of the memories in response to the position of the complex arithmetic processor within the algorithm sequence.

Abstract: A processing system and method is disclosed to access non-contiguous memory locations within a memory block. An address is generated that has a first group of bits and a second group of bits. The first group is decoded to select one of a number of memory blocks. The second group has n bits configured to select any one of (2.sup.n -(n+1)) unique combinations of the locations within the selected block. This second group provides a different pattern corresponding to each different combination of the locations within the selected block. An application of this addressing scheme for video graphics processing is also disclosed.

Abstract: Data storage apparatus comprises: a memory having a plurality of addressable memory locations for storage of data items and memory address input means for receiving addresses of locations to be accessed; main input means for receiving an input address corresponding to a memory location; a counter for changing a count in response to a clock signal; address adjustment means for combining the count with an input address to generate an adjusted address corresponding to a memory location and supplying the adjusted address to the memory address input means; and means for accessing the memory location at the address supplied to the memory address input means. Also provided is a data storage method, and data processing systems including the data storage systems.

Abstract: Method and apparatus for performing bus reflection operation using a data processor (10). The present invention allows a multiplexed peripheral bus master (16) to interface with non-multiplexed peripherals (12, 14) by using a data processor (10) to reflect an address value from the data bus (20) to the address bus (18), or alternately, from the address bus (18) to the data bus (20). In one embodiment, external bus master (16) provides the reflect request signal (30) to data processor (10), and in response, data processor (10) receives the address value provided by external bus master (16) on data bus (20) and drives this same address value on address bus (18) to memories (12, 14). In addition, the present invention allows an external bus master (16) to use the handshake circuitry (50) on data processor (10) to interface with peripheral devices (12,14).

Abstract: An address generating circuit of simple configuration for circular addressing. A bit isolating circuit 304 extracts an index from an input address. When a step value input to an adder 302 is positive, an index generating circuit subtracts the sum of the index and step value from a block size of a memory region. Depending on the subtraction result, an output which is either the sum of the index and step value or the subtraction result is provided as a new index. When the step value is negative, the index and step value are added. Depending on the addition result, an output which is either the sum of the index, step value, and capacity of the memory region or the addition result is provided as a new index. A bit multiplexer 314 generates the next address from the new index and an address.

Abstract: A structure and method for determining whether a first in, first out (FIFO) memory is empty or full when the read address of the memory equals the write address of the memory. The read and write addresses are individually incremented, each in a predetermined circular sequence. The circular sequence is divided at least three segments. Portions of the read and write addresses are encoded to indicate the segments in which the read and write addresses are located. These encoded address portions are decoded to determine the relative segment positions of the read and write addresses. If the read address is in the segment prior to the write address, a DIRECTION signal is set to a first state. If the write address is in the segment prior to the read address, the DIRECTION signal is set to a second state. When the read address equals the write address, the state of the DIRECTION signal is used to determine whether the memory is empty or full. If the DIRECTION signal is in the first state, the memory is empty.

Abstract: A first and a second input ports, the sum of whose inputs is greater than an integer n, receive pairs of first words of k bits and of second words of n-k bits, each set of n bits representing an address item (ADI) for a point (PO) of a two-dimensional space of points (IM) associated with data coded on 2.sup.d bits, the respective bits of the first and second words representing two coordinates (X, Y) of the point in the said space. A configuration input receives a value of k (k1, k2, k3), chosen to be positive or zero and less than or equal to n, and representative of a geometrical configuration chosen for the two-dimensional?s!?pace! space (IM).