Abstract: An address sequencer circuit for generating addresses for accessing a memory device. The address sequencer includes a plurality of address stages that are coupled together, and also includes a first clock generation circuit that receives an input clock and generates a first clock signal that is coupled to a first portion of the address stages. A second clock generation circuit is provided that receives the input clock and a toggle signal and generates a second clock signal that is coupled to a second portion of the address stages, thereby allowing the first and second portions of address stages to be clocked at different rates.

Abstract: Methods of maintaining a record of a samples of a time-dependent variable in a computer memory whereby any period of time extending backward from the present, having a duration between a pre-determined minimum and a pre-determined maximum, is represented by samples whose spacing is short in relation to the duration of the time period represented.

Abstract: An approach for providing intelligent caching is disclosed. A communications system includes a first caching logic that is configured to analyze a traffic stream for content and to output a first profile of the content. The system also includes a second caching logic that is configured to generate a second profile based upon the first profile, wherein the second profile is used to retrieve content. The content associated with the second profile may be pre-loaded into remote cache using multicasting over a wide area network (WAN), such as, a satellite network.

Abstract: A computer system with a multi-master system bus includes a memory controller that changes the burst mode of the including memory system automatically as a function of the selected master. The controller includes a programmable look-up table into which is stored a value B corresponding to a fixed memory burst mode; for each master, a multiplier is stored indicating the multiple of the burst mode that would be optimal for that master. The grant signal used to select the current master is also used to select the multiplier M associated with that master. In response to a read request by the current master, a requested address is forwarded to the memory. Then the controller generates and transmits M−1 addresses spaced B addresses apart every Bth bus cycle. This implements a memory system burst of M*B addresses with no latencies between successive B-address memory bursts. The memory system burst can be aborted if an address in the burst is not confirmed by a subsequent address request by the master.

Abstract: In a method of reducing direct memory access in a machine employing a data segmenting scheme, transfer of a repetitive block of data is detected. The repetitive block of data repeats a data word of a predetermined value. A first invalid address is assigned to a current address pointer. The first invalid address indicates that the repetitive block of data is to be generated. A second invalid address is assigned to an end segment pointer. The second invalid address corresponds to the first invalid address plus a value indicating a number of repetitive data words that is included in the block of repetitive data. While the current address pointer has a value assigned thereto that is not equal to the second invalid address, a data word of the predetermined value is generated and the value assigned to the current address pointer is stepped.

Abstract: A memory access device is presented that synchronously transfers data between contiguous memory locations and a set of potentially non-contiguous registers, via a single load, or move, command. An address generator generates a series of contiguous memory addresses and a corresponding set of potentially non-contiguous register addresses in dependence upon the contents of a variable format command. In this manner, the data transfer efficiencies achievable by a block transfer of contiguous data elements can be achieved while simultaneously transferring the data to and from non-contiguous register locations. The memory access device may also include a data converter which optionally converts the data elements contained in memory to and from another form, such as from integer to floating point, during the data transfer process.

Abstract: A method and apparatus for accommodating irregular memory write word widths allow for writing to multiple rows in a memory so as to reduce or eliminate holes in the address read space. First and second memory blocks are provided that include a first bitcell selectable by a first write bitline and a second bitcell selectable by a second write bitline. Where a write word width is not equal to a read word width and is not some factor of a power of two times the read word width, the column decode to read out the entire word is not a power of two, and holes in the read address space will exist. When the write address is even, a first range of bits is written to the first block on a first write bitline, a second range of bits is written to the second block on the first write bitline, and a third range of bits is written to the first block on a second write bitline.

Abstract: The 2 lower bits of a medium sector address that the memory device receives from the host system are used as the data corresponding to a column address in a sector in the flash memory. For instance, with the flash memory having the sector capacity of 2048 bytes and the memory device having the sector capacity of 512 bytes, data transfer control portion when the respective 2 lower bits, 00, 01, 10, and 11 are input, starts the data transfer to the flash memory from the buffer memory at a timing corresponding to column addresses 0h, 200h, 400h, and 600h, respectively.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad.

Abstract: A system and method of compressing memory for efficiently searching the memory. Values are assigned to initial memory locations and these values are logically combined to form a first group of values. This first group of values are then entered into memory locations and logically combined to form a second group of values. The second group of values are then entered into their own memory locations. By searching the second group of values, it can be determined which of the first group of values includes an initial memory location having a desired logic value.

Abstract: There is provided an address counter and address counting method capable of enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external address or a previous internal address is inputted and further generating both of a path for the case a parity signal having a high state is inputted and that for the case the parity signal having a low state is provided. At the same time of producing the paths, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Moreover, an operation of latching the next address is terminated as soon as the parity signal is generated.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock since the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: An external address is input to an address register AR, and an internal address {circle over (1)} as an output from this address register AR is supplied to a burst length determination circuit BLD. The burst length is determined based on the level of this external address at a timing specified by a burst length setting signal /BL. A binary counter/logic BCL1 outputs burst internal addresses {circle over (2)} Ax″ to A0″ and internal addresses {circle over (1)} A16″ to A(x+1)′ to a memory cell array MCA. This allows data having a desired burst length to be input or output.

Abstract: The 2 lower bits of a medium sector address that the memory device receives from the host system are used as the data corresponding to a column address in a sector in the flash memory. For instance, with the flash memory having the sector capacity of 2048 bytes and the memory device having the sector capacity of 512 bytes, data transfer control portion when the respective 2 lower bits, 00, 01, 10, and 11 are input, starts the data transfer to the flash memory from the buffer memory at a timing corresponding to column addresses 0h, 200h, 400h, and 600h, respectively.

Abstract: A hashing method and apparatus uses a hash function that can be modified in real time by a hash control code. The hash function involves the combining together of multiple bit-shifted versions of a multi-bit input to produce a transformed value from which the hash output is formed. The hash control code is used to set the number of input versions used to produce the transformed value and their respective degrees of bit-shifting. The hashing method and apparatus may be used in executing processor branch instructions where the identity of an item to be accessed occupies a search space that varies in size and degree of population between different branch instructions.

Abstract: A system and method for providing a burst sequence of data in a desired data ordering in response to a request packet. The burst sequence of data includes a plurality of data blocks and the request packet includes one or more data ordering bits which define a data ordering. The system includes one or more random access memory modules. Each random access memory module includes a memory array having a plurality of memory cells organized in an array of rows and columns, a row address decoder connected to the memory array for generating a row address which addresses one of the rows of the memory array, and a column address decoder connected to the memory array for generating a column address which addresses one of the columns of the memory array.

Abstract: A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory and transmitted in a weakly ordered fashion over a bus to a graphics device. The graphics device reorders the incoming data into the same order as which the data was written into the contiguous region of system memory, thereby allowing the use of order dependent encoded commands with the weakly ordered bus interface.

Abstract: A method is disclosed for making a selection on a pattern sequence depending on whether or not the sequence belongs to a routing set, the routing set having at least two keys. The selection is made in a single step by analyzing a selection word (CASE SELECT) identifying the routing set.

Abstract: This invention describes an apparatus and method for the fast and efficient generation of addresses for a circular buffer involving only addition. The invention uses as input the present address, the base address, the length of the circular buffer and the address offset to the next address. The address offset can be either a positive or negative value, and the polarity of the offset is used to control different operations within the apparatus. The apparatus is constructed of two adders, a comparator and a multiplexer, and the next address is selected from the output of either of the two adders based on the output of the comparator.

Abstract: A data processing apparatus improves speed and efficiency of transfer of bit data, especially, multivalue data bit plane. For this purpose, a memory 50 holds four 8-bit multivalue data per 1 word, and bit plane coding processing is made by 4×4 (=16) multivalue data (processing block). In a memory area 51, the most significant bit (bit 7) of respective multivalue data (data 0 to 15 in FIG. 5) is collected in the order of multivalue data, and stored in one position (hatched portions in FIG. 5). Similarly, bit 6 is collected from the respective multivalue data and stored in one position.

Abstract: A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators has logic operative to derive an internal address from the packet address. The internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.

Abstract: A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions.

Abstract: A memory device includes a data array, a tag array, and control logic. The data array is adapted to store a plurality of data array entries. The tag array is adapted to store a plurality of data array entries corresponding to the data array entries. The control logic adapted to access a subset of the data array entries in the data array using a burst access and to access the tag array during the burst access. A method for accessing a memory device is provided. The memory device includes a data array and a tag array. The method includes receiving a data array burst access command. The data array is accessed in response to the data array burst access command. A tag array access is received. The tag array is accessed in response to the tag array access command while the data array is being accessed.

Abstract: A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent ban conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translation or remapping unit that remaps sequences of logical addresses into sequences of slightly aperiodic physical addresses such that the physical addresses do not form a repetitive pattern of period less than N+1, where N is the number of memory banks, and do not on average repeat a physical bank number within approximately N physical addresses. In large memory modules and embedded logic devices wherein multiple memory units communicate with multiple microprocessors in a single chip, the disclosed remapping combined with disclosed scrambling methods also achieves high tolerance of chip defects which would otherwise render chips unusable, thereby yielding manufacturing economies.

Abstract: Data transfers involving accesses of multiple banks of a DRAM having a shared sense amplifier architecture can be performed while also avoiding bank conflicts and associated data bus latency. Groups of DRAM banks which can be sequentially accessed during a given data transfer without conflicting with one another are identified and utilized for data transfers. Each data transfer sequentially accesses the banks of one of the groups. The sequence in which the banks of a given group will be accessed during a data transfer can advantageously be reordered in order to prevent conflicts with banks that have been or will be accessed during prior or subsequent data transfers. In this manner, consecutive data transfers, each involving accesses to multiple banks of a DRAM having a shared sense amplifier architecture, can be performed without any data bus latency between or within the transfers.

Abstract: An improved method and computer to parse a data stream comprising a series of command strings is disclosed. The method provides superior performance in terms of balance between processor cycle usage, memory usage and portability across platforms.

Abstract: A method and apparatus for sequentially generating a set of addresses, defined over a plurality of indices, for a multi-dimensional array stored in a memory for the condition where at least one of the address indices is fixed, is performed by simple addition, OR-ing and AND-ing. An accumulator or counter initially holds an arbitrary binary value composed of a set of binary indices corresponding to the address indices. This binary value is logically OR-ed with a first mask value having binary indices selected in value in relation to the fixed address indices. The resultant is logically AND-ed with a second mask value having binary indices selected in value in relation to the fixed address indices, and this operation produces a first address of the set. The same resultant is incremented and the incremented value is delivered to the accumulator for the cycle to be repeated.

Abstract: A reconfigurable logic system using reconfigurable functional units of the type having arithmetic logic units are associated with address generating memory units. The address generating memory units having address generators that can construct addresses for memory in the address generator memory units. This frees the reconfigurable functional unit from the need to construct a sequence of addresses for the memory unit.

Abstract: ? A method and apparatus for sequentially generating a set of addresses, defined over a plurality of indices, for a multi-dimensional array stored in a memory for the condition where at least one of the address indices is fixed, is performed by simple addition, OR-ing and AND-ing. An accumulator or counter initially holds an arbitrary binary value composed of a set of binary indices corresponding to the address indices. This binary value is logically OR-ed with a first mask value having binary indices selected in value in relation to the fixed address indices. The resultant is logically AND-ed with a second mask value having binary indices selected in value in relation to the fixed address indices, and this operation produces a first address of the set. The same resultant is incremented and the incremented value is delivered to the accumulator for the cycle to be repeated.

Abstract: A linked list memory (8) having an address generator (19) used during initial processing and a method for assigning addresses to lists corresponding to devices using a common memory (10). When the address generator (19) has assigned each address location once, a free list is used to track available addresses. The free list is not used until all addresses have been assigned once. In one embodiment, a counter (22) is incremented each time an address is assigned, where the value of counter (22) provides the address for a write operation. The counter (22) is not effected by requests to read from memory. The free list is not used until the counter (22) has been used to assign all addresses in the memory (10).

Abstract: A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.

Abstract: A magnetic disc control apparatus detects a near sequential I/O and pre-reads data from a magnetic disc drive into a cache memory. The control apparatus includes a near sequential I/O processor, which has an I/O history storage table for storing a transfer end address of I/O requested by a host computer, a near sequential I/O identifier for calculating an address difference between the transfer end address read out from this I/O history storage table and the current I/O transfer start address and identifying the I/O as a near sequential I/O if the address difference is within a predetermined value, and a pre-read executor for pre-reading data from the magnetic disc drive to the cache memory when a near sequential I/O is detected.

Abstract: A memory channel means transferring data streams between different blocks and an internal memory means on a data chip, wherein said memory channel means comprises several memory channels. Each channel has source and destination data stream interfaces, wherein each interface is connectable to different blocks, and a flexible address generator generating source and destination addresses for the internal memory means, wherein the order of the data being transferred is changed.

Abstract: The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect lines in an optimized fashion. In one embodiment, the present invention combines different control information, such as row address and bank address information into a unified address field wherein one or more bits can be shared. By sharing bits across various address fields, the present invention conserves bandwidth that is required by the control signals. In another embodiment, the present invention provides various schemes for defining and constructing packets of information that maximize the amount of information carried by a given packet across a limited number of interconnect lines.

Abstract: A computer server system comprising a plurality of storage units which are arranged to be accessed for data retrieval purposes by a plurality of users, wherein user data is scattered in blocks distributed randomly and repeatably across available storage.

Abstract: A data transfer circuit or a recording apparatus includes an address setting unit for setting a start address for a buffer memory, an offset setting unit for setting an offset for the buffer memory, and an address creating unit for creating a predetermined number of consecutive transfer addresses to be supplied for the buffer memory using a reference address. The circuit also includes an arithmetic logic unit that, after the address creating unit has created transfer addresses using the start address as a reference address, calculates a new reference address in accordance with the offset relative to the start address so as to provide the new reference address to the address creating unit.

Abstract: A sequence controller includes a sequencer to which a basic clock is applied. The sequencer sequentially generates at a period of 125 &mgr;sec address signals for reading statements to be executed at a period of 125 &mgr;sec and one block of statements to be executed at a period of 10 msec or one block of statements to be executed at a period of 100 msec. A memory stores the above statements beforehand. The statements are selectively read out of the memory in accordance with the address signals and fed to a decoder. The decoder decodes the statements and generates control signals respectively corresponding to the statements and feeds the control signals to a switch. The switch controls each of a plurality of function registers on the basis of the respective control signal.

Abstract: A method and apparatus for manipulating data from a processor on a stack memory is disclosed. The method and apparatus comprises aligning a stack pointer (104) in the stack memory (110) to a first memory address (126). The method further comprises incrementing the stack pointer (104) to a second memory address (128). The method further comprises saving data from a register (102) into the stack memory (110) at the second memory address (128). The method further comprises aligning the stack pointer (104) to a next even address if at an odd address when the saving step is complete. The method further comprises performing processor operations. The method further comprises unaligning the stack pointer (104) from the even address back to the odd address. The method further comprises restoring data from the stack memory (110) into the register (102). The method further comprises decrementing the stack pointer (104) from the second memory address (128) to the first memory address (126).

Abstract: In a data storage subsystem providing data storage to host processors, a process of configuration defines a subset of the data storage that each host may access. A vector specification is a convenient mechanism for specifying a set of storage volumes that a host may access. For example, for each host processor, there is stored in memory of the data storage subsystem a list of contiguous ranges or vectors of the storage volumes that the host may access. To determine whether or not a specified logical volume number is included in the vector, a mudulus of the stride of the vector is computed from the difference between the address of the specified logical volume and the beginning address of the vector, and the modulus is compared to zero. To provide a mapping between logical unit numbers specified by the host and the logical volumes, a contiguous range of logical unit numbers may also be specified for each contiguous range or vector of storage volumes.

Abstract: An integrated circuit, including but not limited to a memory device, receives an externally provided voltage signal and selectively adjusts the timing of internal control signals. An external signal selects between two possible pre-determined delay paths. The delay paths are adjusted using fuse circuitry which can be programmed by the manufacturer prior to implementation by a user. The delay path adjustment feature is particularly applicable to adjusting output signal timing to allow the integrated circuit to be operated in an environment which requires slower communications speeds. The same integrated circuit, therefore, can also be implemented in an environment which allows for faster communications speeds.

Abstract: Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

Abstract: A digital data processing apparatus has a primary data storage element that stores data for access by one or more processes, as well as a secondary data storage element, e.g., a disk drive, for non-volatile data storage. A paging mechanism selectively transfers sets of data between the primary data storage element and an associated data file on the secondary data storage element. A directory stores “atomic” signals, or bits, each reflecting a state of one or more subsets of data in respective sets. The paging mechanism includes a page-out element that stores data from a subset of a set to the associated data file. During paging, the page-out element responds to data in the subset which are associated with the atomic state (as indicated by the atomic bit) for storing to an associated status file on the secondary data storage element attributes of the paged data. Those signals can be, for example, the atomic bits themselves.

Abstract: A floating point unit 26 is provided with a register bank 38 comprising 32 registers that may be used as either vector registers V or scalar registers S. Data values are transferred between memory 30 and the registers within the register bank 38 using contiguous block memory access instructions. Vector processing instructions specify a sequence of processing operations to be performed upon data values within a sequence of registers. The register address is incremented between each operation by an amount controlled by a stride value. Accordingly, the register address can be incremented by values such as 0, 1, 2 or 4 between each iteration. This provides a mechanism for retaining block memory access instructions to contiguous memory addresses whilst supporting vector matrix and/or complex operations in which the data values needed for each iteration are not adjacent to one another in the memory 30.

Abstract: A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.

Abstract: An interleave read address generator of an interleaver for use in a CDMA mobile communication terminal. The interleave read address generator includes a base-18 counter for counting a clock input on a base 18, to generate column address bits, a base-32 counter being enabled in response to a carry output from base-18 counter, for counting the clock input on a base 32 to generate row address bits, and a multiplexer for changing a position of output bits of base-32 counter according to data rate selection signals, to variably generate the row address bits.

Abstract: Without making the address control more complex than necessary, a memory can be effectively utilized by accessing a square memory area. According to a processor of the present invention connected to memory apparatus having a two-dimensional memory area comprised of rows and columns, the processor comprises registers for storing a start address, an end address, and a number of columns per row of a square area on the memory. The registers are used to generate access addresses for accessing the square area. The processor is provided with the address generation and control unit for outputting the generated access addresses. The address generation and control unit includes a modulo addressing control unit for generating the access addresses for cyclically accessing the square area. A square circulation mode information decides whether or not to access cyclically the square area. Based on a value of the square circulation mode information, whether or not to cyclically access the square area is decided.

Abstract: A method and apparatus are presented for implementing the next-address determination within a binary search algorithm. A binary search algorithm searches for a compared within a one dimensional sorted array of elements. Typically, a binary search algorithm comprises a comparator and a next address generator. The next address generator determines the address of the next array element (the “next address”) a comparator will search using both a “compared is greater” signal from the comparator and a signal which indicates the address of the last array the comparator searched (the “previous address”). The time needed to search an array for a compared inserts a delay in applications where a binary search algorithm is employed. One method of expediting the searching process is to minimize the number of gates between the input and output of the next address generator (the “critical path”).

Abstract: To provide an improved memory in which code or data can be read out in the original order even when it is successively accessed by a processor of a successive type according to addressing in a grey code system and a method of storing code/data in such memory. Code/data addressed in the original binary code system are stored in a memory in the form in which the original order and continuity are not lost even after the addresses are converted to a grey code system. Accordingly, a processor of successive type can read out code or data in the original order by consecutively outputting addresses according to a grey code address system. The power consumption of the address generator can be reduced in accessing to consecutive addresses by having addresses of the memory space expressed in a grey code.