Generating A Particular Pattern/sequence Of Addresses Patents (Class 711/217)
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Publication number: 20030204673Abstract: A data processing system (20) is able to perform parameter-selectable prefetch instructions to prefetch data for a cache (38). When attempting to be backward compatible with previously written code, sometimes performing this instruction can result in attempting to prefetch redundant data by prefetching the same data twice. In order to prevent this, the parameters of the instruction are analyzed to determine if such redundant data will be prefetched. If so, then the parameters are altered to avoid prefetching redundant data. In some of the possibilities for the parameters of the instruction, the altering of the parameters requires significant circuitry so that an alternative approach is used. This alternative but slower approach, which can be used in the same system with the first approach, detects if the line of the cache that is currently being requested is the same as the previous request. If so, the current request is not executed.Type: ApplicationFiled: April 26, 2002Publication date: October 30, 2003Inventors: Suresh Venkumahanti, Michael Dean Snyder
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Publication number: 20030204703Abstract: A hash table randomly populated with byte patterns is used in finding the byte patterns in a sequence of bytes. A hash function is applied to information associated with a substring of the sequence of bytes to generate a key value. The key value is compared to the keys of the hash table, and if a match is found, the information associated with the substring is compared to corresponding information associated with a substring of a byte pattern stored in the hash table. If a match is found, the substring of the sequence of bytes is compared to the substring of the byte pattern. If a match is found, the substring is compared to the byte pattern.Type: ApplicationFiled: April 25, 2002Publication date: October 30, 2003Inventors: Priya Rajagopal, David M. Durham
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Patent number: 6640266Abstract: A device generally comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25 microamps.Type: GrantFiled: March 23, 2001Date of Patent: October 28, 2003Assignee: Cypress Semiconductor Corp.Inventors: Mathew R. Arcoleo, Rajesh Manapat, Scott Harmel
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Patent number: 6640295Abstract: In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on a memory having memory banks operable independent from one another. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth (where k=0, 1, 2 . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.Type: GrantFiled: August 22, 2001Date of Patent: October 28, 2003Assignee: Oki Electric Industry Co., Ltd.Inventor: Atsushi Takasugi
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Publication number: 20030200416Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: May 30, 2003Publication date: October 23, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030200415Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: May 23, 2003Publication date: October 23, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030200414Abstract: A method and apparatus to reduce the amount of required memory and instruction cycles when implementing Fast Fourier Transformers (FFTs) on a computer system is described. The invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a processor capable of bit reversed incrementation. Alternative embodiments implement the invention for out of place bit reversal (OOPBR) and on processors that do not support special instructions for bit reversed incrementation. The invention only generates unique bit-reversed address pairs and avoids generation of self-reversed addresses. To optimize the invention for in place bit reversal, every non-self bit reversed address in the input array is generated only once, while making simple, computationally efficient increments away from the previous pair of bit reversed addresses. The address pair generator can independently advance only one address in each address pair, and bit reversal of one address uniquely defines the other address.Type: ApplicationFiled: March 15, 2002Publication date: October 23, 2003Inventors: Thomas Harley, Maheshwaramurthy G. Panchaksharaiah
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Publication number: 20030200417Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 23, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196067Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196069Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196070Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196068Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6633966Abstract: FIFO type memory is provided on a small circuit scale. Reading of data Dout<3:0> from a two-port type RAM (101) is executed with respect to the address specified by a read address (21) in synchronization with the fall of a clock (CLK) provided to a clock end (CLR). Writing of data Din<3:0> on the RAM (101) is executed with respect to the address specified by a write address (22) in synchronization with the rise of a clock (CLK) provided to a clock end (CLW). In an address delayer (103) after a read address (21) taking an address value is outputted, a write address (22) taking the same address value is always outputted with a fixed delay, so that a memory (100) performs the FIFO type data input/output as a whole.Type: GrantFiled: October 22, 1998Date of Patent: October 14, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masayuki Koyama
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Patent number: 6625763Abstract: A block interleaver is provided using a relatively small register file and a larger random access memory (RAM). In one embodiment, the size of the RAM is larger than the size of the register file by at least one order of magnitude. As a result, the register file consumes significantly less power than the RAM for similar operations. The register file receives a stream of sequential data values and stores the data values in a column order. The data values are then read from the register file in a row order. The data values read from the register file in a row order are then written to the RAM in a row order. The data values are then read from the RAM in a row order, thereby creating an interleaved data stream. In a particular embodiment, the data values are written to the RAM in a staggered row order and read from the RAM in a sequential row order. All accesses to the RAM are performed using the full width of the RAM, such that no unnecessary power is used to access the RAM.Type: GrantFiled: July 5, 2000Date of Patent: September 23, 2003Assignee: 3G.com, Inc.Inventor: Alon Boner
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Patent number: 6615311Abstract: Updating a content addressable memory (CAM) involves identifying a new entry that is to be added to the CAM, identifying a free location in the CAM that is the fewest number of prefix levels away from the prefix level of the new entry, moving an existing CAM entry into the free location to create a newly freed location that is a fewer number of prefix levels away from the prefix level of the new entry, repeating the move process until a free location is created at the desired prefix level of the new entry, and then adding the new entry into the newly freed location. The specific algorithm for moving entries to free a location in the desired prefix level is a function of whether the prefix level of the first free location is above or below the prefix level of the new entry.Type: GrantFiled: June 7, 2001Date of Patent: September 2, 2003Assignee: Riverstone Networks, Inc.Inventor: Balakrishnan Ramakrishnan
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Patent number: 6611894Abstract: The present invention relates to a data retrieval apparatus for retrieving the data from a number of places of data stored in memories which adopts binary search method and enables high-speed retrieval operation. The apparatus includes three memories and address converting circuits. A logical address space is divided into 2 banks of a bank constituting a set of even number addresses and a bank constituting a set of odd number addresses. Further, in the case where in respect of one bank of the 2 banks and addresses are expressed by binary numbers, the one bank is divided into a bank constituting a set of addresses where an even number of bits of “1” are present and a bank constituting a set of addresses where an odd number of bits of “1” are present. A total of the 3 banks of the logical address space are mapped in a physical address space of 3 memories. A control device carries out retrieval of data stored in the memories by binary search method by using given key data.Type: GrantFiled: March 25, 1999Date of Patent: August 26, 2003Assignee: Kawasaki Microelectronics, Inc.Inventor: Ryuichi Onoo
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Publication number: 20030154351Abstract: A coherence prediction mechanism includes a history cache for storing a plurality of cache entries each storing coherence history information for a corresponding block of data. Entries in the history cache are used to index into a pattern memory containing coherence predictions.Type: ApplicationFiled: November 15, 2002Publication date: August 14, 2003Inventors: Jim Nilsson, Anders Landin, Per O. Stenstrom
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Patent number: 6604178Abstract: A method and apparatus for calculating an expected access time associated with one of a plurality of disk drive commands employs one or more neural networks. A plurality of disk drive commands received from an external source are stored in a memory, typically in a queue. Using a neural network, an expected access time associated with each of the queued commands is determined. Determining the expected access time associated with each of the queued commands involves determining a time for performing a seek and settle operation for each of the queued commands and a latency time associated with each of the queued commands. The command indicated by the neural network as having a minimum expected access time relative to access times associated with other ones of the queued commands is identified for execution.Type: GrantFiled: November 30, 1999Date of Patent: August 5, 2003Assignee: International Business Machines CorporationInventor: David Robison Hall
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Patent number: 6604166Abstract: A memory architecture is provided to enable parallel access along any dimension of an n-dimensional data array. To enable parallel access of s data elements along any dimension, the data elements of n-dimensional data array are mapped to s parallel memory banks in such a way that consecutive s data elements along any dimension are mapped to different memory banks. This mapping is defined by two functions, which define the memory bank number and location within a memory bank for each data element in n-dimensional data array. The necessary and sufficient conditions, which the mapping functions should satisfy in order to enable parallel data access, are described. These generic function pairs are described for all combinations of (n, s). Two particular instances of the mapping, namely circular permutation (rotation) along 0th dimension and dyadic permutation along 0th dimension have been discussed in detail.Type: GrantFiled: December 20, 1999Date of Patent: August 5, 2003Assignee: Silicon Automation Systems LimitedInventors: Soumya Jana, Pankaj Bansal, Balvinder Singh
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Patent number: 6604169Abstract: A hardware based modulo addressing scheme is described that is fast and makes efficient use of logic. The scheme uses a subtractor, multiplexers and AND/OR logic to produce modulo addresses to address, for example, a circular buffer in a memory. The buffer is defined by the user based on start and end addresses and an offset value. The offset may be positive or negative and may be greater than one.Type: GrantFiled: June 1, 2001Date of Patent: August 5, 2003Assignee: Microchip Technology IncorporatedInventor: Michael I. Catherwood
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Patent number: 6601160Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.Type: GrantFiled: June 1, 2001Date of Patent: July 29, 2003Assignee: Microchip Technology IncorporatedInventors: Michael Catherwood, Joseph W. Triece, Michael Pyska, Joshua M. Conner
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Patent number: 6601157Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.Type: GrantFiled: November 1, 2000Date of Patent: July 29, 2003Assignee: Broadcom CorporationInventors: Mark Taunton, Sophie Wilson, Timothy Martin Dobson
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Patent number: 6594738Abstract: A semiconductor device includes an MPU (Micro Processing Unit) section, a DRAM (Dynamic Random Access Memory) section, a plurality of address registers, and a plurality of address delay compensating units. The MPU section is provided on a chip to output a clock signal and an address signal. The DRAM section is provided on the chip to input the clock signal and the address signal. Each of the plurality of address registers latches the address signal in response to the clock signal. Each of the plurality of address delay compensating units is provided in a previous stage to the plurality of address registers and compensates for an address signal transmission delay time such that the address signal transmission delay time falls within a predetermined range. The address signal transmission delay time indicates a time elapsed before the each address register inputs the address signal after the MPU section outputs the address signal.Type: GrantFiled: December 7, 1999Date of Patent: July 15, 2003Assignee: NEC Electronics CorporationInventor: Tadahiko Sugibayashi
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Publication number: 20030126351Abstract: The present invention relates to a memory system, or more particularly to a conflict-free memory system, which can reduce access time to the memory system by supporting simultaneous access to pq units of various data elements of types of 4 directional blocks (pq) and eight directional lines of a constant interval at a location of data within M×N array in a SIMD processor having pq units of PE's (Processing Elements). Accordingly, the present invention is an improvement over the previous memory systems, from the perspective of restriction of subarrary types, constant intervals, and the size of a data array, hardware cost, speed and complexity. Further, it provides a method of address calculation and data routing using said improved conflict-free memory system.Type: ApplicationFiled: March 26, 2002Publication date: July 3, 2003Inventor: Jong-Won Park
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Publication number: 20030120879Abstract: A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory). The queue structure is partitioned into two or more blocks (e.g., chunks) wherein at least some of the blocks of the queue structure include two or more data units. Further, at least some of the blocks of the queue structure may include a pointer to a next block of the queue structure (e.g., a next chunk pointer). Given such a queue structure, the processing circuitry is configurable to address a first block of the queue structure, and then address a next block of the queue structure by setting the next block pointer of the first block to point to the next block.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Inventors: Jian-Guo Chen, David E. Clune, Hanan Z. Moller, David P. Sonnier
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Patent number: 6584556Abstract: A two-stage, pipelined modulo address generator (MAG) (30′) for generating from a current pointer into a circular buffer of size L, a next pointer into the buffer, is comprised of a pointer generation stage (32′) and a modulo correction and pointer selection stage (34′), each adapted to operate in a selected one of two modes. In the first operating mode: the pointer generation stage (32′) generates a sequential pointer which is a selected offset from the current pointer; and the modulo correction and pointer selection stage (34′) generates, modulo L, a modulo corrected sequential pointer, and provides as the next pointer the sequential pointer, if it is in the buffer, and the modulo corrected sequential pointer, otherwise.Type: GrantFiled: March 28, 2000Date of Patent: June 24, 2003Assignee: Analog Devices, Inc.Inventor: David B. Witt
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Patent number: 6584514Abstract: In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory mode, a frame mode, and a sorting mode. To increase the speed of the address modification, the index, the index in the presence of a positive wrap-around, and the index in the presence of negative wrap-around are determined together. Other apparatus determines the addressing mode and provides control signals for the selection of the correct index. The correct index is combined with the base address to provide the next new address.Type: GrantFiled: September 27, 2000Date of Patent: June 24, 2003Assignee: Texas Instruments IncorporatedInventor: Patrick J. Smith
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Publication number: 20030110348Abstract: A memory device is comprised of a plurality of arrays of memory cells and peripheral devices for reading information out of and for writing information into the memory cells. The peripheral devices include a decode circuit responsive to a first portion of address information for identifying an address and is further responsive to a second portion of the address information for identifying an order. The address may be a read address or a write address, and the order may be the order for reading data or writing data, respectively. The peripheral devices may also include a read sequencer circuit or both a write sequencer circuit and a read sequencer circuit for reordering bits to be read or written, as the case may be, in response to another portion of the address information. The necessary address information is routed to the sequencer circuits by an address sequencer. Methods of operating such a memory device are also disclosed.Type: ApplicationFiled: December 7, 2001Publication date: June 12, 2003Inventor: Jeffery W. Janzen
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Patent number: 6574723Abstract: A method of storing values that involves splitting each value into a n-bit value and an overflow value, and storing, in a main table, the n-bit values in order of increasing magnitude of the values. For each overflow value, the position of the smallest n-bit value is stored in an overflow table. To retrieve a value, the position of the corresponding n-bit value is compared to the positions stored in the overflow value to determine the overflow value of the n-bit value. The actual value is then obtained from the n-bit value and its overflow value.Type: GrantFiled: May 18, 2001Date of Patent: June 3, 2003Assignee: Seagate Technology LLCInventors: Yong Peng Chng, Aik Chuan Lim, Patrick Tai Heng Wong, Chew Boon Toh, Steven Tian Chye Cheok
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Patent number: 6574707Abstract: A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automatically change eliminates an access delay to the main memory when switching modes and optimizes system performance by providing a most critical word first in a first cache line fill and advancing to a sequential address following the first cache line. The sequential address has a higher probability of next use by the processor than any other address. The automatic mode change may be overridden by the memory interface.Type: GrantFiled: May 7, 2001Date of Patent: June 3, 2003Assignee: Motorola, Inc.Inventor: Craig D. Shaw
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Patent number: 6574724Abstract: A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value.Type: GrantFiled: October 31, 2000Date of Patent: June 3, 2003Assignee: Texas Instruments IncorporatedInventors: David Hoyle, Joseph R. Zbiciak, Jeremiah E. Golston
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Patent number: 6567900Abstract: A computer system includes multiple processors, each of which includes an associated memory. Each of the processors is capable of accessing the memory of all other processors. Memory can be stored and accessed using different addressing schemes. For data that will only be used by the local processor, data is stored in memory using processor contiguous addressing, so that data is stored in the local memory. For data that may be accessed by multiple processors, data is stored using striping among a local processor set. A stripe control register in the memory controller of each memory comprises a mask that indicates which memory blocks should be accessed using processor contiguous addressing and which should be accessed by using striped addressing. For both striped and contiguous addressing, the address space includes a processor identification field to identify the processor where the associated memory resides, together with an offset indicating where in memory the address is located.Type: GrantFiled: August 31, 2000Date of Patent: May 20, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: Richard E. Kessler
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Patent number: 6557086Abstract: A memory control system includes a frame memory divided into N image memories. Serial input image data are sequentially written onto the N image memories in rotation. Then, image data is concurrently read from each of the N image memories depending on a desired read position to produce N image data in parallel. The N image data are sorted to produce consecutive N image data in parallel.Type: GrantFiled: November 15, 2000Date of Patent: April 29, 2003Assignee: NEC Viewtechnology, LTDInventor: Youichi Tamura
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Patent number: 6553448Abstract: A technique for encoding index values of asynchronous pointers for a non-power-of-two sized buffer that supports the unit distance property. The technique includes converting N+1 pointer index values corresponding to index locations 0 through N of the buffer from the natural binary-coded decimal format to a unit distance code format such as the gray code, adding a 0 bit in the MSB position of each of the N+1 converted pointer index values, adding a first pointer index value at index location N+1 equal to the pointer index value at index location N except that a 1 bit replaces the 0 bit in the MSB position, and adding a plurality of pointer index values at index locations greater than N+1 but less than or equal to N+n+1 that are equal to the first added pointer index value, where “n” equals the number of bits in each pointer index value prior to conversion.Type: GrantFiled: March 1, 2001Date of Patent: April 22, 2003Assignee: 3Com CorporationInventor: David James Mannion
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Patent number: 6549563Abstract: In one example described, a data sequence generator for use in spread spectrum communications includes one or more read-only memories (ROMs) which have first and second spreading sequences stored therein. The first spreading sequence is associated with a first mode of communication, whereas the second spreading sequence is associated with a second mode of communication. The one or more ROMs have inputs to receive counter values and outputs for serially providing, responsive to the counter values, sequence data from either the first spreading sequence or the second spreading sequence depending on which mode of communication is selected. The first and the second spreading sequences may be unique to, for example, IS-95 and IS-2000 standards, respectively.Type: GrantFiled: October 19, 2000Date of Patent: April 15, 2003Assignees: Dot Wireless, Inc., VLSI Technology, Inc.Inventor: John G. McDonough
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Patent number: 6532468Abstract: In a binary search, two storage units are prepared so that when the least significant bit of the search address is “0” and “1”, even and odd address banks respectively are used. The search object data is classified according to data belonging to the odd and even addresses in continuous addresses and allocated to these two storage units. Further, a search tree of the search address is constructed so that two data of object for a next search are stored in different storage units. Upon the binary search, addresses for the two storage units are set according to this search tree. Therefore, simultaneous readout of data is enabled, so that readout and comparison are carried out in parallel. Further, according to multiple division search of the invention, if 2 bits of the least significant bits of the search address are “00”, “01”, “10” and “11”, a search object data is stored in first through fourth banks respectively.Type: GrantFiled: December 18, 1998Date of Patent: March 11, 2003Assignee: Kawasaki Microelectronics, Inc.Inventors: Yoshihiro Ishida, Masahiro Konishi
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Publication number: 20030037219Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asychronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: July 5, 2002Publication date: February 20, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030037218Abstract: Controller component (155) of system (100) generates address pattern (902) through employment of one or more parameters (205), to store information (810) at a plurality of parts of storage, for example, one or more instances of banked data memory (140) that are employable with multiprocessing. The one or more parameters (205) are related to the information (810).Type: ApplicationFiled: August 14, 2001Publication date: February 20, 2003Inventors: David P. Gurney, Vipul Anil Desai
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Patent number: 6519673Abstract: A memory addressing system for a multi-bank device that generally provides no band conflicts for stride 1 data access patterns and infrequent bank conflicts for power of 2 stride patterns or other access patterns of interest. In a preferred embodiment, the device comprises an address translation or remapping unit that remaps sequences of logical addresses into sequences of slightly aperiodic physical addresses such that the physical addresses do not form a repetitive pattern of period less than N+1, where N is the number of memory banks, and do not on average repeat a physical bank number within approximately N physical addresses. In large memory modules and embedded logic devices wherein multiple memory units communicate with multiple microprocessors in a single chip, the disclosed remapping combined with disclosed scrambling methods also achieves high tolerance of chip defects which would otherwise render chips unusable, thereby yielding manufacturing economies.Type: GrantFiled: March 26, 2002Date of Patent: February 11, 2003Inventors: Gregory V. Chudnovsky, David V. Chudnovsky
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Publication number: 20030028735Abstract: The present invention provides a priority encoder comprising a first, second and third resolving-encoding circuit, each of which has a plurality of input terminals receiving a plurality of requests, determines one of the input terminals receiving one of the requests as a prior terminal, and outputs a forward request and an address of the prior terminal, wherein the forward requests of the first and second resolving-encoding circuit are received as the requests of the third resolving-encoding circuit, and a multiplexer receiving the addresses output from the first and second resolving-encoding circuit, and selectively outputting one of the received addresses according to the prior terminal determined by the third resolving-encoding circuit.Type: ApplicationFiled: April 8, 2002Publication date: February 6, 2003Inventor: Ching-Hua Hsiao
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Patent number: 6516398Abstract: A data processing system and a method for accessing data therein. The data processing system includes a microprocessor, an application specific integrated circuit (ASIC), and a memory. The ASIC is coupled between the microprocessor and the memory and is utilized to communicate with an external computer system for downloading a program code from the external computer system to the memory in which the program code is stored in a memory region of the memory through the ASIC. In addition, the ASIC is for mapping the memory region onto an external memory address space of the microprocessor. The microprocessor generates an address latch enable (ALEN) signal, program memory enable (PMEN) signal, read enable (RDEN) signal, write enable (WREN) signal, and a first address signal.Type: GrantFiled: February 9, 2001Date of Patent: February 4, 2003Assignee: Acer Laboratories Inc.Inventor: Yung-Chi Hwang
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Patent number: 6516402Abstract: An initial value of read address is set in a first initial address register; an initial value of write address is set in a second initial address register; and the number of data to be accumulated by an accumulator and the frequency of repetition of accumulation are set in an accumulator count register. A controller controls the timing of output of an initial read address from a first memory controller, the timing of initialization by an initializer, and the timing of output of an initial write address from a second memory controller. Reading of data, accumulation and writing of data proceed in parallel in each cycle of accumulation.Type: GrantFiled: March 12, 2001Date of Patent: February 4, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshihiro Ogawa, Toshihisa Kamemaru, Hirokazu Suzuki
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Patent number: 6513106Abstract: A method and system for implementing a mirror addressing scheme in conjunction with a symmetrical data table are disclosed. The method includes receiving a first address. In response to determining that the first address corresponds to an upper portion of a data table, generating a second address from the first address, where the second address corresponds to a lower portion of the data table. The method further includes using the second memory address to access a memory array, whereby data corresponding to the upper portion of the data table is accessed from the lower portion of the data table. In one embodiment, determining that the first address corresponds to an upper portion of the data table is achieved by determining upper segment and lower segment boundaries for the first memory address determining that the most significant bit of the lower segment is asserted.Type: GrantFiled: November 26, 1999Date of Patent: January 28, 2003Assignee: LSI Logic CorporationInventors: Winnie Lau, Ronen Perets
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Patent number: 6507629Abstract: An address generator for generating addresses in an prescribed order in the case of writing/reading data to/from predetermined storage means, comprises a first address data generating means for generating a plurality of first address data which have predetermined address intervals, a second address data generating means for generating a plurality of second address data representing sequentially shifted positions of the first address data one row by one row within address intervals, and an addition means for generating addresses which have predetermined intervals in order by adding the second address data to the first address data.Type: GrantFiled: April 1, 1999Date of Patent: January 14, 2003Assignee: Sony CorporationInventor: Izumi Hatakeyama
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Patent number: 6507895Abstract: An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of addresses. The second set of addresses follows the first set of addresses. The second set of addresses are calculated based on a fixed stride, where the second set of addresses are associated with data from a first stream. A plurality of addresses is generated for a third set of addresses. The third set of addresses follows the first set of addresses. Each address in the third set of addresses is generated by tracing a link associated with another address in the third set of addresses. The third set of addresses is associated with data from a second stream.Type: GrantFiled: March 30, 2000Date of Patent: January 14, 2003Assignee: Intel CorporationInventors: Hong Wang, Ralph Kling, Jeff Baxter, Konrad Lai
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Patent number: 6505271Abstract: A method of generating a priority address using a priority encoder that includes the steps of: (1) providing a plurality of match signals from a CAM cell memory array to the priority encoder, (2) generating a most significant address bit of the priority address in response to a first set of the match signals, and (3) generating a least significant address bit of the priority address in response to the most significant address bit and a second set of the match signals. In one embodiment, step (3) is implemented by splitting the determination of the least significant address bit into two separate determinations, and the using the most significant address bit to select the result of one of these two separate determinations. Using the most significant address bit to help determine the least significant address bit significantly increases the speed of determining the least significant address bit, thereby increasing the overall speed of the priority encoder.Type: GrantFiled: November 12, 1999Date of Patent: January 7, 2003Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Chau-Chin Wu
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Patent number: 6505288Abstract: A digital signal processor capable of performing matrix operations, by which it is possible to use a method of matrix representation for the instruction level of the digital signal processor in order to effectively process a large amount of data, is provided.Type: GrantFiled: August 16, 2000Date of Patent: January 7, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-rang Jang, Hyun-woo Park, Jin-ckuc Cho
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Patent number: 6499083Abstract: A disk-based storage system for storing a plurality of data segments responds to a direction-selection signal by autonomously providing the data segments in a selected sequence so as to be concatenated together to define a continuous data stream. The disk-based storage system comprises nonvolatile storage including rotating disk media having a plurality of addressable locations. Each of the data segments is stored in a respective one of the addressable locations. Each of the addressable locations has a leading end and a trailing end. A first one of the addressable locations has a trailing end on a first track, and a second one of the addressable locations has a leading end on a second track, the second track being spaced from the first track. The non-volatile storage provides for locally storing a doubly-linked list of pointers.Type: GrantFiled: September 15, 1999Date of Patent: December 24, 2002Assignee: Western Digital Ventures, Inc.Inventor: Christopher L. Hamlin
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Patent number: 6493815Abstract: An interleaving method comprises storing input data in a memory according to a sequential address; providing a virtual address determined by adding a predetermined value to a size of the input data so that a partial bit reversal ordering interleaving rule is satisfied; matching the virtual address to an address interleaved according to the interleaving rule; and reading the input data from the memory using an address other than the address corresponding to the specific value, out of the interleaved addresses.Type: GrantFiled: December 27, 1999Date of Patent: December 10, 2002Assignee: Samsung Electronics, Co., Ltd.Inventors: Min Goo Kim, Beong-Jo Kim, Young-Hwan Lee
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Publication number: 20020184468Abstract: An address sequencer circuit for generating addresses for accessing a memory device. The address sequencer includes a plurality of address stages that are coupled together, and also includes a first clock generation circuit that receives an input clock and generates a first clock signal that is coupled to a first portion of the address stages. A second clock generation circuit is provided that receives the input clock and a toggle signal and generates a second clock signal that is coupled to a second portion of the address stages, thereby allowing the first and second portions of address stages to be clocked at different rates.Type: ApplicationFiled: July 30, 2001Publication date: December 5, 2002Inventor: Takao Akaogi