Abstract: In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on a memory having memory banks operable independent from one another. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth (where k=0, 1, 2, . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.

Abstract: An apparatus and method for detecting an operation value using a look-up table at high speed, which not only minimizes the size of the look-up table but also satisfies a desired error rate. The apparatus includes a means for storing seed values corresponding to seed points determined according to the range of the input data and output data and an error rate, an address and data generator for comparing a predetermined reference value with the input data to generate an address of the storing means and revised input data corresponding to the input data, and an operator for performing a predetermined operation using the seed values output from the storing means and the revised input data generated by the address and data generator to output an operation value corresponding to the input data. Accordingly, an operation value having a minimum error rate can be provided with a small sized memory.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by defining a current memory address, choosing one or more modes by which increment-generated, decrement-generated, or combination increment/decrement addresses that define a next memory address are generated, and generating the row address and the column address of the next memory address in accordance with interdependent row carry-out and column carry-out operations.

Abstract: The inventive state mechanism assigns N+1 tags to N versions of an object stored in N memory areas. Thus, one tag is unused. An additional tag is used as a null or uninitialized tag. The other tags are assigned in a particular precedence order to revisions as they are stored. Thus, each assigned tag, except the null tag, has both a unique predecessor as well as a unique successor tag. The last tag of the sequence is lower in precedence to the first tag of the sequence, and this forms the cyclic relationship. The unused tag is used to determine the tag that is to be assigned to the next revision. The unused tag is also used to determine which revision is the most current revision. The inventive state mechanism is used by a memory management controller in maintaining the revisions.

Abstract: A system, method, and program for detecting and assuring a row by column structure in a Dynamic Random Access Memory array is disclosed. By writing to and reading from each memory location of the DRAM array, memory integrity is assured. The number of columns in the DRAM array is identified by writing data to and reading data from addresses selected from a series of cell addresses. The series of cell addresses identify standard DRAM column structures. When the data written to and read from the cell address is identical, the column configuration of the DRAM arrays is identified. The number of rows in the memory array is then identified by writing data to and reading data from addresses selected from a second series of cell addresses. The second series of cell addresses identify standard DRAM row structures. When data written to and read from the cell address is identical, the row configuration of the DRAM array is identified and accordingly, the row by column structure and integrity of the DRAM array are known.

Abstract: A method and system in a data storage system for reading stored data from the data storage system, where the data storage system comprises N data storage drives and an associated cache, where data and calculated parity are striped across the N data storage drives, where a stripe comprises multiple sectors on each of the N data storage drives. Data is requested from the data storage system. A determination is made of whether or not the requested data currently resides in a cache associated with the data storage system. In addition, a determination is made of whether or not the requested data sequentially follows other sectors also residing in the cache. Only the requested data is fetched into the cache if it is determined that the requested data does not reside in the cache and the requested data does not sequentially follow sectors in the cache.

Abstract: When memory size is increased by a factor of 2N (where N is an integer equal to or greater than unity) in a protocol-based memory system where a memory controller and multiple bus interfaces are interconnected via a bus, there exists a mismatch of N bits between the address format of each bus interface and that of the memory controller. In an initialization method for the memory system, one of the bus interfaces is enabled and request packets are transmitted successively from the memory controller to the enabled bus interface. Each packet contains a unique device identifier for identifying each bus interface. The packets of successive 2N arrivals are received at the enabled bus interface and an identifier for this bus interface is established using the device identifier contained in a predetermined one of the received packets by ignoring one or more device identifiers contained in other 2N−1 received packets.

Abstract: Input subband samples are requantized by a requantizing circuit and the results are stored in a DCT memory as DCT samples for discrete cosine transform. A DCT circuit applies a discrete cosine transform to the DCT samples stored in the DCT memory and stores the results in a band synthesis memory as band synthesis samples. When storing these band synthesis samples in the band synthesis memory, the storage area for each band synthesis sample is designated by alternately switching between two types of addresses generated by a first and second address generating circuits and the timing of processing by the DCT circuit is controlled in accordance with the band synthesis samples necessary for the calculation of output audio samples.

Abstract: A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.

Abstract: The invention provides a volatile or non-volatile memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a synchronous portion of the code. Accordingly, the data at the next memory address is used as a succeeding address and a subsequent portion of the code. The data is organized to repeat when the data stored in the address location is equal to the starting address.

Abstract: A pipelined processor in which the decoder can consume a portion of an instruction and hold that portion in sub-field shadow registers while retrieving the remainder of the instruction in a subsequent cycle or cycles. Each byte in a prefetch buffer is individually tagged such that the decoder can clear individual bytes in the prefetch buffer in order to allow additional instruction bytes to be prefetched before the current instruction is completely consumed and decoded by the decode stage. This allows for an optimal buffer size that is less than the maximum possible instruction length but large enough to hold a complete copy of the vast majority of instructions.

Abstract: A reproducing apparatus which comprises a reproducing part having a first reproducing mode and a second reproducing mode different from the first reproducing mode and arranged to reproduce a signal recorded on a recording medium, a detection part for detecting a recording time of the signal recorded on the recording medium, and a control part for switching the reproducing part between the first reproducing mode and the second reproducing mode according to the recording time detected by the detection part.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.

Abstract: A data processing system (15) including a synchronous random access memory (30) and a method for accessing the synchronous random access memory are disclosed. A digital processor (20) of the data processing system is coupled to a system clock circuit (65) that produces a system clock signal for controlling operation of the digital processor. Addressable storage cells within the synchronous random access memory are accessed in response to the system clock signal and an address select signal (ADS) to write data into the storage cells or read data out from the storage cells. Initial row and column addresses are latched into a row address buffer (48) and a column address buffer (49). The data are read out from the memory in an order corresponding to a control signal (WT) in synchronization with the system clock signal. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed virtual-linear-physical address in a system using segmentation and optional paging. This fast physical address is used for a tentative or speculative memory reference, which reference can be canceled in the event the fast physical address does not match the fully computed address counterpart. In this manner, memory references can be accelerated in a computer system by avoiding a conventional translation scheme requiring two separate and sequential address translation operations—i.e. from virtual to linear, and from linear to physical.

Abstract: A system and method dynamically allocate memory to a RAM disk. Upon a file transfer to the RAM disk, a device driver determines an amount of memory required by the RAM disk then requests the required amount of memory from a memory manager. As files are deleted from the RAM disk, the memory is released from the RAM disk by informing the memory manager of the addresses of the memory to be released. Sector freelists tracks each cluster of memory allocated to the RAM disk. When a sector becomes inactive, a corresponding bit in a sector freelist indicates the inactive status of the sector. When all of the sectors in a cluster are inactive, the cluster is released for the RAM disk.

Abstract: A semiconductor circuit of the present invention comprises, a decoder responding a plurality of address signals to produce a plurality of decoded address signals, a plurality of switch circuits receiving the respective decoded address signals, each switch circuits outputting an output signal, a plurality of registers receiving the respective output signals, each registers outputting a latched output signal, and supplying the latched output signal to the switch circuits except the switch circuit corresponding to that particular latched output signal, and a control circuit generating a control signal in response to a part of the address signal, the switch circuit outputting one of the decoded address signal and the latched output signal as said output signal according to the control signal.

Abstract: The invention provides a method and apparatus that provides for a determination of a memory address for an object coordinate in a non-linear addressing scheme. To minimize computation complexity, the memory address of the object coordinate is based upon a previously computed address of an object coordinate that is in proximity to the given object coordinate.

Abstract: A controller chip has programmable registers that control the operation of the controller chip. The controller chip connects to a microprocessor and bus controller through a bus that performs burst cycles. Although only one address (the starting address) is sent over the bus during the burst cycle, multiple data words are sent in the burst. These data words are written to addresses that follow the starting address in a fixed burst sequence. Programmable registers are accessed in an order that is not the fixed burst sequence. The programmable registers are accessed in a non-sequential order in a single burst cycle by using a mapping control word. The starting address is is set to the address of a mapping control register in the controller chip. The mapping control word is sent as the first data word after the starting address. The mapping control word is decoded to determine which of the programmable registers are to be written during the burst cycle.

Abstract: A linked data structure verification system to verify the integrity of at least one linked data structure simultaneously by way of a verification setup phase and an integrity verification phase. Individual nodes are retrieved from a memory device and examined seriatim in optimal memory device location order. Nodes are retrieved and examined in optimal memory device location order for maximum memory device retrieval performance. Expected and/or actual node information about nodes in a given linked data structure are temporarily stored as records in an integrity verification table for only as much time as is necessary to verify any part of the node information prior to excising one or more unnecessary records from the integrity verification table.

Abstract: The present invention provides a memory system that retrieves data based upon redundant form address data. The memory system includes a memory having a plurality of memory lines and an address decoder that enables one of the memory lines in response to a redundant form address signal. A redundant form decoder decodes redundant form data into a differential pair of decoded address lines for each bit position of a memory address. One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line by memory line basis, using the address of the memory lines themselves. The redundant form address decoder avoids a completion add that would otherwise be required, yielding very fast access to memory.

Abstract: A prefetch controller includes a request address register containing an address associated with an access request, an address history table containing a history of accessed addresses, an adder generating a prefetch address, a plurality of subtracters each generating a difference between the address contained in the address history table and the address stored in the request address register, a selector selecting the output of one of the subtracters, and an address controller updating the address history table according to the address difference generated by the subtracter and issuing a prefetch request to cache memory. When a processor accesses data located at a regular interval, the prefetch controller predicts the address the processor is going to access and prefetches data at the address into the cache memory.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: A method for searching for a record in a table in a memory of a computer system. A table of records is organized into a group of arrays. A hashing algorithm locates a record in the table. Multiple hashing functions are executed concurrently, according to the number of arrays in the group, such that the record can be located relatively quickly in one of the arrays in the group. The table is analyzed to determine the information content of each bit in a string of bits comprising an index value associated with the table, according to Shannon's formula for information-theoretic entropy. The entropy associated with each bit in the string of bits provides a basis for selecting a subset of bits in the string of bits from which to obtain the seed values utilized in the hashing functions. A rotating mask, based on Neumann's code, is applied to the subset of bits to obtain different seed values for each of the hashing functions, thereby minimizing the correlation of the keys provided by the hashing functions.

Abstract: A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions.

Abstract: A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower portion is addressed by the seven least significant bits which are extracted from an input address bus (50). The seven address bits are latched in an address latch (54) for input to the address input of the memory (30). An eighth most significant address bit is received from an external line (64), which is attached to a separate bus on a personal computer other than that of the bus (50). The eighth most significant bit is latched in an address latch (62) for presentation to the most significant bit of the address input memory (30). When this most significant bit is high, the upper portion of the memory (30) is accessed.

Abstract: A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

Abstract: The present disclosure concerns a method and apparatus for accessing a memory device, such as a dynamic random access memory (DRAM). The DRAM has a plurality of rows, wherein each row has a plurality of DRAM paragraphs comprised of a plurality of contiguous columns. A linear shift register (LSR) translates a plurality of logical addresses to corresponding physical address locations in the DRAM. Each translated physical address is comprised of a row address and a column address. A physical address, including the row and column addresses, is accessed from the LSR. To access the DRAM paragraph at the accessed physical address, the row in the DRAM at the accessed row address location is strobed to setup and precharge the row. Following, all columns in the DRAM paragraph at the accessed physical address are strobed. After strobing the columns in a DRAM paragraph, the next physical address in the LSR, including the next row and column addresses, is accessed.

Abstract: An improved apparatus and method for providing addresses for accessing circular memory buffers is provided. An apparatus comprised of a first feedback circuit, a second feedback circuit, a beginning address register, an ending address register, and a comparator circuit. A control circuit is also provided. The beginning and ending address registers preferably include the beginning and ending addresses respectively of a circular memory buffer. The first feedback circuit is comprised of a first register, a first phase delay register, a first adder, a first displacement register, and a first multiplexer. The second feedback circuit is preferably comprised of a second register, a second phase delay register, a second adder, and a second displacement register.

Abstract: The invention relates to a digital signal processor in which two multiply accumulate operations are carried out in one machine cycle. Only one address generation unit is required for addressing two data words of both the X and Y memories, since in the main processing loop the least significant address bit is considered as "Don't care", so that an access operation to the memory results in two output data words at a time.

Abstract: A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

Abstract: A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

Abstract: An address routing scheme supports a variety of memory sizes and interleaving schemes. In one embodiment, any address bit provided by the processor can be routed to any bank, row, or column bit, and can be used to generate any rank bit. This embodiment supports any type of interleaving scheme and memory modules constructed from a wide variety of DRAM chips. In another embodiment, a reduced routing function is used to generate rank bits and route address bits to subsets of bank, row, or column bits such that no route function encoding requires more than 3 bits. The second embodiment supports multi-cache line interleaving, cache effect interleaving, and DRAM page interleaving. Multi-cache line causes cache lines contained in small contiguous blocks to be contained in one DRAM page, while contiguous small contiguous blocks are stored on separate DRAM pages.

Abstract: An address processor (205) receives contiguous row and column addresses from an address decoder (151). In response, the address processor (205) applies a scattering function to the contiguous row and column addresses to produce scattered row and column addresses of scattered locations in the memory (155).

Abstract: A cache memory control system includes a cache memory to store a copy of a subset of data which is stored in the main memory and a cache controller to control data caching and data replacement for the cache memory. Upon a cache miss, the cache controller replaces data in the cache memory with the read requested data and a plurality of data which are adjacent to that read requested data on a display screen.

Abstract: A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write control unit, each time N units of data and an address indicative of a storage location next to this data is written into the shared memory, one of the written addresses is stored in a second memory provided separately from the shared memory. Each time N addresses are read from the shared memory, an address stored in the second memory is read to detect in a detector whether or not the address is erroneous. If an error is detected, the erroneous address is discarded.

Abstract: A semiconductor memory device is provided with a determination circuit and an address adder. The determination circuit determines whether a read start address selects upper-address banks B5-B8 or lower-address banks B1-B4. When the determination circuit determines that the lower-address banks are selected, the address adder increments a column address by 1. From the upper-address banks, data are read from the columns corresponding to the read start address. From the lower-address banks, data are read from the columns that are next to the columns corresponding to the read start address. Even when the upper-address banks are designated by the read start address, the data output from the lower-address banks corresponds to the next columns. Since there is no busy time during data output, successive access is enabled and the access cycle time can be as short as possible.

Abstract: A parallel type of memory is divided into P sub-arrays with which there are associated column and row decoding circuits and read circuits. Circuits are used to produce and give P addresses simultaneously to the decoding circuits on the basis of a given address so as to enable the simultaneous reading of P words from a single address. Circuits receive the P information elements extracted from the P words and give them in series at an output port at a frequency greater than the reading frequency. Thus the access time to the information elements seen from the exterior of the memory is reduced.

Abstract: A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache line has L/W banks, the lowermost bank being in an odd position and the uppermost bank being in an even position. In a request for a particular data entity, a series of addresses are issued on the address bus to fill the associated cache line. The first address is always for a particular cache bank to which the particular data entity is mapped. The remaining addresses are sequenced ascending linearly, modulo L. If the particular data entity is mapped to an even cache bank, but not to the uppermost cache bank, then L/W remaining addresses are issued, beginning with the base address of the cache bank immediately following the cache bank to which the particular data entity is mapped.

Abstract: The invention provides a read-only memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a synchronous portion of the code. Accordingly, the data at the next memory address is used as a succeeding address and a subsequent portion of the code. The data is organized to repeat when the data stored in the address location is equal to the starting address.

Abstract: Method for increasing data-processing speed in computer systems containing at least one microprocessor, a memory device, and a so-called cache connected to the processor, in which the cache is arranged to fetch data from the addresses in the memory device requested by the processor and then also fetches data from one or several addresses in the memory device not requested by the processor. The computer system includes a circuit called the stream-detection circuit, connected to interact with a cache such that the stream-detection circuit detects the addresses which the processor requests in the cache and registers whether the addresses requested already existed in cache. The stream-detection circuit is arranged such that it is made to detect one or several sequential series of addresses requested by the processor in the cache.

Abstract: A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a first input and a displacement as a second input. The adder for adding the inputs to provide an output. A comparator compares the current address pointer to an ending address of a circular buffer ignoring least significant bits thereof when the displacement is greater than one. The comparator provides an output that is a first state when the inputs are the same and an output that is a second state when the outputs are different. A control circuit is adapted to receive an indicator of the beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer.

Abstract: The inventive prediction mechanism constructs a time ordered state space of the file accesses, and then searches the state space looking for file accesses that form either sequential or stride patterns. A cache is maintained to store information about existing patterns. The mechanism will review the cache to determine if a new access request is a continuation of an existing pattern before searching the entire state space for a new pattern. If the request is either a continuation of an existing pattern or forms a new pattern, then a read ahead is issued for the next block in the pattern. The cache and the state space are updated as each request arrives. The mechanism uses a trigger array to prevent the re-issuing of predictions. The mechanism also has a strength feature which is an indication how many times the pattern has been continued, and can be used by the operating system in deciding how many read aheads should be issued.

Abstract: An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.

Abstract: A method and hardware apparatus for data prefetching. In one embodiment, the method of the present invention comprises first calculating a local stride value by computing the value between two address references of a first load instruction. The local stride value of the first load instruction is used as a global stride value for address prefetching for a second load instruction, where the second load instruction is different from the first load instruction. An appropriate global stride value is added to a previous address value associated with a previous occurrence of the second load instruction, producing an address location for prefetching a block of data.

Abstract: The present invention relates to a modulo address generator and method thereof. The apparatus includes an adder which adds a current address value and an address increment value to generate an incremented address value. Also included is an adder/subtracter circuit which adds a data region size value to the incremented address value when the sign bit of the address increment value is negative and subtracts the data region size value from the incremented address value when the sign bit is positive in order to generate a revised address value. An output selection circuit selects either the incremented address value, when the sign bit is negative, or the revised address value, when the sign bit is positive, for comparison to a minimum address of the data region in order to generate a comparison result value.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a sign detector adapted to determine whether a sum of an address pointer and a precomputed comparison term is of a first state or a second state. A first adder adds an address pointer and a precomputed correction term to generate a first potential next address pointer. A second adder, operating in parallel with the first adder, adds the address pointer and a displacement to generate a second potential next address pointer. A selector adapted to select the first potential next address pointer as an output when the sign detector output and a sign bit of the displacement are different, and to select the second potential next address pointer as an output when the sign detector output and a sign bit of the displacement are the same.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A carry-save adder adapted to receive as inputs an inverted representation of the first selector output, an address pointer, and a displacement. The carry-save adder is adapted to add the inputs to produce sum bits and carry bits as outputs. A sign detector adapted to determine whether a sum of the sum bits and carry bits is greater than or equal to zero, or less than zero, and for providing an output indicative of whether the sum is greater than or equal to zero, or less than zero.

Abstract: A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.