Abstract: Controller component (155) of system (100) generates address pattern (902) through employment of one or more parameters (205), to store information (810) at a plurality of parts of storage, for example, one or more instances of banked data memory (140) that are employable with multiprocessing. The one or more parameters (205) are related to the information (810).

Abstract: A circular buffer control circuit, a method of controlling a circular buffer and a digital signal processor (DSP) incorporating the circuit or the method. In one embodiment, the circuit includes: (1) address calculation logic, having multiple datapaths, that calculates, from data regarding a buffer operation, an updated address result therefor and (2) modification order determination circuitry, coupled in parallel with the address calculation logic, that transmits a memory access request and the updated address result in an order that is based on whether the buffer operation is pre-modified or post-modified.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: The present disclosure relates to an address sub-sampling apparatus and method, and an image sensor employing the same. An address sub-sampling apparatus includes a counting unit that generates a binary address of N bits, N being a natural number larger than 2. The address sub-sampling apparatus also includes an address conversion unit that sub-samples the binary address of N bits to output a sub-sampled address having first, second and third bit groups, wherein the sub-sampled address is arranged in order of the third, the first and the second bit groups from the MSB (Most Significant Bit).

Abstract: A system for detecting/avoiding memory usage conflicts when generating and merging multi-threaded software test cases. Initially, a test case generator is given a unique segment of memory which it can use. A plurality of test cases are generated, one at a time, by the test case generator. When the first test case is generated, the memory segment used is noted. When each of the second through Nth test cases is generated, a memory segment of the same size as the first test case, but not overlapping that of the previously assigned test case(s), is assigned to each subsequent test case.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A system for recording data to a disc shaped record medium. The data is recorded according to a universal disc format employing a hierarchical file system, and data within the hierarchical structure is referenced using pointer information. The pointer information includes a file identifier descriptor and a file entry and is recorded such that the pointer information and its corresponding substantive data are stored at successive addresses.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: There is disclosed a method and apparatus for mapping between logical and physical addresses in a solid state data storage device, particularly but not exclusively a magnetic random access solid state data storage device, in which a list of mappings between ranges of logical addresses and ranges of physical addresses are stored in a data table, the mappings being operated on to look up a physical address from a logical address and vice versa, and being operated on by a data processor, to amend the data mappings by introduction of new ranges of logical and physical addresses, upon ranges of individual physical memory elements becoming defective.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: An access circuit for efficiently accessing a buffer memory in accordance with an instruction from an external circuit. An access data unit for accessing a SDRAM in one operation clock cycle of the access circuit may be switched between one byte, one word, and two words. The switching of the access data unit is performed in accordance with a data unit designation signal generated by decoding address data, which is provided to a control unit, with an address decoder. The memory interface receives a request signal that is in accordance with the data unit designation signal from a request generator and accesses the buffer memory in the access data unit that is in accordance with the request signal.

Abstract: An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.

Abstract: An application program (6) may issue a file access request to an operating system (4) accompanied by a caching hint. This caching hint may be selected in dependence upon the file type and file size of the computer file to which access has been requested. The data defining which hint type is to be used for each combination of file type and file size may be adaptively updated depending upon measured performance for the different hint types. The hint defining data may be initialised in dependence upon the operating system version and the installed memory size of the computer system concerned.

Abstract: A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address vector from the non-sequential addresses, and using the address vector in a block fetch command to a data store.

Abstract: In order to sort signal group elements organized in blocks in a time-division multiplex protocol into frames of related elements, an address unit addresses the first element in each of the element blocks, then the second element in each element block, etc until all of the elements of all of the blocks have been addressed. In this manner, the related elements are sorted into frames of elements. The address unit performs this element sorting using a base address, an element index equal to the number of elements in a block, and a frame index equal to {the number of elements times (the number of frames minus one)} minus one as parameters.

Abstract: A memory array or structure and method for decoding a read address to facilitate simultaneous reading of successive rows. The memory includes row decoders in the form of decoding logic for enabling multiple rows of the memory structure to be read in response to a single row address. The memory structure helps to reduce the number of ports that are required for the memory structure and, thus, reduces the die area occupied by the memory structure. The row address may be divided into most significant bits and least significant bits. Further, the decoding logic may decode the most significant bits differently from the least significant bits when processing the row address. The most significant bits may be preprocessed or predecoded into a fully decoded format while the least significant bits may be decoded into a priority decoded format.

Abstract: A data formatter includes a shift register and a pointer manager. The shift register receives data from a providing RAM and shifts that data in response to reading data from the providing RAM and writing data to a receiving FIFO. A pointer manager maintains a pointer that points to a first valid byte in a sub-block of data into the correct bytes lanes of the FIFO by moving the pointer as data is shifted into and out of the shift register.

Abstract: The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.

Abstract: A parallel memory configured to enable access to a table with aligned and equidistant components constituting a vector of N components. The memory (1) is organized as M memory banks (8). Each memory bank (8) includes an address calculator. The memory (1) also includes a unidirectional network (6) configured to carry out a permutation of the N components of the vector being accessed and to carry out a translation by a specified value t of the components of the vector.

Abstract: A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes a segment length field describing the length of memory reserved for the data record and the data record contains at least one data instance object. Each of the data instance objects has a data instance header and data field. The header includes a data instance state field and a data instance length field. The data instance length field contains data representing the length of the data instance data field allowing for variable length “in place” updating. The data instance state field contains data representing an object state of the instance data. Only one of the data instance objects of the data record of the single segment data object has a valid object state. The state field facilitates a power loss recovery process.

Abstract: A linear and non-linear object management method and structure. A data structure on a computer-readable medium is used to store linear and non-linear objects in a range of memory of a volume. The data structure includes a contiguous range of memory in which the data objects are stored. A plurality of data objects are stored contiguously in the range of memory and are associated with a first or second list in the range of memory. The plurality of data objects include a first-type of data object having a data field in linear objects are stored and further include a second-type of data object having a data field containing non-linear data objects.

Abstract: A circular buffer for use in a telecommunications system is described as well as a method of operating the same in which data is protected during wraparound procedures. In the operation of the circular buffer at least four reference values are stored to enable address calculations: a first reference value representative of a begin address of the circular buffer; a second reference value representative of an end address of the circular buffer; a third reference value representative of a current write address of the circular buffer; and a fourth reference value representative of a current read address of the circular buffer. The cyclic state of the buffer is also monitored in order to protect the data after a wraparound or when the buffer is full. The buffer is able to accommodate multirate data arrival.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: A data processing system may include an interconnect and first and second components coupled to the interconnect for data transfer therebetween. The first component contains a write pipeline that includes an address register and a queue including storage locations for a plurality of data granules. In response to receipt of a plurality of data granules that are each associated with a single address specified by the address register, the queue loads the plurality of data granules into sequential storage locations in order of receipt. Upon the queue being filled with a predetermined number of data granules, the queue outputs, to the second component via the interconnect, the predetermined number of data granules at least two at a time according to the order of receipt. Thus, data transfer efficiency is enhanced while maintaining the relative ordering of the data granules.

Abstract: A semiconductor device with adjustable number of pages and page depth is disclosed. The semiconductor device includes multiple memory cell array blocks, a page control circuit for generating a control signal which varies the number of pages and the page depth in response to a page control signal, and a sense amplifying and write driving circuit. The page control circuit controls a row address and a column address to generate the control signal, that is, to vary the number of pages and the page depth. The sense amplifying and write driving circuit senses, amplifies and outputs data from a memory cell array block, and writes data into a memory cell array block in response to the control signal. The page control circuit includes an address buffer, a block controller and a control signal generator. The address buffer buffers the most significant bit (MSB) of the row address and outputs the buffered result, or ignores the MSB depending on the page control signal.

Abstract: A ROM is provided with sufficient input address terminals for receipt of a unique address for each data storage location, even though the number of ROM input addresses exceeds the capacity of the processor and address bus. A dual mode read operation includes a random address mode for randomly accessing the ROM and a sequential address mode for accessing sequentially stored data strings at a high access rate. A first portion of the bus addresses are allocated as random reading mode bus addresses, the bus addresses having direct correspondence with ROM addresses. Other bus addresses are allocated as sequential reading mode bus addresses for addressing the ROM in sequential ROM address order for reading data. Successive output by the processor of the same sequential reading mode bus address effects application to the ROM of sequentially numbered ROM addresses. The first numbered address of the plurality of the sequential ROM address string is loaded as data into at least one counter.

Abstract: Interleavers are used in data transmission and storage applications to introduce diversity into a data stream, thereby making adjacent symbols more independent with respect to a transfer environment of variable quality. Conventional interleavers require storage in whole units of data blocks. This storage requirement complicates implementations for applications where available circuit area is limited and data rates and block sizes are large. A novel interleaver produces an interleaved data block using storage space that is only a fraction of the size of the input data block.

Abstract: A switching router memory map is organized as 64-bit wide double words. The bi-directional data bus is only 32-bits wide, so the Least Significant Words (LSW) are mapped to the even addresses and the Most Significant Words (MSW) are mapped to the odd address. When the host writes to the even address the 32-bit data is stored in the bidirectional data bus buffer. When the host writes to the odd address the entire 64-bit double word access is posted to the appropriate global access bus. When a read operation is performed from an even address the entire 64-bit double word access is performed by the appropriate global access bus. The LSW is available on the bi-directional data bus address data pins and the 32-bit MSW is buffered within the bi-directional data bus. The host can access the MSW by performing a read from the odd address.

Abstract: A memory controller comprises a programmable interface coupled to address circuitry. The programmable interface receives a configuration signal into the memory controller indicating a selected address configuration. The address circuitry processes system addresses based on the selected address configuration to generate memory addresses. The configuration signal may also indicate a selected memory configuration, and the address circuitry processes the system addresses based on the selected memory configuration to generate memory device selections.

Abstract: A method and system for installing software on a computer generates an installation order that ensures that a component required for the functioning of another component is already installed. Furthermore, it makes possible generating good installation orders to allow related components, e.g., in a software suite, to be installed close together, thus reducing disk swapping. The method and system take into account the existing configuration on a computer and allow removal of components along with dynamic reconfiguration of a computing system in response to a user's choice of an application program to launch. In accordance with the invention, preferably a developer includes information about the component's relationship with other components, e.g., a specific requirement for a preinstalled component or a requirement that a particular component not be present, thus requiring its removal.

Abstract: A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.

Abstract: A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized word in the cache line are compared with the upper bits of the cache line's effective address. If the upper bits of the address-sized word match the upper bits of the effective address, the address-sized word is identified as a candidate virtual address.

Abstract: Methods and apparatus enable: the partitioning of a main memory into a plurality of blocks, each block being adjacent to at least one of the other blocks, and each block including a plurality of data units containing one or more bits of data; the partitioning of each block of the main memory into a plurality of zones, each zone containing one or more of the data units; the association of at least some of the respective zones of each given block with respective others of the adjacent blocks to the given block; and the pre-fetching of a given one of the other blocks into a cache memory when any one of the data units within any of the associated zones of that block is addressed.

Abstract: Methods and apparatus are provided for use in digital information processors that support digital memory buffers. In one aspect of the present invention, a digital signal processor receives a swap instruction and responds to the swap instruction by swapping the contents of a first address register and a second address register. In another aspect, a digital signal processor receives a swap instruction, swaps the contents of a first address register and a second address register in a future file, generates and sends one or more control signals to an architecture file in a downstream stage of a pipeline in response to the swap instruction, and swaps the contents of the first address register and the second address register in the architecture file in response to the one or more control signals.

Abstract: Among the embodiments of the present invention is a processor (22) having a number of registers in a register bank (50). The registers include a general purpose register (52a) and a stack pointer register (52b) having a common register name. Processor (22) includes logic responsive to programming to perform a program instruction that references the common register name. This instruction is performed with general purpose register (52a) under a first condition and with stack pointer register (52b) under a second condition. Accordingly, multiple registers identified by the same name can be selectively accessed based on the establishment of certain conditions.

Abstract: An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

Abstract: A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 1 to N and reading the stored bit symbols from the memory. The device comprises a look-up table for providing a first variable m and a second variable J satisfying the equation N=2m×J; and an address generator for generating a read address depending on the first and second variables m and J provided from the look-up table. The read address is determined by 2m(K mod J)+BRO(K/J), where K (0≦K≦(N−1)) denotes a reading sequence and BRO is a function for converting a binary value to a decimal value by bit reversing.

Abstract: A high-function address generating apparatus is realized which generates a memory address that can access a multidimensional area without running over a memory area specified by a user. Continuous addressing domain which is determined by a top address and a final address is set by an addressing domain setting means 101, an address is generated by a two-dimensional address generating means 106, the address in a two-dimensional area is compared with the final address and the top address by a first and a second comparing means 108 and 109, respectively, whether it runs over the addressing domain or not is judged by an address correction means 112, and an address running over is corrected so as to not run over.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A method for creating a mark stack for use in a moving garbage collection algorithm is described. The algorithm of the present invention creates a mark stack to implement a MGCA. The algorithm allows efficient use of cache memory prefetch features to reduce the required time to complete the mark stack and thus reduce the time required for garbage collection. Instructions are issued to prefetch data objects that will be examined in the future, so that by the time the scan pointer reaches the data object, the cache lines for the data object are already filled. At some point after the data object is prefetched, the address location of associated data objects is likewise prefetched. Finally, the associated data objects located at the previously fetched addresses are prefetched. This reduces garbage collection by continually supplying the garbage collector with a stream of preemptively prefetched data objects that require scanning.

Abstract: A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.

Abstract: An address counter and address counting method is provided for enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external address or a previous internal address is inputted and further generating both a path for the case when a parity signal having a high state is inputted and a path for the case when a parity signal having a low state is inputted. While the paths are being produced, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Moreover, an operation of latching the next address is terminated as soon as the parity signal is generated.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock because the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: A data storage system randomly determines a start offset at which to write objects to a storage medium. For updated blocks of the object, e.g., for blocks written during copy-on-write as part of a point-in-time snapshot, the updated block is written in the region of the original file or as close thereto as possible to achieve “virtual contiguity”. Subsequent reads of the object read entire region containing both the object and, potentially, “chaff” data other than the object. The “chaff” data is discarded by the I/O system or file system using, e.g., a bit mask, subsequent to the read.

Abstract: The present invention provides a register-indirect addressing mode using modulo arithmetic to transpose addresses for digital processing systems. The preferred systems and methods permit direct access of column data, which improves matrix computation significantly. The overhead of transpose mode is minimal because it can be implemented, if desired, by sharing hardware and/or software used in circular buffers. Transpose addressing mode also reduces program size and processor power consumed by reducing the sequence of instruction cycles.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).