Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

Abstract: A method for an associative memory device includes storing a plurality of pairs of N-bit numbers A and B to be added together in columns of a memory array of the associative memory device, each pair in a column, each bit in a row of the column, and dividing each N-bit number A and B into groups containing M bits each, having group carry-out predictions for every group except a first group, the group carry-out predictions calculated for any possible group carry-in value, and, once the carry-out value for a first group is calculated, selecting the next group carry out value from the group carry-out predictions. The method also includes repeating the ripple selecting group carry-out values, until all group carry out values have been selected.

Abstract: A system and method for sanitizing a mass storage device on a host computer which includes a control system which receives input which starts a process of sanitizing a mass storage device, which includes a switch which isolates the mass storage device from an input interface that is used in normal operations and provides signals from an alternate input to the mass storage device to sanitize the mass storage.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising assigning a plurality of data streams to a block family comprising a plurality of blocks of a memory device; responsive to programming a first block associated with a first data stream of the plurality of data streams, associating the first block with the block family; and responsive to programming a second block associated with a second data stream of the plurality of data streams, associating the second block with the block family.

Abstract: A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.

Abstract: A system is provided that includes multiple different consistency groups, a respective thin journal included in each of the consistency groups, and each thin journal includes a respective thin VMDK, a thin journal space that is shared by all of the consistency groups, and the journal space includes a plurality of journal blocks, and a datastore that stores blocks allocated to the thin journals, and datastore space is dynamically allocated in journal blocks to each of the respective consistency groups.

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

Abstract: A host operation to be performed can be received. Sub-operations that are associated with the received host operation can be determined. A memory component of multiple memory components can be identified for each sub-operation. Furthermore, each sub-operation can be transmitted to a media sequencer component that is associated with a respective memory component of the memory components.

Abstract: Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.

Abstract: Described is a system (and method) for efficient access-based reallocation of backup data stored within an object storage. The system may implement various specialized procedures to efficiently store and manage backup data within the object storage. These procedures may include packing backup data into objects to improve data operation efficiency. The system may also conserve storage space on the object storage by performing an analysis to reallocate backup data as necessary. For example, data may be stored in objects in an immutable manner, and thus, the system may efficiently reallocate data to new objects based on data access patterns. For example, the system may determine an access pattern associated with live data remaining within the first object satisfies a condition, and in response, reallocated the live data to a new object.

Abstract: A system and method comprising: receiving a request to write data stored at a first range of a first volume to a second range of a second volume, where first metadata for the first range of the first volume is associated with a range of physical addresses where the data is stored in the storage system; and responsive to receiving the request: creating second metadata for the second range of the second volume, wherein the second metadata is associated with the range of physical addresses where the data is stored in the storage system; and associating the second volume with the second metadata.

Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller is configured to issue a command to the non-volatile semiconductor memory device specifying a subset of n buffers of the plurality of buffers in which to transfer a data payload relating to the command.

Abstract: An information management system can detect instances in which data is being stored in a non-standard file path and can alert the user of the client computing device, modify the storage policy to include the non-standard file path, and/or initiate a secondary copy operation to prevent data loss of the data stored in the non-standard file path. For example, a client computing device may execute a filter driver that monitors interactions with files in the file system. The filter driver can identify any non-standard file paths not subject to a storage policy that include files in which interactions occurred. For a non-standard file path, the filter driver can determine whether the frequency of interaction with files in the non-standard file path satisfies a threshold frequency. If the threshold is satisfied, then the filter driver may determine that the files should be subject to the storage policy and take appropriate action.

Abstract: A non-volatile storage system that is implementing a storage region (e.g., a persistent memory region) which is accessible to a host (e.g., via a PCIe connection) and a cache for the storage region shares details of the structure of the storage region and/or the cache (e.g., cache segment size). With awareness of the shared details of the structure of the storage region and/or the cache, the host arranges and sends out requests to read data from the persistent memory region in a manner that takes advantage of parallelism within the non-volatile storage system. For example, the host may initially send out one read request per cache segment to cause the non-volatile storage system to load the cache. Subsequently, additional read requests are made to the non-volatile storage system, with the data already loaded (or starting to load) in the cache, thereby increasing performance.

Abstract: A semiconductor package provided. The semiconductor package includes an interposer layer including a first surface and a second surface opposing each other, a first semiconductor chip and a second semiconductor chip on the first surface of the interposer layer, and a block copolymer film on the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are different from each other. The block copolymer film includes a first pattern and a second pattern, which are different from each other, and one of the first pattern and the second pattern contains graphite.

Abstract: A method may comprise, on a basic input/output system (BIOS), executing a hardware attestation verification application configured to: (a) during a first boot session of the information handling system comprising the BIOS, execute a first stage of an update to the information handling system and securely record a platform state record associated with beginning of execution of a second stage of the update; and (b) during a second boot session of the information handling system: (i) obtain the platform state record; (ii) compare the platform state record to an actual platform state during boot process of the second boot session; and (iii) if the platform state record matches the actual platform state during boot process of the second boot session, permit execution of the second state of the update.

Abstract: Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.

Abstract: Various embodiments described herein provide for adjusting (e.g., increasing) buffer memory space, provided by memory (e.g., active memory) of a memory sub-system used to store logical-to-physical memory address (L2P) mapping data, by reducing the amount of L2P mapping data stored on the memory.

Abstract: An image processing apparatus includes a first memory, a second memory, and a processor configured to write data related to a processing instruction that is inputted into the apparatus to the second memory instead of the first memory when a write lifetime of the first memory is less than a first lifetime threshold, based on state information about a state of the first memory.

Abstract: A first data block on a storage device including a data structure of deallocated data blocks on the storage device and a corresponding program erase count value for each of the deallocated data blocks is identified. A determination as to whether a second data block from the data structure of deallocated data blocks remains deallocated after being added to the data structure of deallocated data blocks based on the program erase count value is made. The data is stored at the second data block upon determining that the second data block remains deallocated after being added to the data structure of deallocated data blocks.

Abstract: Space allocation for non-volatile memory is shown. A controller establish a first namespace set by allocating the non-volatile memory in units of a first storage unit, and establishes a second namespace set by allocating the non-volatile memory in units of a second storage unit. The first storage unit is bigger than or equal to the second storage unit, and the first storage unit has better input and output isolation than the second storage unit. The first namespace set and the second namespace set are in the different tiers in a hierarchical storage architecture.

Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

Abstract: An apparatus comprising memory access circuitry to perform a tag-guarded memory access in response to a received target address and methods of operation of the same are disclosed. In the tag-guarded memory access a guard-tag retrieval operation seeks to retrieve a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the received target address, and a guard-tag check operation compares an address tag associated with the received target address with the guard tag retrieved by the guard-tag retrieval operation. When the guard-tag retrieval operation is unsuccessful in retrieving the guard tag, a substitute guard tag value is stored as the guard tag in association with the block of one or more memory locations comprising the addressed location identified by the target address.

Abstract: Scheduling data replication operations, including: identifying, for each of a plurality of target storage systems, an amount of data to be transferred from one or more source storage systems in order to fully replicate a dataset to the target storage system; scheduling, based on the amount of data to be transferred from one or more source storage systems in order to fully replicate the dataset to each of the target storage systems, replication operations between the storage systems; and replicating the dataset from the one or more source storage systems to each of the target storage systems in accordance with the scheduling of replication operations between the storage systems.

Abstract: Techniques for reducing data log recovery time and metadata write amplification when checkpointing a data log of a storage object in a distributed storage system are provided. In one set of embodiments, a node of the system can determine whether the data log has reached a first threshold size, where the data log comprises a plurality of data log records, and where each data log record includes data and metadata for a write request directed to the storage object. If the data log has reached the first threshold size, the node can copy, from each of the plurality of data log records, the metadata for the write request to a corresponding metadata log entry in a metadata log of the storage object. The node can then truncate the data log by removing the plurality of data log records.

Abstract: A processing system of a storage network operates by: sending, to at least one storage unit of the storage network, at least one read request corresponding to at least a read threshold number of a set of encoded data slices to be retrieved, wherein the set of encoded data slices correspond to a data segment, wherein the data segment is coded in accordance with dispersed error coding parameters that include a write threshold number and the read threshold number, wherein the write threshold number is a number of encoded data slices in the set of encoded data slices and wherein the read threshold number is a number of the set of slices that is required to decode the data segment; receiving, via the at least one processing circuit and from the at least one storage unit, a first subset of encoded data slices of the set of encoded data slices, wherein the first subset of encoded data slices is missing at least one missing encoded data slice that was not received from the at least one storage unit in response to the

Abstract: The present disclosure includes apparatuses and methods updating a register in memory. An example includes an array of memory cells; and a controller coupled to the array of memory cells configured to perform logical operations on data stored in the array of memory cells using a register that is updated to access the data stored in the array of memory cells.

Abstract: At least one processing device receives a create-token command from a host device. Responsive to receipt of the create-token command, the processing device creates the token, generates an in-memory snapshot of data in one or more logical address ranges of one or more source storage volumes, associates the in-memory snapshot with the token, and provides the token to the host device. The processing device receives a write-via token command from the host device, the write-via-token command specifying the token and one or more logical address ranges of one or more target storage volumes. Responsive to receipt of the write-via-token command, the processing device determines whether or not differential metadata of the storage system includes one or more entries for the one or more logical address ranges of the one or more source storage volumes, and controls execution of the write-via-token command based at least in part on the determination.

Abstract: A transfer device (230) for communicating with a first processing device (110 or 210) and a second processing device (210 or 110) by PCIe is provided. The transfer device (230) is provided with a direct memory access controller (DMAC) (233) for controlling a data transfer from a first memory (120 or 220) of the first processing device to a second memory (220 or 120) of the second processing device; a first transmission descriptor controller (235 or 237) for acquiring, from the first processing device, information relating to a first memory address in the first memory at which the data to be transferred is stored; and a first reception descriptor controller (234 or 236) for acquiring, from the second processing device, information relating to a second memory address in the second memory at which the data to be transferred should be stored.

Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

Abstract: A method, computer program product, and computing system for generating a pair of protocol endpoints within each storage system of a pair of storage systems. One protocol endpoint of the pair of protocol endpoints may be dedicated to each storage system of the pair of storage systems. One or more IO requests may be processed between one or more hosts and one or more virtual volumes within the pair of storage systems via the pair of protocol endpoints.

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

Abstract: An operating method of a memory controller may include receiving a state analysis request of a memory from a host, determining a fragment state of the memory, determining a lifespan situation of the memory, generating an analysis result indicating whether a garbage collection is restricted, on the basis of the fragment state and the lifespan situation, and providing the analysis results to the host.

Abstract: The described technology is generally directed towards efficiently organizing data in a single, non-distributed database as an associated array of key-value pairs implemented on top of a storage medium that allows only data appends. A table segment in an append-only storage medium is accessed by table keys. The table keys are hashed into key values used to access information in an attribute index (a search tree) that contains offsets to the table segment entries. Hashing the table keys can result in a series of hash parts, including a primary hash part corresponding to a node in the attribute index, and as needed in the event of hash collisions, secondary hash parts that map to child nodes in the attribute index.

Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the memory device, to perform operations that include, generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and responsive to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells of the plurality of word lines to a plurality of data states in a multi-pass programming operation. A later programming pass of the multi-pass programming operation includes a plurality of programming loops with incrementally increasing programming pulses. For at least one data state, the later programming pass includes maintaining a count of the programming loops of the later programming pass. The later programming pass also includes inhibiting or slowing programming of the memory cells being programmed to one of the data states during a predetermined program count verify (PCV) programming loop and a PCV?1 programming loop and skipping a verify operation for all programming loops prior to a PCV+1 programming loop.

Abstract: A storage system erases blocks of memory prior to writing data to the blocks. Instead of erasing the blocks at the time the write operations are executed, the storage system pre-erases the blocks, which can improve performance. However, because program failure errors can occur if the blocks sit empty for a relatively-long period of time prior to programming, the storage system pre-erases the blocks upon a prediction that a host will send sequential write commands to the storage system that will use the blocks. Additionally or alternatively, the storage system can pre-erase a block upon determining that the number of write commands in a command queue in the storage system is above a threshold that represents a number of write commands needed to fill the block with data.

Abstract: A last-level collective hardware prefetcher (LLCHP) is described. The LLCHP is to detect a first off-chip memory access request by a first processor core of a plurality of processor cores. The LLCHP is further to determine, based on the first off-chip memory access request, that first data associated with the first off-chip memory access request is associated with second data of a second processor core of the plurality of processor cores. The LLCHP is further to prefetch the first data and the second data based on the determination.

Abstract: An information processing apparatus and method capable of minimizing influences affecting business activities and dynamically changing the configuration of a storage apparatus in response to scale-out of hosts are proposed.

Abstract: A method is provided for performing transaction processing in a system that includes a plurality of nodes. Each of the nodes include a processor, an application executing in the processor, and an instance of a database used by the application. Each node executes transactions. At least two of the nodes are dynamically selected to receive the same request to process a transaction, and the processor at each of the at least two nodes executes and validates the same request to process a transaction. One or more of the at least two nodes replicates the same request, steps and operations, and/or indicia of the transactions to one or more other nodes in the system.

Abstract: Systems and methods for dynamically moving virtual machine (VM) data based upon context are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: select a VM having a plurality of VM files; identify, among the plurality of VM files, a movable VM file; and transfer the movable VM file from a first storage tier to a second storage tier based upon a usage classification associated with the movable VM file.

Abstract: Systems and methods are disclosed for retrieving, from a database, over a network, historical routing data for multiple attributes and determining, for each attribute, based on its respective historical routing data, whether processing volume and processing error rates for each attribute exceed respective threshold. If both processing volume and error rate exceed their respective thresholds, the systems and methods describe herein calculate, for each qualifying attribute, a degree to which routing for each attribute can be improved. The systems and methods described herein output a ranking for each qualifying attribute based on their respective degrees to which routing can be improved for the respective attributes.

Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

Abstract: Apparatuses and methods related to logging failed authentication attempts. Failed authentication attempts can be logged in the circuitry by degrading the circuitry. The degradation can signal a fail authentication attempt while an amount of the degradation can represent a timing of the error.

Abstract: A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating con

Abstract: An information processing apparatus including: a first management data storing region that stores a plurality of first links being provided one for each of multiple calculating cores and representing an order of migration of pages of a page group allocated to the calculating core among a plurality of the pages; a second management data storing region that stores a second link being provided for an operating system and managing a plurality of pages selected in accordance with the order of migration among the page group of the plurality of first links as a group of candidate pages to be migrated to the second memory; and a migration processor that migrates data of a page selected from the group of the second link from the first memory to the second memory. With this configuration, occurrence of a spinlock is reduced, so that the load on processor is reduced.

Abstract: A method and apparatus with a data storage device receives a data write request that is sent by a first tenant, and determines, from a plurality of resource zones (RZs) and based on the data write request and storage permission of the first tenant for each of the plurality of RZs. The data storage device further determines distribution of N duplicates in the at least one RZ based on the data write request and a first data distribution policy, and stores the N duplicates into at least one node corresponding to the at least one RZ based on distribution of the N duplicates in the at least one RZ and a second data distribution policy.

Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.

Abstract: According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.