Abstract: An information processing device according to the present invention includes an operation unit that outputs an access request, a storage unit including a plurality of connection ports and a plurality of memories capable of a simultaneous parallel process that has an access unit of a plurality of word lengths for the connection ports, and a memory access control unit that distributes a plurality access addresses corresponding to the access request received for each processing cycle from the operation unit, and generates an address in a port including a discontinuous word by one access unit for each of the connection ports.

Abstract: The storage system includes first and second disk arrays. The first disk array has a first port coupled to a second port of the second disk array, a port controller controlling the first port, a plurality of disk devices to store data, and a controller managing a plurality of logical units on the plurality of disk drives. The first port controller controls the first port so as to execute, in a time-sharing manner, data transfer corresponding to a initiator task and data transfer corresponding to a target task. The initiator task is generated to execute the data transfer from a first logical unit on the plurality of disk drives of the first disk array to a second logical unit on a plurality of disk drives of the second disk array. The target task is generated to execute the data transfer to receive data from the second disk array.

Abstract: Methods of protecting cache data are provided. For example, various methods are described that assist in handling dirty write data cached in memory by duplication into other locations to protect against data loss. One method includes caching a data item from a data source in a first cache device. The data item cached in the first cache device is designated with a first designation. In response to the data item being modified by a data consumer, the designation of the data item in the first cache device is re-assigned from the first designation to a second designation, and the data item with the second designation is copied to a second cache device.

Abstract: An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.

Abstract: An apparatus including: a plurality of multi-level memory cells configured to store data, wherein one or more of the multi-level memory cells are designated as pilot memory cells, and wherein each pilot memory cell is configured to store known, pre-determined data; an estimation block configured to, based on the known, pre-determined data, determine (i) estimated mean values of level distributions of the multi-level memory cells and (ii) estimated standard deviation values of level distributions of the multi-level memory cells; and a computation block configured to compute at least optimal or near optimal detection threshold values of level distributions of the multi-level memory cells based, at least in part, on (i) the estimated mean values and (ii) the estimated standard deviation values, wherein the optimal or near optimal detection threshold values are to be used in order to facilitate reading of the data stored in the multi-level memory cells.

Abstract: A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.

Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: An apparatus and system for protecting memory of a virtual guest includes initializing a virtual guest on a host computing system. The host computing system includes a virtual machine manager that manages operation of the virtual guest. The virtual guest includes a distinct operating environment executing in a virtual operation platform provided by the virtual machine manager. The method includes receiving an allocation of run-time memory for the virtual guest, the allocation of run-time memory comprising a portion of run-time memory of the host computing system. The method includes setting, by the virtual guest, at least a portion of the allocation of run-time memory to be inaccessible by the virtual machine manager.

Abstract: A method for maintaining a cache of dynamically generated objects. The method includes storing in the cache dynamically generated objects previously served from an originating server to a client. A communication between the client and server is intercepted by the cache. The cache parses the communication to identify an object determinant and to determine whether the object determinant indicates whether a change has occurred or will occur in an object at the originating server. The cache marks the object stored in the cache as invalid if the object determinant so indicates. If the object has been marked as invalid, the cache retrieves the object from the originating server.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Abstract: Embodiments include methods, apparatus, and systems for managing resources in a storage system. One embodiment includes a method that discovers storage resources for arrays in a cluster storage system. A table defines how the resources are divided among the arrays and is provided to the arrays so each array can identify which resources to manage.

Abstract: A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from which data should be read, and a write pointer to indicate a particular one of the plurality of buffers to which data should be written. The write pointer points at least one buffer ahead of the buffer to which the read pointer is pointing. An electronic system and a telecommunications system are further disclosed.

Abstract: The method for protecting memory of a virtual guest includes initializing a virtual guest on a host computing system. The host computing system includes a virtual machine manager that manages operation of the virtual guest. The virtual guest includes a distinct operating environment executing in a virtual operation platform provided by the virtual machine manager. The method includes receiving an allocation of run-time memory for the virtual guest, the allocation of run-time memory comprising a portion of run-time memory of the host computing system. The method includes setting, by the virtual guest, at least a portion of the allocation of run-time memory to be inaccessible by the virtual machine manager.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: To increase the efficiency of a running application, it is determined whether using a cache or directly a storage is more efficient block size-specifically; and the determined memory type is used for a data stream having a corresponding block size.

Abstract: A method for automatically optimizing an allocation amount for a data set includes receiving an extend request, specifying an allocation amount, for a data set in a storage pool. The method increments a counter in response to receiving the extend request. In the event the counter has reached a threshold value, the method automatically increases the allocation amount of the extend request, such as by multiplying the allocation amount by a multiplier. In the event the allocation amount is larger than a largest free extent in the storage pool, the method automatically decreases the allocation amount of the extend request to correspond to the largest available free extent. Such a method reduces or eliminates the chance that an extend request will fail, and reduces overhead associated with extending and consolidating extents. A corresponding apparatus and computer program product are also disclosed herein.

Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).

Abstract: Systems and processes may include a first memory and a second memory. A driver and/or an application may be stored in the first memory. Flash memory type data of the first memory may be stored in the second memory. The driver may control the first memory at least partially based on the flash memory type data. The first memory may be exchanged for a third memory. The driver may be stored on the third memory. The flash memory type data for the third memory may be stored on the second memory.

Abstract: A virtual disk is comprised of segments of unused capacity of physical computer-readable storage media co-located with computing devices that are communicationally coupled to one another through network communications. The computing devices execute one or more of a client process, a storage process and a controller process. The controller processes manage the metadata of the virtual disk, including a virtual disk topology that defines the relationships between certain ones of the physical computer-readable storage media and a particular virtual disk. The client process provide data for storage to certain ones of the computing devices executing the storage processes, as defined by a virtual disk topology, and also read data from storage from those computing devices. The client process additionally expose the virtual disk in the same manner as any other computer-readable medium.

Abstract: A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

Abstract: Techniques for reducing storage space and detecting corruption in hash-based applications are presented. Data strings are hashed or transformed into numerically represented strings. Groupings of the numeric strings form a set. Each numeric string of a particular set is associated with a unique co-prime number. All the numeric strings and their corresponding co-prime numbers for a particular set are processed using a Chinese Remainder Theorem algorithm (CRT) to produce a single storage value. The single storage value is retained in place of the original numeric strings. The original numeric strings can be subsequently reproduced and verified using the single storage value and the co-prime numbers.

Abstract: A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.

Abstract: A method, system, and computer program product for preemptive page eviction in a computer system are provided. The method includes identifying a region in an input file for preemptive page eviction, where the identified region is infrequently accessed relative to other regions of the input file. The method also includes generating an output file from the input file, where the identified region is flagged as a page for preemptive page eviction in the output file. The method further includes loading the output file to a memory hierarchy including a faster level of memory and a slower level of memory, wherein the flagged page is preemptively written to the slower level of memory.

Abstract: Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.

Abstract: A method for operating a host device includes inserting a plug-in adapter, having a subscriber identity module (SIM) component disposed thereon, into a host receptacle of the host device. A memory card is inserted into a memory receptacle on the plug-in adapter. After inserting the plug-in adapter and the memory card, communications are conveyed between the host device and the SIM component via the adapter and the memory card.

Abstract: An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.

Abstract: A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.

Abstract: An information processing system includes: a storage device storing information including settings information configured to an information processing apparatus, attribute management information indicating whether each settings information item is limited information with an update limit to the settings information or non-limited information without an update limit to the settings information, and apparatus specification information for specifying the information processing apparatus; and an information processing apparatus including an input unit reading information from the storage device when the storage device is connected, a determining unit comparing the apparatus specification information read by the input unit with the apparatus specification information for specifying the information processing apparatus stored in a storage unit and determines whether the apparatus settings information read by the input unit is identical to the apparatus settings information of the information processing apparatus, a

Abstract: Example embodiments of the present invention provide a method, apparatus and computer-program product for application migration validation. In short, example embodiments of the present invention provide a tool to be run by an administrator prior to migration to determine a pre-migration policy. The administrator then performs the migration. After the migration is complete, the administrator runs to tool again to determine a post-migration policy. The tool then validates the post-migration policy. For example, the tool may compare the pre-migration policy and the post-migration police to determine whether there are differences between the pre-migration policy and the post-migration policy. Alternatively, the tool may compare the post-migration policy against a changed policy, different from the pre-migration policy, deliberately implemented by the administrator. The tool may alert on differences between the pre-migration policy and the desired post-migration policy (i.e.

Abstract: A system comprises a first storage system, a second storage system, a plurality of switches, and a server connected with the first storage system via a first group of switches and connected with the second storage system via a second group of switches. The first group and the second group have at least one switch which is not included in both the first and second groups. The first storage system receives I/O commands targeted to first logical units from the server via the first group of switches. The first storage system maintains first information regarding the ports of both the first and second storage systems. The first information is used to generate multipath communication between the server and the first storage system, including at least one path which passes through the second storage system and at least one other path which does not pass through the second storage system.

Abstract: A memory access control device for controlling access to a plurality of memory devices with differing latency, controls, when performing a first access and then a second access, the timing of performing the second access, according to a memory device accessed in the first access and a memory device accessed in the second access.

Abstract: A storage apparatus and method, a program, and a playback apparatus and method, capable of quickly reading a specific part of data among metadata including metadata associated with faces. A storage controller controls storing face metadata in a storage medium, wherein the face metadata includes a content data set added for each content, content data storage location information indicating the storage location of the content data set, a detected face data set associated with each of face images detected from a content, and detected face data storage location information indicating the storage location of the detected face data set, and wherein the face metadata is configured such that the content data storage location information and face block storage location information indicating the storage location of the detected face data storage location information are described in a single data set. The present invention is applicable to a digital camera.

Abstract: A storage subsystem coupled to a host computer is described. The storage subsystem includes storage devices and first and second storage apparatuses that control data transfer between the host computer and the storage devices. The first storage apparatus includes a first controller coupled to the host computer via a first host communication control unit and to the storage devices via a first storage device communication control unit. The second storage apparatus includes a second controller coupled to the host computer via a second host communication control unit and to the storage devices via a second storage device communication control unit. At least one of the controllers monitors a status of the first host communication control unit and the storage device communication control units, and, if the status of the first storage device communication unit indicates failure, switch communication paths for transferring data from the host computer to the storage devices.

Abstract: Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write command when a write signal is applied to the write signal connection during an edge of the system clock signal.

Abstract: Described is a technology by which a virtual hard disk is migrated from a source storage location to a target storage location without needing any shared physical storage, in which a machine may continue to use the virtual hard disk during migration. This facilitates use the virtual hard disk in conjunction with live-migrating a virtual machine. Virtual hard disk migration may occur fully before or after the virtual machine is migrated to the target host, or partially before and partially after virtual machine migration. Background copying, sending of write-through data, and/or servicing read requests may be used in the migration. Also described is throttling data writes and/or data communication to manage the migration of the virtual hard disk.

Abstract: A detection module selects logically adjacent first and second control areas of a cluster. The detection module further determines that the first and second control areas satisfy a migration test wherein the first control area has free space exceeding a free threshold, the free space is at least equal to a space requirement for each second control area control interval, and the second control area has fewer control intervals than a control interval threshold. In addition, a copy module copies each second control area control interval to the first control area in response to determining that the first and second control areas satisfy the migration test.

Abstract: A memory address filter is configurable to emulate memory overrun performance of a legacy memory using an electronic memory of equal or greater capacity. The address filter includes a comparator configured to determine whether a target address is greater than a maximum legacy-address. Memory emulation at target address values greater than the maximum legacy-address value includes one or more of inhibiting the memory transaction; accomplishing the requested memory transaction at the maximum legacy-address value; and accomplishing the requested memory transaction at an address equivalent to the target address wrapped according to the maximum legacy-address value. In some embodiments, the address filter accepts one or more configuration parameters, such as memory depth, wrap-around, and overwrite enable.

Abstract: Systems and methods for balancing electronic mailboxes among databases communicatively coupled to an information handling system are disclosed. A method may include comparing an actual utilization values for a first database to a threshold utilization value for the first database and, depending upon the results, identifying the first database as over-utilized. The method may also include comparing an actual utilization values for a second database to a threshold utilization value for the second database and, depending upon the results, identifying the second database as under-utilized. The method may further include comparing a threshold usage value of a first electronic mailbox stored in the first database to an upper threshold usage value for the first electronic mailbox and, depending upon the results, identifying the first electronic mailbox as heavily-utilized. The method may also include moving the heavily-utilized electronic mailbox to the second database.

Abstract: As apparatus and associated method for a dual active-active array storage system with a first controller with top level control of a first memory space and a second controller with top level control of a second memory space different than the first memory space. A seek manager residing in only one of the controllers defines individual command profiles derived from a combined list of data transfer requests from both controllers. A policy engine continuously collects qualitative information about a network load to both controllers to dynamically characterize the load, and governs the seek manager to continuously correlate each command profile in relation to the load characterization.

Abstract: Time managed read and write access to a data storage device. As a part of time managed read and write access to a data storage device, a request for read and/or write access to the data storage device is accessed and it is determined whether the request for read and/or write access to the data storage device is to be granted. Based on the determination, read and/or write access to the data storage device is either allowed or blocked. If read and/or write access is allowed, read and/or write access is terminated after passage of a predetermined period of time.

Abstract: Systems and methods for backing up storage volumes are provided. One system includes a primary side, a secondary side, and a network coupling the primary and secondary sides. The secondary side includes first and second VTS including a cache and storage tape. The first VTS is configured to store a first portion of a group of storage volumes in its cache and migrate the remaining portion to its storage tape. The second VTS is configured to store the remaining portion of the storage volumes in its cache and migrate the first portion to its storage tape. One method includes receiving multiple storage volumes from a primary side, storing the storage volumes in the cache of the first and second VTS, migrating a portion of the storage volumes from the cache to storage tape in the first VTS, and migrating a remaining portion of the storage volumes from the cache to storage tape in the second VTS.

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Abstract: An improved sectored cache replacement algorithm is implemented via a method and computer program product. The method and computer program product select a cache sector among a plurality of cache sectors for replacement in a computer system. The method may comprise selecting a cache sector to be replaced that is not the most recently used and that has the least amount of modified data. In the case in which there is a tie among cache sectors, the sector to be replaced may be the sector among such cache sectors with the least amount of valid data. In the case in which there is still a tie among cache sectors, the sector to be replaced may be randomly selected among such cache sectors. Unlike conventional sectored cache replacement algorithms, the improved algorithm implemented by the method and computer program product accounts for both hit rate and bus utilization.

Abstract: The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.

Abstract: An apparatus and method is disclosed for a computer processor configured to access a memory shared by a plurality of processing cores and to execute a plurality of memory access operations in a transactional mode as a single atomic transaction and to suspend the transactional mode in response to determining an implicit suspend condition, such as a program control transfer. As part of executing the transaction, the processor marks data accessed by the speculative memory access operations as being speculative data. In response to determining a suspend condition (including by detecting a control transfer in an executing thread) the processor suspends the transactional mode of execution, which includes setting a suspend flag and suspending marking speculative data. If the processor later detects a resumption condition (e.g., a return control transfer corresponding to a return from the control transfer), the processor is configured to resume the marking of speculative data.

Abstract: Methods and apparatus relating to buffering in media and pipelined processing components are described. In one embodiment, a buffer may include an arbiter to receive data structure information from a producer, a memory to store the information, and an address generator to indicate a location in the memory to store the data structure information. Other embodiments are also disclosed.

Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual inline memory module (RDIMM) in which control signals are synchronusly buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.

Abstract: An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.