Abstract: A method of storing data on a data storage device having a cache, includes receiving, by the data storage device, a write command indicating a data portion and a range of addresses on the data storage device, the write command instructing the data storage device to write the data portion to each address in the range of addresses; and storing, in the cache, indicia that each address in the range of addresses comprises the data portion.

Abstract: A data processing apparatus may include a plurality of buffer units that stores data, a data write control unit that writes input data to any one of the plurality of buffer units by exclusively controlling the plurality of buffer units, and a data read control unit that reads data to be output from any one of the plurality of buffer units by exclusively controlling the plurality of buffer units. The data write control unit may output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may output a data read completion signal indicating that the reading of the data is completed when the reading of the data to be output is completed.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: An apparatus for storing or reading data in a memory array of a transponder and a corresponding transponder, read/write device and program element is described. Therein, a data file system for storing data within the memory array is defined by a predetermined protocol. The storing additional data includes checking whether a memory size of the application data file is larger than the memory size indicated by the application data length indicator; and storing second application data in a partial memory area of the application data file not occupied by the first application data. Thereby, memory areas which, according to the predetermined protocol, are not used can be used for new applications, data can be hidden in these areas such that they can not be read by protocol compliant reader devices and the data structure read or written is compatible with the former predetermined protocol.

Abstract: For data backup and recovery based on linked file repositories with each of the linked file repositories representing an individual file system capable of storing at least one version of a file and being connected to at least one server system, each of the linked file repositories are placed in a certain position for storing a certain version of the file. Each position of each of the linked file repositories is continuously numbered. A number of the versions of the file are determined by the position of the one of the linked file repositories. A version-movement process over each of the linked file repositories is implemented to perform a read operation of the at least one version of the file.

Abstract: A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

Abstract: The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.

Abstract: A constrained computing device is provided. The constrained computing device includes a memory, a processor coupled to the memory, and a journaling component executed by the processor in kernel mode. The journaling component is configured to receive information descriptive of a device control, allocate, in the memory, a variable record structured according to a variable definition associated with the device control, store the information within the variable record, receive updated information descriptive of the device control, allocate, in the memory, an update record structured according to an update variable definition, store the updated information within the update record, and link the variable record to the update record.

Abstract: Aspects of the disclosure provide for increasing the capacity of ternary content addressable memories (TCAMs). For example, one aspect provides a method for adding rules to a TCAM, wherein the TCAM comprises multiple configurable banks. According to this method, a range of candidate banks in which the proposed rule may be stored is identified based on a priority of the proposed rule, and one of the candidate banks is selected for storing the proposed rule based on a width of the proposed rule and widths of the candidate banks. Another aspect provides a method for deleting one or more rules from a TCAM comprising multiple configurable banks. According to this method, once the rule is deleted, the bank from which it was deleted may be reduced in width, and therefore increased in capacity. For example, wider rules stored in this bank may be relocated to other banks using the method for adding rules to a TCAM.

Abstract: An electronic component is provided having a plurality of functionalities. The electronic component comprises a control logic, and a non-volatile storage element. The control logic is coupled to the non-volatile storage element and is adapted for storing values in the non-volatile storage element based on an external input signal to the electronic component, each value being indicative for one or more functionalities of the plurality of functionalities. The control logic is adapted for controlling the availability of the plurality of functionalities based on one or more values stored in the non-volatile storage element and for outputting a confirmation signal being indicative for the availability of the plurality of functionalities.

Abstract: Methods and apparatus relating to a hardware and file system agnostic mechanism for achieving capsule support are described. In one embodiment, content associate with a capsule are stored in a non-volatile memory prior to a cold reset. A capsule descriptor may also be constructed, prior to the reset, which includes information about the physical location of the capsule content on the non-volatile memory. Other embodiments are also described and claimed.

Abstract: According to an embodiment, an information processing device that includes a first storage unit and a second storage unit having power consumption different from that of the first storage unit. The information processing device also includes a control unit configured to make a control to determine a priority of information that is to be stored in the first storage unit or the second storage unit. The control unit is configured to store the information into the first storage unit or into the second storage unit based on the determined priority.

Abstract: Multiple applications request data from multiple storage units over a computer network. The data is divided into segments and each segment is distributed randomly on one of several storage units, independent of the storage units on which other segments of the media data are stored. At least one additional copy of each segment also is distributed randomly over the storage units, such that each segment is stored on at least two storage units. This random distribution of multiple copies of segments of data improves both scalability and reliability. When an application requests a selected segment of data, the request is processed by the storage unit with the shortest queue of requests. Random fluctuations in the load applied by multiple applications on multiple storage units are balanced nearly equally over all of the storage units.

Abstract: A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in the translation lookaside buffer. The technique also includes translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.

Abstract: Embodiments described herein are directed to providing scalability to software applications. A computer system partitions a portion of data stored in a directory services system into multiple different data partitions. Each data partition includes a primary writable copy and at least one secondary read-only copy of the data. The computer system receives a client request for a portion of the data that is stored in the directory services system and accesses various stored partition mappings to determine which of the different data partitions includes the requested data. The computer system also accesses a dynamic copy locator to determine which of the read-only copies of the indicated partition to access and provide the accessed primary writeable copy of the indicated partition and the determined read-only copy to the client in a virtualized manner so that the client is not aware of the data partitions.

Abstract: A file storage apparatus comprises: duplication determination unit that determines whether file supplied from client apparatus and file stored in storage unit coincide with each other in same format, and stores the file supplied from client apparatus in the storage unit if the files do not coincide in the same format; and storage management unit that associates, if duplication determination unit determines that the files coincide in the same format, format of the file supplied from the client apparatus with the file stored in the storage unit, reads file stored in the storage unit in response to file read request from client apparatus, converts, if format associated with the read file exists, the read file into the format, and provides the converted file.

Abstract: To provide delayed updating of shared data, a concept of dualistic sequence information is introduced. In the concept, if during local modification of data, a modification to the data is published by another user, a local deviation is created, and when the modification is published, it is associated with an unambiguous sequence reference and the local deviation.

Abstract: A data storage system configured to efficiently manage system data, efficiently organize system data, and reduce system data redundancy is disclosed. In one embodiment, the data storage system can maintain memory allocation information configured to track defective allocation units. Memory allocation information can be further configured to provide information for locating the memory allocation units or memory locations in physical memory. Separate information that indicates locations of the data allocation units or memory locations and/or records defective memory locations may not be needed. Hence, redundancy can be reduced, efficiency can be increased, and improved performance can be attained.

Abstract: A RAID bad block module is added to a RAID controller. The bad block module intercepts bad block errors and marks them in a bad block table. When a bad block error is intercepted the bad block module logs the error and determines, based on the error and previously received errors logged in the table, whether the RAID controller can handle the error without failing the entire array. If so, the bad block module passes the error to the RAID controller. Else, the bad block module passes the error to an application or operating system where it is handled like any other disk error. Thus, instead of failing the entire array, the bad block errors are dealt with by the operating system.

Abstract: A method is used in reserving storage space in data storage systems. A set of logical units (LUs) predefined as file based storage hardware specific LUs are reserved in a restricted access storage space of a block based storage system. The restricted access storage space is accessed by a file based storage system for storing information required for initializing the file based storage system. The file based storage system is initialized using the information stored in the file based storage hardware specific LUs.

Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: determining that a first search value is associated with a first range field; determining a first bitmap associated with the first search value, wherein the first bitmap indicates at least one range encompassing the first search value; generating a search key based on the first bitmap; and accessing the ternary content addressable memory based on the search key.

Abstract: Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point.

Abstract: For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage.

Abstract: A method begins by a dispersed storage (DS) processing module concurrently receiving a first data stream and a second data stream for transmission to a receiving entity. The method continues with the DS processing module segmenting each of the first and second data streams to produce a first plurality of data segments and a second plurality of data segments, dividing one of the first plurality of data segments into a first plurality of data blocks, and dividing one of the second plurality of data segments into a second plurality of data blocks. The method continues with the DS processing module creating a data matrix from the first and second plurality of data blocks and generating a coded matrix from the data matrix and an encoding matrix. The method continues with the DS processing module outputting one or more pairs of coded values of the coded matrix to the receiving entity.

Abstract: After a file is stored in a storage device, the file is segmented into a first segment and a second segment, the latter of which is relocated to a removable security device only when the removable security device is connected to the storage device. After the removable security device is removed from the storage device, as long as the removable security device is kept by the owner of the file, the file cannot be accessible for someone other than the owner even if said someone takes the storage device. Security of the file is thus assured.

Abstract: In electronic equipment 1, a limitation level on reading data from a USB flash drive (storage device) 2 is set to a setting section 3 in advance. The USB flash drive 2 ascertains the setting at the setting section 3 when connected to the electronic equipment 1 and limits reading data based on the determined setting. If the limitation level does not match with the condition for permitting data read-out as determined in USB flash drive 2, the USB flash drive 2 prohibits the electronic equipment 1 from reading out data. By executing the processing for limiting data read-out at the side of the USB flash drive 2, unauthorized leakage of data can easily be prevented.

Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.

Abstract: A data storage apparatus acquires rule information that is used by the external device when performing data access and that defines a relation between the type of access operation and a data read condition, and status information including information for specifying data currently displayed on the external device, and indicates a current display status of the external device. Then, the data storage apparatus determines data to be pre-read from a storage medium and stored in a temporary data storage unit based on the rule information and the status information, and reads the determined data from the storage medium, and stores the read data in a temporary data storage unit. In the case where a data access request is received from the external device, if the requested data is stored in the temporary data storage unit, the requested data is read from the temporary data storage unit, and is output.

Abstract: The techniques introduced here provide for efficient management of storage resources in a modern, dynamic data center through the use of virtual storage appliances. Virtual storage appliances perform storage operations and execute in or as a virtual machine on a hypervisor. A storage management system monitors a storage system to determine whether the storage system is satisfying a service level objective for an application. The storage management system then manages (e.g., instantiates, shuts down, or reconfigures) a virtual storage appliance on a physical server. The virtual storage appliance uses resources of the physical server to meet the storage related needs of the application that the storage system cannot provide. This automatic and dynamic management of virtual storage appliances by the storage management system allows storage systems to quickly react to changing storage needs of applications without requiring expensive excess storage capacity.

Abstract: A semiconductor chip may be operable to receive and copy an OTP programming vector presented by the semiconductor chip programming device into its memory after it boots up from the boot read-only memory (ROM). The OTP programming vector which is a computer program may comprise an encrypted data to be programmed into the one-time programmable (OTP) memory in the semiconductor chip and may be signed with an electronic signature. The semiconductor chip may be operable to authenticate the OTP programming vector in the memory. The authenticated OTP programming vector in the memory may be executed to decrypt the data and program the data in a random data format into the OTP memory and then report the status via one or more general purpose input/output (GPIO) pins on the semiconductor chip.

Abstract: A newer generation game terminal according to one embodiment of the present invention is provided with a storage access control unit. The storage access control unit accesses a newer generation storage according to a request for access from an application designed to execute a synchronization process based on the assumption of a speed of access to an older generation storage. The storage access control unit estimates time required to access the older generation storage in accordance with an evaluation function for calculating the required time. The storage access control unit executes an adjustment process to fill a time gap between the time required to access the newer generation storage and time estimated to be required to access the older generation storage.

Abstract: A new data block to be stored in the dispersed storage system is received. When it is determined that a previous data segment contains sufficient space for the new data block, the previous data segment is retrieved from a plurality of dispersed storage units. A revised data segment is generated by aggregating the new data block with at least one existing data block of the previous data segment. A plurality of slices are generated for the revised data segment. The plurality of slices are stored in the plurality of dispersed storage units.

Abstract: A device is provided for use with a content provider that is operable to provide content, which includes a plurality of content components. The device includes a communication portion, a memory portion, a parsing portion, a counting portion and a processing portion. The communication portion can receive the content from the content provider. The parsing portion can parse the content into the plurality of content components and can store the parsed plurality of content components within the memory portion. The counting portion can provide a counter for each of the parsed plurality of content components within the memory portion, respectively. The processing portion can retrieve and process one of the parsed plurality of content components within the memory portion. The counting portion can further increment the counter associated with the retrieved one of the parsed plurality of content components within the memory portion.

Abstract: A computer system (a method) for providing storage management solution that enables server virtualization in data centers is disclosed. The system comprises a plurality of storage devices for storing data and a plurality of storage management drivers configured to provide an abstraction of the plurality of the storage devices to one or more virtual machines of the data center. A storage management driver is configured to represent a live disk or a snapshot of a live disk in a virtual disk image to the virtual machine associated with the driver. The driver is further configured to translate a logical address for a data block to one or more physical addresses of the data block through the virtual disk image. The system further comprises a master server configured to manage the abstraction of the plurality of the storage devices and to allocate storage space to one or more virtual disk images.

Abstract: A request for application information can be received from an application running in a process. The application information can be requested from an information repository, and received back from the repository in a first format. The application information can be converted to a second format, and passed to the application in the second format. In addition, the application information can be saved in the second format in a cache in the process. Also, when application information has been cached in response to a request for the information for a first user object, and a subsequent request for the application information for a second user object is received, it can be determined whether the second user object is authorized to access the application information. If so, then the application information can be fetched from the cache and returned for use by the second user object.

Abstract: Automatically aligning virtual blocks of partitions to blocks of underlying physical storage is disclosed. In some embodiments, a starting offset of a first partition included in a logical container is detected. In some embodiments, a misalignment correction amount for a first partition included in a logical container is detected. In some embodiments, a misalignment associated with a first partition included in a logical container is corrected.

Abstract: Techniques for implementing a multicast write command are described. A data block may be destined for multiple targets. The targets may be included in a list. A multicast write command may include the list. Write commands may be sent to each target in the list.

Abstract: In one embodiment, multiple content-addressable memory entries are associated with each other to effectively form a batch content-addressable memory entry that spans multiple physical entries of the content-addressable memory device. To match against this content-addressable memory entry, multiple lookup operations are required—i.e., one lookup operation for each combined physical entry. Further, one embodiment provides that a batch content-addressable memory entry can span one, two, three, or more physical content-addressable memory entries, and batch content-addressable memory entries of varying sizes could be programmed into a single content-addressable memory device. Thus, a lookup operation might take two lookup iterations on the physical entries of the content-addressable memory device, with a next lookup operation taking a different number of lookup iterations (e.g., one, three or more).

Abstract: Various implementations of shared upper level cache architectures for multi-core processors including a first subset of processor cores and a second subset of processor cores and a module configured to copy data from a first shared upper level cache memory to a second shared upper level cache memory are generally disclosed.

Abstract: A storage system and a method of control of a storage system including plural storage media, at least one SAS expander physically connected to each of the plural storage media and to a controller via plural parallel data channels, the controller being connected to a host CPU arranged in use to execute input/output operations to transfer data to and read data from the plural storage media, the method including: at the expander, varying the available bandwidth for communication with the plural storage media by varying the available number of the plural parallel data channels thereby providing control of the number of input/output operations executed by the host CPU.

Abstract: A memory module including memory devices, a spare memory device, a multiplexing unit, and a memory buffer is provided. The multiplexing unit is coupled with each of the memory devices and the spare memory device, while the memory buffer is coupled with the multiplexing unit. The memory buffer includes a serial interface over which commands are received from a memory controller. The memory buffer is configured to process the commands and provide the memory controller access to the memory device through the multiplexing unit in response to the commands. Also, in response to at least one of the commands, the memory buffer is configured to direct the multiplexing unit to couple the spare memory device to the memory buffer in place of one of the memory devices for at least a next access of the memory devices.

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract: To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract: Described are techniques for selecting a storage pool configuration. A set of one or more candidate storage pool configurations is determined. For each of the candidate storage pool configurations of the set, a reliability calculation is performed to determine a reliability value indicating reliability of the candidate storage pool configuration. For each of the candidate storage pool configurations of the set, an availability calculation is performed to determine an availability value indicating availability of the candidate storage pool configuration. In accordance with selection criteria, one of the candidate storage pool configurations of the set for a first storage pool is selected. The selection criteria includes the availability value and the reliability value for each of the plurality of candidate storage pool configurations.

Abstract: Decoding a content of interest with optimal power usage. In an embodiment, a central processing unit (CPU) retrieves the frames of a data stream of interest from a secondary storage and stores them in a random access memory (RAM). The CPU forms an index table indicating the locations at which each of the frames is stored. The index table is provided to a decoder, which processes the frames in sequence to recover the original data from the encoded data. By using the index information, the power usage is reduced at least in an embodiment when the decoding is performed by an auxiliary processor.

Abstract: Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.