Abstract: An information processing apparatus includes a processor including a first operation circuit that executes a product-sum operation, a second operation circuit that executes a certain operation, and a resister. The processor executes a first operation including the certain operation in a first layer in a neural network. The processor executes the first operation by a second method of calculating the certain operation by the second operation circuit, in a case where second operation time necessary for the first operation when the certain operation is executed by the second operation circuit is less than memory transfer time. Or the processor executes the first operation by a first method of calculating the certain operation by an approximate calculation by the first operation circuit, in a case where first operation time necessary for the first operation when executed by the first method is less than the memory transfer time.

Abstract: An open-channel storage device being configured to be controlled by a host including a bad block manager, the open-channel storage device including a buffer memory and a nonvolatile memory device. An operation method of the open-channel storage device includes performing a normal operation under control of the host, detecting a sudden power-off immediately after a program failure associated with a first data block among a plurality of memory blocks included in the nonvolatile memory device while the normal operation is performed, dumping a plurality of user data stored in the buffer memory to a dump block among the plurality of memory blocks in response to the detected sudden power-off, detecting a power-on, and performing a data recovery operation on the plurality of user data stored in the dump block in response to the detected power-on.

Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a liner on the MTJ; removing part of the liner to form a recess exposing the MTJ; and forming a conductive layer in the recess, wherein top surfaces of the conductive layer and the liner are coplanar. Preferably the MTJ further includes: a bottom electrode on the substrate, a fixed layer on the bottom electrode, and a top electrode on the fixed layer, in which the conductive layer and the top electrode are made of same material.

Abstract: An apparatus in one embodiment comprises at least one processing device configured to control delivery of input-output (IO) operations from a host device to a storage system over selected ones of a plurality of paths through a network, and to monitor response times for particular ones of the IO operations sent from the host device to the storage system. The at least one processing device is further configured to interact with the storage system to determine network latency from a viewpoint of the storage system, and responsive to (i) at least a subset of the monitored response times being above a first threshold and (ii) the network latency from the viewpoint of the storage system being above a second threshold, to at least temporarily modify a manner in which additional ones of the IO operations are sent from the host device to the storage system.

Abstract: A data storage device includes storage including a plurality of memory blocks and a controller configured to control operations of the plurality of memory blocks. The controller is configured to calculate a stress value of each of the plurality of memory blocks based on an erase completion count and an erase interruption count of the corresponding memory block.

Abstract: According to some embodiments, systems and methods are provided comprising receiving, via a communication interface of an authorization module comprising a processor, a part file with instructions to manufacture one or more parts with an additive manufacturing machine; generating a shape signature for the part based on the part file; providing a data store storing one or more stored shape signatures, wherein the one or more stored shape signatures are one of an authorized-to-print stored shape signature and an unauthorized-to-print stored shape signature; determining the generated shape signature of the part corresponds to at least one of the authorized-to-print stored shape signatures or at least one of the unauthorized-to-print stored shape signatures; and receiving the determination of whether the generated shape signature of the part corresponds to at least one authorized-to-print stored shape signature or at least one unauthorized-to-print stored shape signature. Numerous other aspects are provided.

Abstract: A system includes a non-volatile memory (NVM), and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone index; and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index for an active zone, wherein the zone write pointer includes a location in the LBA space for the active zone; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; and journal metadata of the entry of one the ZMDS or the HFUT affected by a flush transition between the ZMDS and the HFUT.

Abstract: A memory system includes: a plurality of memory devices; a plurality of cores suitable for controlling the plurality of memory devices, respectively; and a controller including: a host interface layer for providing any one of the cores with a request of a host based on mapping between logical addresses and the cores, a remap manager for changing the mapping between the logical addresses and the cores in response to a trigger, a data swapper for swapping data between the plurality of memory devices based on the changed mapping, and a state manager for determining a state of the memory system depending on whether the data swapper is swapping the data or has completed swapping the data, and providing the remap manager with the trigger based on the state of the memory system and a difference in a degree of wear between the plurality of memory devices.

Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.

Abstract: Methods that can provide distributed data deduplication reference counting are disclosed herein. One method includes generating, by a processor, a secondary reference in response to a determination that a data chunk is a copy of the primary reference in which the primary reference includes a pointer to an existing data chunk stored on a storage device. The method further includes incrementing a secondary reference counter on the primary reference in response to generating the secondary reference. Apparatus and computer program products that can include, perform, and/or implement the methods are also disclosed herein.

Abstract: A method, a computing device, and a non-transitory machine-readable medium for managing modes of operation for volumes in a node. A first portion of a plurality of volumes in a node is selected to operate in an active mode. A second portion of the plurality of volumes in the node is selected to operate in a passive mode. The second portion of the volumes that operates in the passive mode consumes fewer resources than the first portion of the volumes that operates in the active mode. The first portion of the plurality of volumes and the second portion of the plurality of volumes are adjusted over time based on activity of each volume of the plurality of volumes.

Abstract: To allow a time-series change among signal values to be recorded easily for a process of recording the respective time-series values of input signals, a recording device includes: a determination reference value obtaining section configured to obtain a determination reference value on a basis of signal values during a reference time period, the reference time period being a predetermined time period after a start of input of time-series signal values, the determination reference value indicating a feature of the signal values during the reference time period, and a recording control section configured to (i) obtain information on a recording start condition on a basis of the determination reference value, the recording start condition indicating whether, as compared to the signal values during the reference time period, there has been a large change among signal values after the reference time period has elapsed, and (ii) start recording signal values in response to the recording start condition becoming sati

Abstract: The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.

Abstract: A storage system and method for dynamic selection of a host interface are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a selection of a first host interface; in response to receiving the selection of the first host interface, implement the first host interface; after the first host interface has been implemented, receive, from the host, a selection of a second host interface; and in response to receiving the selection of the second host interface, implement the second host interface even though the first host interface was previously implemented. Other embodiments are provided.

Abstract: computer-based system and method for selecting a write unit size for a block storage device, includes performing a plurality of sequences of I/O operations to the block storage device, each sequence having a write unit size from a plurality of write unit sizes; collecting performance metrics of the sequences of I/O operations; and selecting the write unit size for the block storage device from the plurality of write unit sizes based on the performance metrics. In some cases, preconditioning is performed prior to performing the plurality of sequences of I/O operations by emptying the block storage device; and writing data to the block storage device to fill the block storage device above a predetermined level.

Abstract: An operation method is applied to a memory device. The memory device includes a plurality of memory tiles. The operation method includes following steps: utilizing a first wear leveling process to perform an intra-tile wear leveling on the plurality of memory tiles by a processor; and utilizing a second wear leveling process to perform an inter-tile wear leveling on the plurality of memory tiles by the processor.

Abstract: File system object storage is disclosed, including: receiving, via a communication interface, a request to perform a file system operation; determining a file system object associated with the request, wherein the file system object comprises two or more files; and performing the file system operation in a manner determined at least in part by data associated with the file system object.

Abstract: One embodiment provides a method for optimizing data read-ahead for machine learning applications including obtaining, by a processor, next file information from a workflow scheduler for next input files for a next processing stage that are to be accessed by a machine learning application. Data for the next processing stage for the machine learning application and at least one system job is prefetched. The next input files are prefetched as the prefetching data reaches an end of current inputs. A schedule is caused to chain the next input files for the next processing stage to current input files of a current processing stage.

Abstract: A computing device and method for providing a user interface for summarizing and presenting information regarding dynamic provisioning and deployment of media processing resources, in a manner that is easy and intuitive and analogizes well to conventional physical media processing deployment. Users are not required to understand hypervisor configuration or virtual machine deployment, or switch through various layers and screens to find configuration information or controls, a process that may be particularly slow, complex, and difficult to learn, particularly for media and broadcast engineers unfamiliar with virtualization technologies. Instead, the present user interface improves efficiency of use of the computing environment for media processing, by providing deployment information in a format similar to physical processing deployment.

Abstract: Aspects of the present disclosure relate to encryption management. An indication of a data set to be tagged with an encryption tag is received. A location for the encryption tag is determined. The encryption tag is stored at the location, where the encryption tag includes an encryption status indicator specifying whether or not the data is encrypted and an encryption algorithm indicator specifying an encryption algorithm used to encrypt the data.

Abstract: Provided is a vehicle brake system equipped with an electric brake and which has high reliability and enables redundancy at low cost. This vehicle brake system 1 is equipped with a mutually connected master controller 30 and first and second sub-controllers 40, 41, and an output cut-off control unit 200. Each of the controllers includes: a braking force calculation section for calculating the braking force of the electric brake; a self-determination section for determining whether or not the controller itself is normal; and an other-determination section for comparing the braking force calculation results of the controllers to determine whether the other two are normal.

Abstract: Example implementations described herein are directed to systems and methods for facilitating remote copy pair volume with data consistency. For a command received for one of a first volume and a second volume during execution of a pair synchronization process between the first volume and the second volume, example implementations can involve determining whether an address range of one of the first volume and the second volume configured to be provided to a host computer is to be locked based on the command; locking the address range of the one of the first volume and the second volume for the determination indicative of the address range of one of the first volume and the second volume is to be locked; and executing the command on the first volume and the second volume while the address range configured to be provided to the host computer is locked.

Abstract: A first storage node communicates with at least one second storage node. A physical disk included in the at least one second storage node is mapped as a virtual disk of the first storage node. The method may include: receiving a first write request, where the first write request carries first to-be-written data; striping the first to-be-written data to obtain striped data, and writing the striped data to a physical disk and/or the virtual disk of the first storage node; and recording a write location of the striped data. For example, the technical solution may be applied to a storage system that includes an NVMe SSD.

Abstract: A data storage device includes a nonvolatile memory device which includes a first nonvolatile memory group including a plurality of first nonvolatile memories coupled to a first flash translation layer (FTL) core and a second nonvolatile memory group including a plurality of second nonvolatile memories coupled to a second FTL core, and a controller including the first FTL core configured to write first user data transmitted from the host device and second metadata related to second user data in one among the plurality of first nonvolatile memories and a common memory.

Abstract: A trim command processing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a trim command from a host system, where the trim command is configured to indicate data stored in at least one logical address among a plurality of logical addresses can be erased; calculating a first data volume of data required to be programmed when a data trim operation is performed according to the trim command; and determining whether to perform a first trim operation or a second trim operation according to the first data volume.

Abstract: Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.

Abstract: The present invention provides a control method of multiple memory devices, wherein the multiple devices comprise a first memory device and a second memory device, and the control method includes the steps of: determining a first operation timing and a second operation timing according to at least a first command signal that a first memory controller needs to send to the first memory device; controlling the first memory controller to send the first command signal to the first memory device at the first operation timing; and controlling the second memory controller to send the second command signal to the second memory device at the second operation timing.

Abstract: A first current bin boundary for a first voltage bin on a first target die of a set of dies at a memory device is identified by accessing a block family metadata table including an entry for each block family of a memory device. The first current bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family corresponding to a first new bin boundary for the first voltage bin is determined. The first bin boundary is determined based on a calibration scan performed for the first voltage bin. A first new bin boundary for the first voltage bin is determined on each die of the set of dies based on the first bin boundary offset.

Abstract: A computer-implemented method includes writing a plurality of change records to a first set of redo records in a first transaction log file. The computer-implemented method further includes determining, while writing a change record to a redo record, that the change record includes changes made to data associated with an in-scope table. The computer-implemented method further includes updating the first transaction log file with information indicating that the redo record includes changes made to data associated with the in-scope table. The computer-implemented method further includes accessing the first transaction log file from storage in response to receiving a request for replicating changes made to data associated with in-scope tables. The computer-implemented method further includes scraping a first redo record in the first transaction log file in response to determining that the first redo record includes at least one change record associated with the in-scope table.

Abstract: Each object is associated with one root metadata record and one or more version-specific metadata records, each corresponding to a version of object data. A conditional command may be conditioned upon whether an object is stored in a storage system. Whether the condition is satisfied is determined based on whether a root metadata record of the object exists. If the condition is satisfied, then metadata is updated to reflect execution of the conditional command. A conditional command may be conditioned upon whether a data version identifier or a metadata version identifier equals a particular value. A conditional command execution engine retrieves the relevant version identifier from a version-specific metadata record, and performs a check on whether the condition is satisfied. If the condition is satisfied, the engine ensures that the version-specific record has not been modified during the check, and updates metadata to reflect execution of the conditional command.

Abstract: A storage device includes: a host interface to receive a host command from a host device over a storage interface; one or more memory translation layers to execute one or more operations associated with the host command to retrieve one or more chunks of data associated with the host command from storage memory; a bitmap circuit including a bitmap to track a constrained order of the one or more chunks of data to be transferred to the host device; and a transfer trigger to trigger a data transfer to the host device for the one or more chunks of data in the constrained order according to a state of one or more bits of the bitmap.

Abstract: Each object is associated with one root metadata record and one or more version-specific metadata records, each corresponding to a version of object data. A conditional command may be conditioned upon whether an object is stored in a storage system. Whether the condition is satisfied is determined based on whether a root metadata record of the object exists. If the condition is satisfied, then metadata is updated to reflect execution of the conditional command. A conditional command may be conditioned upon whether a data version identifier or a metadata version identifier equals a particular value. A conditional command execution engine retrieves the relevant version identifier from a version-specific metadata record, and performs a check on whether the condition is satisfied. If the condition is satisfied, the engine ensures that the version-specific record has not been modified during the check, and updates metadata to reflect execution of the conditional command.

Abstract: A storage access request to access a solid state drive (SSD) is received. A storage access timer is set with a time duration, where the time duration is based on a desired performance of the SSD. A non-volatile memory command associated with the storage access request is sent to non-volatile memory. The storage access timer is started. A determination is made whether the non-volatile memory completed execution of the non-volatile memory command after the storage access timer indicates that the time duration elapsed. An indication that the storage access request is complete is sent to a host if the non-volatile memory completed execution of the non-volatile memory command. Alternatively, the storage access timer is reset with the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.

Abstract: Various embodiments described herein provide for adjusting (e.g., increasing) buffer memory space, provided by memory (e.g., active memory) of a memory sub-system used to store logical-to-physical memory address (L2P) mapping data, by reducing the amount of L2P mapping data stored on the memory.

Abstract: In an in-memory database management system, non-volatile random access memories (NVRAMs) are used to store database data and control data. Because this data is stored in NVRAM, the data survives system failures. Recovery from a system failure may be accomplished more quickly by, at least in part, modifying the surviving data in NVRAM, rather than loading an entire checkpoint image and applying uncheckpointed transactions needed to synchronize the database. Because in this form of recovery the database state that serves as the starting point for applying change records is the database as stored in the NVRAM, this form of recovery is referred to herein as in-memory-based recovery. Recovery, where the database state that serves as the starting point for applying change records is a checkpoint image, is referred to herein as checkpointed-based recovery. In-memory-based recovery eliminates or reduces the need to perform certain operations that are performed for checkpointed-based recovery.

Abstract: A security tool analyzes database queries of internal users to determine if these users accessed information in a manner that deviates from established and/or expected access patterns. The security tool can also analyze the behavior of a group of internal users to determine whether that behavior deviates from expected access patterns. The security tool then determines security risks corresponding to the users' access. If any of the security risks exceeds a threshold, then the security tool takes remedial action (e.g., preventing one or more users from accessing information). In this manner, internal data breaches can be detected and prevented. Additionally, in certain embodiments, an internal data breach can be prevented before the internal data breach even occurs.

Abstract: Techniques for supporting replication and recovery of virtual volumes are provided. In various embodiments, these techniques can include workflows and application programming interfaces (APIs) that facilitate: (1) the provisioning of virtual volumes with metadata indicating that the virtual volumes should be replicated from one virtual volume-enabled storage array/site to another; (2) the discovery of a replication topology across virtual volume-enabled storage arrays/sites; (3) the orchestration of a test failover of a set of virtual volumes; and (4) the orchestration of an actual failover of a set of virtual volumes.

Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.

Abstract: Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.

Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.

Abstract: A sensing device and an electronic apparatus in which impairment of performance due to destruction of parameters can be reduced are to be provided. Parameters (sensor parameters 1 to n (n?1)) associated with sensors 1 to N (N?1) are stored in a ROM. A memory control unit reads out the sensor parameters 1 to n from the ROM and writes the sensor parameters into the RAM, and after that, carries out refresh processing to read out the sensor parameters from the ROM and overwrite the RAM with the sensor parameters in predetermined timing. A processing unit carries out signal processing of the sensors 1 to N based on the sensor parameters 1 to n written in the RAM.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

Abstract: In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping at a rank aggregator, the logical rank to one of a plurality of physical ranks at the memory modules, and forwarding the request to one of the memory modules according to the mapping. Two or more of the memory modules are combined to represent the number of logical ranks at the memory controller such that there is a one-to-one mapping between the logical ranks and the physical ranks. An apparatus for rank aggregation is also disclosed.

Abstract: A method is disclosed for providing memory bus timing of a load reduction dual inline memory module (LRDIMM). The method includes: determining a latency value of a dynamic random access memory (DRAM) of the LRDIMM; determining a modified latency value of the DRAM that accounts for a delay caused by a load reduction buffer (LRB) that is deployed between the DRAM and a memory bus; storing the modified latency value in a serial presence detector (SPD) of the LRDIMM; and providing memory bus timing for the LRDIMM based on the modified latency value, wherein the memory bus timing is compatible with a registered dual inline memory module (RDIMM).

Abstract: A method and system for self-sizing dynamic cache for virtualized environments is disclosed. The preferred embodiment self sizes unequal portions of the total amount of cache and allocates to a plurality of active virtualized machines (VM) according to VM requirements and administrative standards. As a new VM may emerge and request an amount of cache, the cache controller reclaims currently used cache from the active VM and reallocates the unequal portions of cache required by each VM. To ensure cache availability, a quick reclamation amount of cache is immediately available to each new VM as it makes the request begins operation. After reallocation, the newly created VM may rely on a guaranteed minimum quota of cache to ensure performance.

Abstract: Systems and methods for copy on write storage conservation are presented. In one embodiment a copy on write storage conservation method includes creating and mounting a snapshot; mounting a snapshot; monitoring interest in the snapshot; initiating a copy on write discard process before a backup or replication is complete; and deleting the snapshot when the backup or replication is complete. In one embodiment the method also includes marking a file as do not copy on write. In one embodiment, the copy on write discard process includes discarding copy on write data when a corresponding read on the file in the snapshot is successful. Initiating a copy on write discard process can be done at a variety of levels (e.g., a file level, an extent level, a block-level, etc.).

Abstract: An approach to efficient space reclamation in multi-layered thinly provisioned systems. A parent storage volume is thinly provisioned, and uses one or more child storage volumes that are also thinly provisioned for storage. A reclamation command sent to the device providing the parent thinly provisioned storage volume identifies that data has been released, and that the physical storage storing that data can be placed in a free pool and used to satisfy future write requests in the parent storage volume. An identify module identifies which child storage volumes supporting the parent storage volume are thinly provisioned. The data is released at the level of the parent storage volume, and the reclamation command is sent to the child storage volumes supporting the parent storage volume and that are themselves thinly provisioned. The storage is thus released by all affected thinly provisioned storage volumes, and not just the parent storage volume that received the reclamation command.

Abstract: A design structure for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.